DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 08/01/2024 have been accepted by the examiner.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 10/01/2024. The information disclosed therein was considered.
Claims 1-21 are presented for examination.
Allowable Subject Matter
A timely filed Terminal Disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome the non-statutory double patenting rejection of claims 1-21 of the invention.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-21 of 18/791456 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 & 16-22 of U.S. Patent NoUS11594280. Although the claims at issue are not identical, they are not patentably distinct from each other because, claims 1-21 of the current application are either anticipated, or would have been obvious over, by the claims 1-7 & 26-22 of U.S. Patent No US11594280, e.g., despite a slight difference in the current application ( having a plurality of third transistors are connected), Patent No US11594280, already teaches a third transistor and would be obvious to have a plurality of third transistors that are electrically connected in the circuit as a design choice. MPEP 2144.04.
Below is the chart showing the similarities (in bold) and differences between Claims 1-21, of the present application and claims 1-7 & 16-22 of U.S. Patent No 11594280.
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18/791456
US11594280
Claim 1,
An integrated circuit comprising: a content addressable memory array comprising a plurality of content addressable memory cells arranged in a plurality of rows and columns, wherein each said content addressable memory cell comprises: a first floating body transistor; a second floating body transistor; and a third transistor; wherein said first floating body transistor and said second floating body transistor are electrically connected in series through a common node; wherein said third transistor is electrically connected to said common node; wherein said first floating body transistor and said second floating body transistor store complementary data; wherein a plurality of said third transistors are electrically connected; and a control circuit configured to perform write operations to said content addressable memory array.
Claim 1,
An integrated circuit comprising: a content addressable memory array comprising a plurality of content addressable memory cells arranged in a plurality of rows and columns, wherein each said content addressable memory cell comprises: a first floating body transistor; a second floating body transistor; and a third transistor; wherein said first floating body transistor and said second floating body transistor are electrically connected in series through a common node; wherein said third transistor is electrically connected to said common node; wherein said first floating body transistor and said second floating body transistor store complementary data; and a control circuit configured to perform write operations to said content addressable memory array.
Claim 2,
wherein said first floating body transistor and said second floating body transistor comprise a buried well region
Claim 2,
wherein said first floating body transistor and said second floating body transistor comprise a buried well region.
Claim 3,
wherein said first floating body transistor and said second floating body transistor comprise a buried insulator region.
Claim 3,
wherein said first floating body transistor and said second floating body transistor comprise a buried insulator region.
Claim 4,
wherein said first floating body transistor comprises a first gate region and said second floating body transistor comprises a second gate region
Claim 4,
wherein said first floating body transistor comprises a first gate region and said second floating body transistor comprises a second gate region.
Claim 5,
wherein said first floating body transistor comprises a first conductivity type and said third transistor comprises said first conductivity type.
.
Claim 5,
wherein said first floating body transistor comprises a first conductivity type and said third transistor comprises said first conductivity type.
Claim 6,
wherein said first floating body transistor comprises a first conductivity type and said third transistor comprises a second conductivity type different from said first conductivity type
Claim 6,
wherein said first floating body transistor comprises a first conductivity type and said third transistor comprises a second conductivity type different from said first conductivity type.
Claim 7,
wherein said third transistor comprises a third floating body transistor.
Claim 7,
wherein said third transistor comprises a third floating body transistor.
Claim 8,
An integrated circuit comprising: a content addressable memory array comprising a plurality of content addressable memory cells arranged in a plurality of rows and columns, wherein each said content addressable memory cell comprises: a first floating body transistor; and a second floating body transistor; wherein said first floating body transistor and said second floating body transistor are electrically connected in series through a common node; wherein said first floating body transistor and said second floating body transistor store complementary data; and a third transistor; wherein a plurality of said third transistors are electrically connected; and a control circuit configured to perform write operations to said content addressable memory array.
Claim 1,
An integrated circuit comprising: a content addressable memory array comprising a plurality of content addressable memory cells arranged in a plurality of rows and columns, wherein each said content addressable memory cell comprises: a first floating body transistor; a second floating body transistor; and a third transistor; wherein said first floating body transistor and said second floating body transistor are electrically connected in series through a common node; wherein said third transistor is electrically connected to said common node; wherein said first floating body transistor and said second floating body transistor store complementary data; and a control circuit configured to perform write operations to said content addressable memory array.
Claim 9,
wherein said first floating body transistor and said second floating body transistor comprise a buried well region
Claim 2,
wherein said first floating body transistor and said second floating body transistor comprise a buried well region.
Claim 10,
wherein said first floating body transistor and said second floating body transistor comprise a buried insulator region.
Claim 3,
wherein said first floating body transistor and said second floating body transistor comprise a buried insulator region.
Claim 11,
wherein said first floating body transistor comprises a first gate region and said second floating body transistor comprises a second gate region
Claim 4,
wherein said first floating body transistor comprises a first gate region and said second floating body transistor comprises a second gate region.
Claim 12,
wherein said first floating body comprises a first conductivity type and said third transistor comprises said first conductivity type.
Claim 5,
wherein said first floating body transistor comprises a first conductivity type and said third transistor comprises said first conductivity type.
Claim 13,
wherein said first floating body transistor comprises a first conductivity type and said third transistor comprises a second conductivity type different from said first conductivity type.
Claim 6,
wherein said first floating body transistor comprises a first conductivity type and said third transistor comprises a second conductivity type different from said first conductivity type.
Claim 14,
wherein said third transistor comprises a third floating body transistor.
Claim 7,
wherein said third transistor comprises a third floating body transistor.
Claim 15,
An integrated circuit comprising: a content addressable memory array comprising a plurality of content addressable memory cells arranged in a plurality of rows and columns, wherein each said content addressable memory cell comprises: a first transistor having a first floating body; a second transistor having a second floating body; a third transistor; a first drain region contacting said first floating body; a second drain region contacting said second floating body; a first source region contacting said first floating body, spaced apart from said first drain region; and a second source region contacting said second floating body, spaced apart from said second drain region; wherein said first and second drain regions are electrically connected to each other; wherein said third transistor is electrically connected to said first and second drain regions; wherein said first floating body and said second floating body store complementary charge states; wherein a plurality of said third transistors are electrically connected; and a control circuit configured to perform write operations to said content addressable memory array.
Claim 16,
An integrated circuit comprising: a content addressable memory array comprising a plurality of content addressable memory cells arranged in a plurality of rows and columns, wherein each said content addressable memory cell comprises: a first transistor having a first floating body; a second transistor having a second floating body; a third transistor; a first drain region contacting said first floating body; a second drain region contacting said second floating body; a first source region contacting said first floating body, spaced apart from said first drain region; and a second source region contacting said second floating body, spaced apart from said second drain region; wherein said first and second drain regions are electrically connected to each other; wherein said third transistor is electrically connected to said first and second drain regions; and wherein said first floating body and said second floating body store complementary charge states; and a control circuit configured to perform write operations to said content addressable memory array.
Claim 16,
wherein said first transistor and said second transistor comprise a buried well region.
Claim 17,
wherein said first transistor and said second transistor comprise a buried well region.
Claim 17,
wherein said first transistor and said second transistor comprise a buried insulator region.
Claim 18,
wherein said first transistor and said second transistor comprise a buried insulator region.
Claim 18,
wherein said first transistor comprises a first gate region and said second transistor comprises a second gate region.
Claim 19,
wherein said first transistor comprises a first gate region and said second transistor comprises a second gate region.
Claim 19,
wherein said first transistor comprises a first conductivity type and said third transistor comprises said first conductivity type.
Claim 20,
wherein said first transistor comprises a first conductivity type and said third transistor comprises said first conductivity type.
Claim 20,
wherein said first transistor comprises a first conductivity type and said third transistor comprises a second conductivity type different from said first conductivity type.
Claim 21,
wherein said first transistor comprises a first conductivity type and said third transistor comprises a second conductivity type different from said first conductivity type.
Claim 21,
wherein said third transistor comprises a third floating body.
Claim 22,
Further comprising a fourth transistor, having a third floating body.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure Widjaja et al (US20100246277 Fig 24), Widjaja et al (US20120120752 Fig 4), Okhonin et al (US2011007578 fig 2).
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/MUNA A TECHANE/Examiner, Art Unit 2827