Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed August 1, 2024.
Status of claims to be treated in this office action:
a. Independent: 1, 12, 16
b. Pending: 1-20
Specification
The disclosure is objected to because of the following informalities:
In the Detailed Description section of the Specification, in para. [0044], make the following change:
“NOC[[’]]s can span synchronous and asynchronous clock domains…”
In the Detailed Description section of the Specification, in para. [0046], make the following change:
“Processor 156 may also be implemented as a translation module…”
In the Detailed Description section of the Specification, in para. [0063], since two die are being discussed but only one of them is a memory die, make the following change:
“This allows each of the its technology.”
In the Detailed Description section of the Specification, in para. [00126], make the following change:
“Referring now to FIG. 7B, the solid line curves 720, 722 are for the nominal temperature and the dashed curves 724, 726 are for high temperature with the same temperature compensation as was used for the freshly programmed cells.[[.]]”
In the Detailed Description section of the Specification, in para. [00127], make the following change:
“As will be described below, the target read levels are different for nominal temperature and high temperature and the temperature compensation was determined based on…”
Appropriate correction is required.
Claim Objections
Claims 4, 8, 11, 17-20 are objected to because of the following informalities:
Regarding claim 4, make the following change:
“set the Tco based on the shift in the threshold voltage distribution.”
Regarding claim 8, make the following changes:
“The apparatus of claim 1, wherein the one or more control circuits are configured to:
read the NAND memory cells in the selected block based on the set Tco during a normal read that uses prese[[n]]t values for read levels.”
Regarding claim 11 and claims 17-20, make the following change:
“wherein the one or more control circuits are configured to:”
Regarding claim 20, make the following change:
“read the second NAND memory cells in the selected block based on the bit line voltage Tco during a normal read that uses prese[[n]]t values for read levels.”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8, and 10 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Achtenberg et al. (US Pub. 20200159465 A1; “Achtenberg”).
Regarding independent claim 1, Achtenberg discloses an apparatus (Fig. 1A: data storage device 102; [0047]) comprising:
one or more control circuits (controller 120; [0058]; [0140]: One or more components described herein may include one or more physical components, such as hardware controllers, state machines, logic circuits, one or more other structures, or a combination thereof, to enable the data storage device 102 to perform one or more operations described herein) configured to connect to a NAND memory structure (memory device 103; [0144]: The memory device 103 may include a three-dimensional (3D) memory, such as a resistive random access memory (ReRAM), a flash memory (e.g., a NAND memory), the NAND memory structure having blocks ([0056]: The memory 104 may include one or more blocks, such as a NAND flash erase group of storage elements) having NAND strings and word lines associated with the NAND strings, the NAND memory structure having bit lines associated with the NAND strings ([0070]: FIG. 1B is a schematic diagram of one example of a 3D memory array 1310, such as a 3D or vertical NAND memory array or a BiCS2 cell array as shown. Memory array 1310 is made up of a plurality of pages 1390. Each page 1390 includes a set of NAND strings 1350 (four NAND strings are shown). Each set of NAND strings 1350 is connected in common to a global bit line 1380…A row of memory cells 1360A-1360N are connected in common to a word line (WL) 1370. The number of word lines 1370 (WL0, WL1, etc.) is dependent upon on the number of memory cells 1360A-1360N in a NAND string 1350), the one or more control circuits configured to:
measure a data retention impact to a data state of a group of NAND memory cells in a selected block of NAND memory cells since the group was programmed to the data state ([0031]: Devices and methods provide compensation for shifting and widening of Vt levels due to differences of programming temperatures as compared to reading temperature variations…a write temperature may be stored once for each programmed block (e.g., an erase block of an NAND flash memory); [0032]: during reading data, a “read temperature” for each read block or WL may be measured. One or more memory access parameters, such as read Vts, may be adjusted based on tracking the CVD, based on BER, based on tables that are based on the difference between the write temperature and the read temperature, or any combination thereof; regarding Fig. 17, per [0132]: At block 1720, the controller 120 determines a proxy vector (i.e., a single component proxy vector or multiple component proxy vector) for each memory cell identified at block 1710. The proxy vectors are determined in operation of data storage device 102. The proxy vectors are determined at the start of operations by making two or more measurements of Vts of each memory cell under two or more different read parameters. For example, two measurements of Vts of each memory cell under two different read parameters are made for a single component proxy vector, and three or more measurements of Vts of each memory cell under three or more different read parameters are made for a multiple component proxy vector. The proxy vectors measured in operation are related to a memory cell's specific physical characteristics, such as a cell's sub-threshold slope. Examiner concludes that the controller measures cell threshold voltages to determine the extent of the temperature effects since programming, and this may be performed on a block-level);
set a temperature coefficient (Tco) based on the data retention impact ([0134]: At block 1730, an estimated TCO or correction term ΔV per memory cell is determined based upon the proxy vectors at block 1720…the controller 120 may calculate a correction term per memory cell from proxy vectors at block 1730. For example, a matrix W and b may be obtained during offline memory characterization, such as offline characterization 1500 in reference to FIG. 15 and in reference to equation (6), and stored in non-volatile memory (such as ROM) of controller 120 or memory 104. The controller 120 may calculate a correction term based upon the stored matrix W and b); and
read NAND memory cells in the selected block based on the set Tco ([0009]: The method includes characterizing an estimated TCO value for each memory cell of one or more memory arrays…applying the proxy vector to determine a corrected Vt, and applying the corrected Vt to a read/write operation).
Regarding claim 8, Achtenberg discloses the limitations of claim 1, and further through Achtenberg:
the one or more control circuits (Fig. 1A: 120) are configured to:
read the NAND memory cells in the selected block based on the set Tco during a normal read that uses present values for read levels ([0040]: the controller may track the temperature range at which most of the traffic is being programmed and define this range as the “normal” temperature range; [0009]: characterizing an estimated TCO value for each memory cell of one or more memory arrays, where the characterization generates an offline look-up table, and where the look-up table correlates a single proxy to a single TCO value. Examiner asserts that a normal read is defined by a normal temperature range, and that the single proxy for a memory cell in a normal read operation will have a single set TCO value).
Regarding claim 10, Achtenberg discloses the limitations of claim 1, and further through Achtenberg:
wherein the one or more control circuits (Fig. 1A: 120) are configured to:
dynamically update read levels ([0099]: memory access parameters associated with the group may enable reliable reading and writing of data using the memory access parameters for the group. Adjustment of the memory access parameters, such as due to device usage or in response to temperature variation of the data storage device, may be performed by adjustment of the memory access parameters associated with the groups…The updating of the parameters of the different time and temperature groups may be done as maintenance operations performed in the background. Alternatively, the updating of parameters may be triggered by some event in the foreground (e.g., high BER observed during a host read)) based on the read of the NAND memory cells in the selected block based on the set Tco ([0009]); and
read NAND memory cells in the selected block based on the dynamically updated read levels and the set Tco ([0099]; [0009]).
Claims 1-3 and 8-10 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Lu et al. (US Pub. 20240096408 A1; “Lu”).
Regarding independent claim 1, Lu discloses an apparatus (Fig. 1A: computing system 100; [0019]) comprising:
one or more control circuits (memory sub-system controller 115; [0029]) configured to connect to a NAND memory structure ([0034]: An external controller (e.g., memory sub-system controller 115) can externally manage the memory device 130…An example of a managed memory device is a managed NAND (MNAND) device), the NAND memory structure having blocks having NAND strings and word lines associated with the NAND strings ([0053]: A block of memory cells can include those memory cells that are configured to be erased together, such as all memory cells connected to wordlines 202.sub.0-202.sub.N (e.g., all NAND strings 206 sharing common wordlines 202); [0046]: FIG. 2 is a schematic of portions of an array of memory cells 104, such as a NAND memory array, as could be used in a memory of the type described with reference to FIG. 1B), the NAND memory structure having bit lines associated with the NAND strings ([0053]: Although bit lines 204.sub.3-204.sub.5 are not explicitly depicted in FIG. 2, it is apparent from the figure that the bit lines 204 of the array of memory cells 104 can be numbered consecutively from bit line 204.sub.0 to bit line 204.sub.M), the one or more control circuits configured to:
measure a data retention impact to a data state of a group of NAND memory cells in a selected block of NAND memory cells since the group was programmed to the data state ([0014]: In many memory devices, the level separation in threshold voltages becomes further reduced (or shifted) due to changes in environmental conditions, such as cross-temperature effects, or data retention (i.e., the passage of time). Cross-temperature negatively impacts level separation in situations where the memory cell operates (e.g., is read) at a temperature range which is different from a temperature at which the memory cell was programmed. For example, cross-temperature effects can arise when data is read from a memory cell at a temperature that is different from the temperature at which data was written into the memory cell. Cross-temperature-induced errors can be accumulated by one or both of shifted levels that cross thresholds boundaries causing bit flip errors and/or overlapping levels causing increased number of bit flip errors; [0016]: a number of errors in one particular programming distribution (e.g., the highest voltage programming distribution among QLC memory cells) is determined at the start of the read operation, and the read voltage level can be adjusted based on the determined number of errors);
set a temperature coefficient (Tco) based on the data retention impact ([0017]: The voltage level of the strobe is set to target a specific programming distribution (i.e., level) so that a number of errors in that distribution can be determined and used to adjust one or more parameters for the remainder of the read operation (e.g., as part of a secondary calibration operation and/or to actually read the host data stored in memory cells configured as QLC memory). Control logic in the memory device can use the number of errors read from the one distribution of QLC memory cells and use that value to adjust one or more parameters of the read operation. For example, the control logic can adjust the read voltage level. In addition, the control logic can adjust one or more other trim settings, such as a bitline voltage (e.g., Vbl), a pass voltage applied to adjacent wordlines (e.g., Vpasslr), a read threshold voltage (e.g., V.sub.t) sensing time, or other parameters); and
read NAND memory cells in the selected block based on the set Tco ([0036]: Using the number of errors in that one distribution, local media controller 135 can determine (e.g., using a pre-populated data structure, such as a look-up table) a read level offset (i.e., an adjustment to a default read voltage level) to be used in both the second fine calibration operation and the host data read. In addition, local media controller 135 can use the number of errors determined in the first coarse calibration operation to adjust one or more parameters of the read operation. For example, using the same or a different data structure, local media controller 135 can identify and apply offsets to one or more other trim settings…Local media controller 135 can use these offsets when performing the second fine calibration operation, such as a parallel auto-read calibration (pARC) operation and when reading the host data stored in the memory cells of the selected wordline).
Regarding claim 2, Lu discloses the limitations of claim 1, and further through Lu:
the temperature coefficient (Tco) includes a bit line Tco for a bit line voltage during read ([0058]: Configuring the one or more parameters associated with the read operation comprises configuring one or more of a bitline voltage to be applied to a bitline of the memory array 104, such as one of bitlines 204.sub.0 to 204.sub.M, or a pass voltage (e.g., Vpasslr) to be applied to one or more wordlines adjacent to the target wordline in the memory array 104); and
the one or more control circuits (Fig. 1A:115) are configured to apply a voltage to the bit lines during the read of the NAND memory cells in the selected block based on the set Tco, wherein a magnitude of the bit line voltage depends on the bit line Tco ([0058]: In one embodiment, local media controller 135 can maintain a lookup table or other data structure storing a number of entries…Each entry can further include corresponding parameter values to be used when performing the read operation (e.g., a read voltage offset to be applied to a default read voltage, a bitline voltage offset to be applied to a default bitline voltage, a pass voltage offset to be applied to a default pass voltage); [0034]: In some embodiments, the memory devices 130 include local media controllers 135 that operate in conjunction with memory sub-system controller 115 to execute operations on one or more memory cells of the memory devices 130. Examiner concludes that the local media controllers 135 are one of the plurality of controllers. Also, Examiner concludes that the magnitude of the bitline voltage depends on the bitline Tco because the “offset to be applied to a default bitline” indicates a change to the bitline voltage is an offset that per [0036] is an adjustment amount applied to the parameters/trim settings).
Regarding claim 3, Lu discloses the limitations of claim 1, and further through Lu:
the temperature coefficient (Tco) includes a read pass Tco for a read pass voltage during read ([0058]); and
the one or more control circuits (Fig. 1A:115) are configured to apply a voltage to unselected word lines in the selected block during the read of the NAND memory cells in the selected block based on the set Tco, wherein a magnitude of the unselected word line voltage depends on the read pass Tco ([0058]).
Regarding claim 8, Lu discloses the limitations of claim 1, and further through Lu:
the one or more control circuits (Fig. 1A:115) are configured to:
read the NAND memory cells in the selected block based on the set Tco during a normal read that uses present values for read levels ([0036]: local media controller 135 can selectively take corrective action to adjust the read voltage level (e.g., apply a read voltage offset to a default read voltage level) and other parameters only when necessary, and can prevent the added latency in completing the read operation associated with both taking unwarranted corrective action).
Regarding claim 9, Lu discloses the limitations of claim 1, and further through Lu:
wherein the one or more control circuits (Fig. 1A:115) are configured to:
perform a valley scan search during the read of the NAND memory cells in the selected block ([0036]: the memory array 104 can be logically or physically divided into a number of segments (e.g., dies, blocks, pages, etc.). When performing a read operation on one of those segments, local media controller 135 can perform one or more enhanced valley tracking operations) based on the set Tco ([0036]: In one embodiment, the enhanced valley tracking operations can include a first coarse calibration operation and a second fine calibration operation. For example, the first coarse calibration operation can include a failed byte count read operation (e.g., a digital Cfbyte operation), where local media controller 135 can cause a failed byte count strobe signal to be applied to one or more wordlines of memory array 104 to read the number of errors in one distribution of xLC (e.g., TLC, QLC) memory cells in the memory array 104. Using the number of errors in that one distribution, local media controller 135 can determine (e.g., using a pre-populated data structure, such as a look-up table) a read level offset (i.e., an adjustment to a default read voltage level) to be used in both the second fine calibration operation and the host data read. In addition, local media controller 135 can use the number of errors determined in the first coarse calibration operation to adjust one or more parameters of the read operation), the valley scan search comprising reading at a plurality of read levels associated with a data state ([0059]: performing the second fine valley tracking calibration operation comprises performing a parallel auto-read calibration (pARC) operation on the segment of the memory array 104. In a parallel auto-read calibration operation, local media controller 135 can perform a sequence of read operations at different read voltage levels, but starting at and centered on the read voltage level configured based on the results of the first coarse valley tracking calibration operation. Local media controller 135 can generate a histogram representing the error counts from that sequence of read operations and use the histogram to identify the mid-point of the valley between two adjacent programming distributions); and
determine a new read level for the data state based on a read level in the valley scan search having a lowest fail bit count (FBC) ([0059]. Examiner asserts that the mid-point of the valley identified from the histogram is analogous to the “read level in the valley scan search having a lowest fail bit count”).
Regarding claim 10, Lu discloses the limitations of claim 1, and further through Lu:
wherein the one or more control circuits (Fig. 1A: 115) are configured to:
dynamically update read levels based on the read of the NAND memory cells in the selected block based on the set Tco ([0060]: At operation 325, a read operation is performed. For example, the control logic can perform the read operation on the segment of the memory array 104 using the one or more configured parameters. For example, local media controller 135 can apply a modified read voltage level to the wordlines of the memory array 104 associated with the segment being read…Depending on the embodiment, one or more parameters of the read operation can be adjusted at the same time; [0036]: local media controller 135 can selectively take corrective action to adjust the read voltage level (e.g., apply a read voltage offset to a default read voltage level) and other parameters only when necessary. Examiner asserts that the ability of the controller to adjust more than one parameter of the read operation at the same time and to selectively adjust the read voltage level are proof that Lu teaches dynamically updating read levels); and
read NAND memory cells in the selected block based on the dynamically updated read levels and the set Tco ([0060]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Achtenberg (US Pub. 20200159465 A1) as applied to claim 1 above, and further in view of Choi et al. (US Pub. 20240249782 A1; “Choi”).
Regarding claim 2, Achtenberg discloses the limitations of claim 1. Achtenberg does not disclose:
the temperature coefficient (Tco) includes a bit line Tco for a bit line voltage during read; and
the one or more control circuits are configured to apply a voltage to the bit lines during the read of the NAND memory cells in the selected block based on the set Tco, wherein a magnitude of the bit line voltage depends on the bit line Tco.
However, Choi teaches:
the temperature coefficient (Tco) includes a bit line Tco for a bit line voltage during read; ([0133]: As described in FIGS. 7 to 9, the memory device 300 may set in advance compensation values of a plurality of sensing parameters (e.g., the word line voltage VWL, the bit line voltage (VBL), and the SO discharge time (tSO_develop)) for compensating for the cell current that changes depending on the temperature and the read mode. Examiner concludes that the bit line voltage is a sensing parameter that may be compensated by a compensation value. Examiner asserts that the compensation value is analogous to a temperature coefficient) and
the one or more control circuits are configured to apply a voltage to the bit lines during the read of the NAND memory cells in the selected block based on the set Tco, wherein a magnitude of the bit line voltage depends on the bit line Tco ([0064]: The processor 230 may modify the sensing parameter for the memory device 100 based on the temperature bump table of the buffer memory 240; [0061]: The processor 230 may control an overall operation of the memory controller 200…the processor 230 may include a central processing unit (CPU), a controller, an application specific integrated circuit (ASIC), or the like; [0165]: applying the compensation value may mean adding the compensation value corresponding to each sensing parameter to each sensing parameter. Examiner asserts that the processor is functioning as a one or more control circuit, and the compensation value is added to the bit line voltage).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Choi to
Achtenberg wherein the temperature coefficient (Tco) includes a bit line Tco for a bit line voltage during read; and the one or more control circuits are configured to apply a voltage to the bit lines during the read of the NAND memory cells in the selected block based on the set Tco, wherein a magnitude of the bit line voltage depends on the bit line Tco in order to maintain data sensing reliability by compensating for temperature changes to cell current by adjusting sensing parameters (Choi, [0004]-[0006], [0108]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Achtenberg (US Pub. 20200159465 A1) as applied to claim 1 above, and further in view of Lu et al. (US Pub. 20200005878 A1; “Lu-878”).
Regarding claim 3, Achtenberg discloses the limitations of claim 1. Achtenberg does not disclose:
the temperature coefficient (Tco) includes a read pass Tco for a read pass voltage during read; and
the one or more control circuits are configured to apply a voltage to unselected word lines in the selected block during the read of the NAND memory cells in the selected block based on the set Tco, wherein a magnitude of the unselected word line voltage depends on the read pass Tco.
However, Lu-878 teaches:
the temperature coefficient (Tco) includes a read pass Tco for a read pass voltage during read ([0144]: the overdrive, or the amount by which the read pass voltage exceeds the Vth of the memory cell, is lower when the temperature is lower. Increasing the read pass voltages when the temperature is lower compensates for this effect. The read pass voltages can be adjusted for the adjacent word lines as well as the other remaining unselected word lines and even the selected word line); and
the one or more control circuits are configured to apply a voltage to unselected word lines in the selected block during the read of the NAND memory cells ([0071]: A NAND memory array may be configured so that the array is composed of multiple strings of memory) in the selected block ([0045]: During the read operation, the voltages of the unselected word lines are ramped up to a read pass voltage; [0058]: The power control module 116 controls the power and voltages supplied to the word lines, select gate lines, bit lines and source lines during memory operations. It can include drivers for word lines; [0099]: The voltage drivers can include a selected data word line (WL) driver 447 which provides a voltage on a data word line (WLn) selected during a program or read operation. A WLn−1 word line driver 447a provides a voltage on an unselected word line which is adjacent to and below WLn in a stack, and a WLn+1 word line driver 447b which provides a voltage on an unselected word line which is adjacent to and above WLn in a stack...In a word line programming order of a block, WLn−1 is before WLn and WLn+1 is after WLn. A voltage driver 448 is provided for other unselected data word lines. Examiner concludes that the power control module, which is part of the control circuitry 110 of Fig. 1A, controls the drivers that provide the read pass voltage to the unselected word lines) based on the set Tco, wherein a magnitude of the unselected word line voltage depends on the read pass Tco ([0144]).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Lu-878 to modified Achtenberg wherein the temperature coefficient (Tco) includes a read pass Tco for a read pass voltage during read; and the one or more control circuits are configured to apply a voltage to unselected word lines in the selected block during the read of the NAND memory cells in the selected block based on the set Tco, wherein a magnitude of the unselected word line voltage depends on the read pass Tco in order to prevent uncorrectable errors during read by applying compensation based on threshold voltages (Lu-878, [0050]-[0051]).
Claims 4, 5, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Achtenberg (US Pub. 20200159465 A1) as applied to claim 1 above, and further in view of Gorobets et al. (US Pub. 20160179407 A1; “Gorobets”).
Regarding claim 4, Achtenberg discloses the limitations of claim 1, and further through Achtenberg:
wherein the one or more control circuits (Fig. 1A: 120) are configured to:
program the group of memory cells in the selected block to a plurality of threshold voltage distributions prior to measuring the data retention impact in the group ([0125]: The offline characterization 1500 includes processes for determining actual TCOs of the group of memory cells. At process 1510, the group of memory cells are programmed with a selected soft bit or hard bit at a first temperature (referred to as program temperature in FIG. 15), and the Vts of each memory cell are measured at the first temperature…At process 1530, an actual TCO of each memory cell (i.e., the threshold voltage change ΔVt measured from the first temperature to the second temperature) may be determined. The programming at a first temperature and measurements of the Vt at the first temperature and the second temperature can occur over a number of programming/erase cycles; [0031]; [0032]. Examiner asserts that Achtenberg discloses that programming may occur prior to measuring Vt shift);
Achtenberg does not disclose:
measure a shift in a candidate threshold voltage distribution of the plurality of threshold voltage distributions to determine the data retention impact; and
set the Tco based shift in the threshold voltage distribution.
However, Gorobets teaches:
measure a shift in a candidate threshold voltage distribution of the plurality of threshold voltage distributions to determine the data retention impact ([0058]: modules such as a locator 812, scaler 814, and/or shaper 816 may analyze the cell voltage distribution as further described with respect to FIG. 18. The locator 812 can determine data retention based on a location shift of the states in the cell voltage distribution as described with respect to FIG. 20); and
set the Tco based shift in the threshold voltage distribution (claim 1: A method comprising…dynamically adjusting trim parameters based on the calculated data retention.).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Gorobets to modified Achtenberg wherein the one or more control circuits are configured to measure a shift in a candidate threshold voltage distribution of the plurality of threshold voltage distributions to determine the data retention impact; and set the Tco based shift in the threshold voltage distribution in order to improve memory and data management by measuring and dynamically adjusting memory parameters (Gorobets, [0005]).
Regarding claim 5, Achtenberg and Gorobets together disclose the limitations of claim 4. Achtenberg does not disclose:
wherein the shift in the candidate threshold voltage distribution is a downshift in the candidate threshold voltage distribution.
However, Gorobets teaches:
wherein the shift in the candidate threshold voltage distribution is a downshift in the candidate threshold voltage distribution ([0099]: FIG. 19 illustrates that the data loss (i.e. poor data retention) results in a gradual shift of the distribution. In particular, FIG. 19 is an illustration of analysis of data retention (DR). The right most distributions (i.e. the E, F, and G distributions) have a downward (lower voltage) shift due to the lapse in time; [0149]: data retention changes have a signature of upper states shifting down in voltage (left on the distribution diagram diagram)).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Gorobets to modified Achtenberg wherein the shift in the candidate threshold voltage distribution is a downshift in the candidate threshold voltage distribution in order to improve memory and data management by measuring and dynamically adjusting memory parameters (Gorobets, [0005]).
Regarding claim 11, Achtenberg and Gorobets together disclose the limitations of claim 1, and further through Achtenberg:
wherein the one or more control circuits (Fig. 1A: 120) configured to:
Achtenberg does not disclose:
perform a bitscan of the group of NAND memory cells in the selected block to determine a bitscan count that indicates the data retention impact;
access a table from non-transitory memory, wherein the table comprises entries that associate bitscan count ranges to modifications to the Tco; and
set the Tco based on the bitscan count determined from the bitscan.
However, Gorobets teaches:
perform a bitscan of the group of NAND memory cells in the selected block to determine a bitscan count that indicates the data retention impact ([0108]: There may be a component or module (e.g. in the controller or coupled with the controller) that monitors the distribution changes (location shifts, and width or shape changes) of the cell voltage distribution to identify or predict data retention or wear problems. In one embodiment, this may be part of a scan that is specific for either data retention loss or wear…A periodic measurement of the cell voltage distribution can be made and stored. That data may be periodically analyzed to identify wear (using either width or shape distribution changes) or retention loss (using location distribution changes).);
access a table from non-transitory memory, wherein the table comprises entries that associate bitscan count ranges to modifications to the Tco ([0060]: The data retention results or memory wear results from the cell voltage distribution changes may be tracked and stored (e.g. in the flash memory or within the controller). For example, a system table may track the changes in the cell voltage distributions and resultant changes in data retention and/or wear…The variation in data retention may be block by block or die by die; [0053]: trim parameters may be adjusted based on the wear or data retention loss for certain blocks…the trim parameters that are adjusted may be individually adjusted for each block based on the measurements of the block's health (e.g. wear, data retention, etc.)); and
set the Tco based on the bitscan count determined from the bitscan ([0108]; [0060]; [0053]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Gorobets to modified Achtenberg wherein the control circuits perform a bitscan of the group of NAND memory cells in the selected block to determine a bitscan count that indicates the data retention impact; access a table from non-transitory memory, wherein the table comprises entries that associate bitscan count ranges to modifications to the Tco; and set the Tco based on the bitscan count determined from the bitscan in order to improve memory and data management by measuring and dynamically adjusting memory parameters (Gorobets, [0005]).
Claims 6, 7, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Achtenberg (US Pub. 20200159465 A1) as applied to claim 1 above, and further in view of Parthasarathy et al. (US Pub. 20210350869 A1; “Parthasarathy”).
Regarding claim 6, Achtenberg discloses the limitations of claim 1, and further through Achtenberg:
wherein the one or more control circuits (Fig. 1A: 120) are configured to:
program the group of memory cells in the selected block to a plurality of threshold voltage distributions prior to measuring the data retention impact in the group ([0125]; [0031]; [0032]);
Achtenberg does not disclose:
read the group of memory cells at two voltage levels associated with a candidate threshold voltage distribution of the plurality of threshold voltage distributions;
determine how many memory cells in the group have a threshold voltage between the two voltage levels to determine the data retention impact in the group; and
set the Tco based on how many memory cells in the group have a threshold voltage between the two voltage levels.
However, Parthasarathy teaches:
read the group of memory cells at two voltage levels associated with a candidate threshold voltage distribution of the plurality of threshold voltage distributions;
determine how many memory cells in the group have a threshold voltage between the two voltage levels to determine the data retention impact in the group; and
set the Tco based on how many memory cells in the group have a threshold voltage between the two voltage levels ([0018]: Conventional calibration circuitry has been used to self-calibrate a memory region in applying read level signals to account for shift of threshold voltages of memory cells within the memory region. During the calibration, the calibration circuitry is configured to apply different test signals to the memory region to count the numbers of memory cells that output a specified data state for the test signals. Based on the counts, the calibration circuitry determines a read level offset value as a response to a calibration command. Examiner asserts that the “different test signals” are read voltage levels, that the “shift of threshold voltages of memory cells within the memory region” is the data retention impact in the group, and the “read level offset value” is a Tco. Because there are multiple test signals, the counting of memory cells for a “specified data state” implies that the count is between two test signal levels; also see [0021]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Parthasarathy to modified Achtenberg wherein the control circuits read the group of memory cells at two voltage levels associated with a candidate threshold voltage distribution of the plurality of threshold voltage distributions; determine how many memory cells in the group have a threshold voltage between the two voltage levels to determine the data retention impact in the group; and set the Tco based on how many memory cells in the group have a threshold voltage between the two voltage levels in order to determine, using the bit count of memory cells with certain threshold voltages, optimized read voltage levels (Parthasarathy, [0014], [0017], [0019]).
Regarding claim 7, Achtenberg and Parthasarathy together disclose the limitations of claim 6. Achtenberg does not disclose:
wherein the two voltage levels associated with the candidate threshold voltage distribution are within a lower tail of the candidate threshold voltage distribution.
However, Parthasarathy teaches:
wherein the two voltage levels associated with the candidate threshold voltage distribution are within a lower tail of the candidate threshold voltage distribution ([0021]: An optimized read voltage can be found at a voltage where the distribution of the count differences over voltage reaches a minimum; [0087]: As a result of the different voltages applied during the read operation, a same memory cell in the group (e.g., 131, . . . , or 133) may show different states. Thus, the counts C.sub.A, C.sub.B, C.sub.C, C.sub.D, and C.sub.E of memory cells having a predetermined state at different read voltages V.sub.A, V.sub.B, V.sub.C, V.sub.D, and V.sub.E can be different in general. Examiner asserts that, per Fig. 3, the two voltage levels may be VB and VC are lower than but in the vicinity of the optimal read voltage Vo, which is analogous to a candidate threshold voltage. The x-axis range of the curve at the bottom of Fig. 3 represents a distribution of threshold voltages, and thus VB and VC are within a lower tail of the distribution).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Parthasarathy to modified Achtenberg wherein the two voltage levels associated with the candidate threshold voltage distribution are within a lower tail of the candidate threshold voltage distribution in order to determine, using the bit count of memory cells with certain threshold voltages, optimized read voltage levels (Parthasarathy, [0014], [0017], [0019]).
Regarding claim 9, Achtenberg discloses the limitations of claim 1, and further through Achtenberg:
wherein the one or more control circuits (Fig. 1A: 120) are configured to:
the read of the NAND memory cells in the selected block based on the set Tco ([0009]),
Achtenberg does not disclose:
perform a valley scan search during the read of the NAND memory cells in the selected block, the valley scan search comprising reading at a plurality of read levels associated with a data state; and
determine a new read level for the data state based on a read level in the valley scan search having a lowest fail bit count (FBC).
However, Parthasarathy teaches:
perform a valley scan search during the read of the NAND memory cells ([0061]: non-volatile memory devices such as 3D cross-point type and NAND type memory (e.g., 2D NAND, 3D NAND) are described) in the selected block, the valley scan search comprising reading at a plurality of read levels ([0026]: Thus, when reading the group of memory cells using an optimized read voltage estimated using the techniques of FIGS. 5 and 6, the memory device can count the number of memory cells in the group that have threshold voltages above the estimated optimized read voltage. If the ratio between the count of such memory cells and the population of memory cells in the group is outside of a predetermined percentage range known for the actual optimized read voltage, the estimated optimized read voltage can be considered to be in a wrong voltage range. In such a situation, the memory device and/or the memory sub-system can adjust the test voltage range to search for an improved optimized read voltage) associated with a data state ([0084]: The data from the memory cells identified by the address (135) can include hard bit data 177 and soft bit data 173. The hard bit data 177 is retrieved using optimized read voltages. The hard bit data 177 identifies the states of the memory cells that are programmed to store data and subsequently detected in view of changes caused by factors, such as charge loss, read disturb, cross-temperature effect (e.g., write and read at different operating temperatures), etc. The soft bit data 173 is obtained by reading the memory cells using read voltages centered at each optimized read voltage with a predetermined offset from the center, optimized read voltage); and
determine a new read level for the data state based on a read level in the valley scan search having a lowest fail bit count (FBC) ([0019]: The estimated/classified level of bit error rate can be used to decide whether to recalibrate the read voltage, to retry read operations, to read additional data to facilitate decoding using a sophisticated technique, to search for a voltage range for calibrating/optimizing the read voltage).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Parthasarathy to modified Achtenberg wherein the control circuits perform a valley scan search during the read of the NAND memory cells in the selected block, the valley scan search comprising reading at a plurality of read levels associated with a data state; and determine a new read level for the data state based on a read level in the valley scan search having a lowest fail bit count (FBC) in order to determine, using the bit count of memory cells with certain threshold voltages, optimized read voltage levels (Parthasarathy, [0014], [0017], [0019]).
Claims 12, 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Achtenberg (US Pub. 20200159465 A1) in view of Choi (US Pub. 20240249782 A1) and Gorobets (US Pub. 20160179407 A1).
Independent claim 12 contains limitations that are mostly the same as the limitations of claims 1, 2, and 4. Specifically, the first limitation of claim 12 is mostly the same as limitations from claims 4 and 1, and the second and third limitations of claim 12 are mostly the same as limitations from claim 2. Thus, claim 12 is rejected for the same reasons using Achtenberg, Choi, and Gorobets.
Regarding claim 13, Achtenberg, Choi, and Gorobets together disclose the limitations of claim 12, and further through Achtenberg:
the group of NAND memory cells reside in a selected block ([0031]; [0032]); and
reading the selected NAND memory cells associated with the set of bit lines while applying the bit line voltage to the set of bit lines includes reading NAND memory cells in the selected block other than the group of NAND memory cells ([0035]: The read or memory access parameters of the group associated with a given time & temperature tag may be adjusted from time to time by running a read thresholds calibration algorithm, such as CVD tracking or BES, on representative page(s) from the group. This may be performed as a background maintenance process. Examiner concludes that the operations that calibrate compensation coefficients, which are performed on a subset of a group of memory cells (“representative pages”), may be performed at the same time as reads of other cells from the same group. “Group” of Achtenberg is analogous to “block” of the present application, and “representative page(s)” of Achtenberg is analogous to “group” of the present application).
Regarding claim 15, Achtenberg, Choi, and Gorobets together teach the method of claim 12, further comprising accessing a default bit line voltage Tco for freshly programmed memory cells that are programmed to a plurality of threshold voltage distribution including a candidate threshold voltage distribution, wherein the default bit line voltage Tco assumes no shift to the candidate threshold voltage distribution; wherein determining the bit line voltage Tco based on the shift to the candidate threshold voltage distribution to which the group of NAND memory cells in the non-volatile storage were programmed includes re-calibrating the default bit line voltage Tco to account for effects of data retention on the group of NAND memory cells (Fig. 2 and Fig. 3, teaches when there is not shift to the data as a result of having similar temperature range as the program operation, the default bit line voltage is applied. In the other case, when shift occurs, the bit line voltage is determined based on the shift to the threshold voltage distribution).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Achtenberg (US Pub. 20200159465 A1), Choi (US Pub. 20240249782 A1), and Gorobets (US Pub. 20160179407 A1) as applied to claim 12 above, and further in view of Parthasarathy (US Pub. 20210350869 A1).
Regarding claim 14, Achtenberg, Choi, and Gorobets together disclose the limitations of claim 12. The first limitation of claim 14 is mostly the same as a limitation from claims 12, and the second limitation of claim 14 is mostly the same as limitations from claim 6. Thus, claim 14 rejected for the same reasons using Achtenberg, Choi, Gorobets, and Parthasarathy.
Claims 16, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Achtenberg (US Pub. 20200159465 A1) in view of Choi (US Pub. 20240249782 A1), Gorobets (US Pub. 20160179407 A1), and Parthasarathy (US Pub. 20210350869 A1).
Independent claim 16 contains limitations that are mostly the same as the limitations of claims 1, 2, 6-7, and 12. Specifically, the first and second limitation of claim 16 are mostly the same as limitations from claim 1, the third limitation of claim 16 is mostly the same as a combination of a limitation from claim 6 and the limitation of claim 7, the fourth limitation is mostly the same as a limitation from claim 2, and the last limitation is mostly the same as a limitation of claim 12. Thus, claim 16 is rejected for the same reasons using Achtenberg, Choi, Gorobets, and Parthasarathy.
Regarding claim 17, Achtenberg, Choi, Gorobets, and Parthasarathy together disclose the limitations of claim 16. The limitations of claim 17 are mostly the same as limitations from claims 6, 7, and 11, and are thus rejected for the same reasons.
Regarding claim 20, Achtenberg, Choi, Gorobets, and Parthasarathy together disclose the limitations of claim 16. The limitations of claim 20 are almost exactly the same as the limitations from claim 8, and are thus rejected for the same reasons.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Achtenberg (US Pub. 20200159465 A1), Choi (US Pub. 20240249782 A1), Gorobets (US Pub. 20160179407 A1), and Parthasarathy (US Pub. 20210350869 A1) as applied to claim 16 above, and further in view of Lu-878 (US Pub. 20200005878 A1).
Regarding claim 18, Achtenberg, Choi, Gorobets, and Parthasarathy together disclose the limitations of claim 16. Achtenberg discloses the one or more control circuits.
Neither Achtenberg, Choi, nor Gorobets disclose:
determine a Vread temperature coefficient (Tco) based on the number of first NAND memory cells having a threshold voltage within the voltage range;
apply a voltage to unselected word lines in the selected block that is based on the Vread; and
read third NAND memory cells in the selected block while applying the voltage that is based on the Vread Tco to the unselected word lines.
However, Parthasarathy teaches:
determine a Vread temperature coefficient (Tco) based on the number of first NAND memory cells having a threshold voltage within the voltage range ([0018]; [0021]);
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Parthasarathy to modified Achtenberg wherein the one or more control circuits are configured to determine a Vread temperature coefficient (Tco) based on the number of first NAND memory cells having a threshold voltage within the voltage range in order to determine, using the bit count of memory cells with certain threshold voltages, optimized read voltage levels (Parthasarathy, [0014], [0017], [0019]).
Also, Lu-878 teaches:
apply a voltage to unselected word lines in the selected block that is based on the Vread ([0071]; [0045]); and
read third NAND memory cells in the selected block while applying the voltage that is based on the Vread Tco to the unselected word lines ([0045]; [0099]; [0144]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lu-878 to modified Achtenberg wherein the one or more control circuits are configured to apply a voltage to unselected word lines in the selected block that is based on the Vread; and read third NAND memory cells in the selected block while applying the voltage that is based on the Vread Tco to the unselected word lines in order to prevent uncorrectable errors during read by applying compensation based on threshold voltages (Lu-878, [0050]-[0051]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Achtenberg (US Pub. 20200159465 A1), Choi (US Pub. 20240249782 A1), Gorobets (US Pub. 20160179407 A1), and Parthasarathy (US Pub. 20210350869 A1) as applied to claim 16 above, and further in view of Lu (US Pub. 20240096408 A1).
Regarding claim 19, Achtenberg, Choi, Gorobets, and Parthasarathy together disclose the limitations of claim 16, and further through Achtenberg:
wherein the one or more control circuits (Fig. 1A: 120) configured to:
update read levels based on the read of the second NAND memory cells in the selected block
read third NAND memory cells in the selected block based on the updated read levels ([0088]: By closing the block when the temperature variation has exceeded the threshold, reading data from the block may be accomplished using a common set of read parameters, without having to adjust read parameters for different word lines of the block. Examiner concludes that parameters calculated based on second NAND memory cells may be applied in the read of third NAND memory cells, wherein “second NAND memory cells” and “third NAND memory cells” are interpretated as meaning cells connected to a second word line and third word line, respectively)
Neither Achtenberg, Choi, nor Gorobets disclose:
dynamically update read levels based on the read of the NAND memory cells in the selected block while applying the voltage that is based on the bit line voltage Tco to the bit lines; and
read NAND memory cells in the selected block based on the dynamically updated read levels and the bit line voltage Tco.
However, Lu teaches:
dynamically update read levels based on the read of the NAND memory cells in the selected block while applying the voltage that is based on the bit line voltage Tco to the bit lines ([0060]: At operation 325, a read operation is performed. For example, the control logic can perform the read operation on the segment of the memory array 104 using the one or more configured parameters…local media controller 135 can increase or decrease bitline voltage or pass voltage applied to adjacent wordlines for the read operation, as determined at operation 315. Depending on the embodiment, one or more parameters of the read operation can be adjusted at the same time; [0036]); and
read NAND memory cells in the selected block based on the dynamically updated read levels and the bit line voltage Tco ([0060]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lu to modified Achtenberg wherein the one or more control circuits are configured to dynamically update read levels based on the read of the NAND memory cells in the selected block while applying the voltage that is based on the bit line voltage Tco to the bit lines; and read NAND memory cells in the selected block based on the dynamically updated read levels and the bit line voltage Tco in order to improve performance in the memory device by adjusting the offsets of parameters such as read voltage (Lu, [0018]).
Conclusion
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/Khamdan N. Alrobaie/Primary Examiner, Art Unit 2824
/E.R.A./ Examiner, Art Unit 2824
1/21/2026