DETAILED ACTION
This non-final action is responsive to the following communications: application filed on 08/01/2024. Applicant’s Preliminary Amendment filed on 10/21/2024 is being acknowledged and entered.
Claims 2-21 are pending. Claims 2, 10, and 18 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Domestic Priority
4. See ADS for domestic CON priority details.
Information Disclosure Statement
5. IDS filed on 10/21/2024 has been considered.
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
8. Claims 2-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Vimercati (US 10,546,629 B1).
Regarding independent claim 2, Vimercati teaches a memory device (Fig. 10: 1000. See col. 30, lines 16-18. See applicable illustrated method, circuit components and functionality in Fig. 10-Fig. 15), comprising:
one or more memory arrays (Fig. 1: ARRAY);
a sense amplifier (col. 30, lines 26-27: folded cascode “sense amplifier”) having a gain stage that comprises a single transistor (Fig. 1: 1020, see col. 31, lines 23-24: “…sense amplifier 1020 may comprise a transistor…a PMOS device…”),
one or more controllers (Fig. 1: 150 memory controller, col. 38, lines 63-67) coupled with the one or more memory arrays (Fig. 1: ARRAY) and configured to cause the memory device to:
precharge (Fig. 13: 1305) an input of the sense amplifier (Fig. 10: 1010 “access line”) with a first voltage (col. 34, lines 31-38: “first voltage”) that is associated with a threshold voltage of the single transistor (see col. 31, lines 33-37: “…precharge voltage of the access line 1010 may reflect or otherwise be based on any offset voltage of the sense amplifier 1020…any variation in threshold voltage of the transistor…”. See also col. 34, lines 31-38);
transfer, after precharging the input of the sense amplifier (See Fig. 13: 1310), a first charge (col. 34, lines 31-38: “charge”) from a first digit line (Fig. 10: DL) to the input of the sense amplifier (Fig. 10: 1010) based at least in part on coupling (Fig. 10: 1055 switch coupling) the first digit line with the input of the sense amplifier (col. 34, lines 39-47: “…transfer charge between the access line and a memory cell after the precharging…”);
transfer (Fig. 13: 1315) a second charge (Fig. 10: e.g., reference voltage in RefCap) from a second digit line (Fig. 10: digit line with RefCap) to the input of the sense amplifier (Fig. 10: 1010) based at least in part on coupling (Fig. 10: 1050, 1045 switch coupling) the second digit line with the input of the sense amplifier (col. 34, lines 48-56: “…transfer charge between the access line and a capacitor…”. See also col. 31, lines 56-65); and
output, by the sense amplifier (Fig. 13: 1320), a signal (Fig. 10: sensing_out) indicating a logic state that is based at least in part on a voltage of the input of the sense amplifier (col. 34, lines 48-56: “third voltage” in access line) as a result of transferring the first charge and the second charge to the input of the sense amplifier (col. 34, lines 57-63: “…determine a state of the memory cell based on amplifying the third voltage using the sense amplifier”).
Regarding claim 3, Vimercati teaches the memory device of claim 2, wherein the one or more controllers are further configured to cause the memory device to:
precharge the second digit line to a reference voltage based at least in part on a capacitance of the second digit line (See also col. 31, lines 56-65: charge store in RefCap charges the digitline with Vref),
wherein the coupling the second digit line with the input of the sense amplifier is subsequent to the precharging the second digit line to the reference voltage (Fig. 11 in context of col. 31, lines 56-67; col. 32, lines 1-2).
Regarding claim 4, Vimercati teaches the memory device of claim 2, wherein the one or more controllers are further configured to cause the memory device to:
isolate (by turning off Fig. 10: 1040 switch) the input of the sense amplifier (Fig. 10: 1010) from an output of the sense amplifier (Fig. 10: sensing_out) after precharging the input of the sense amplifier (this is required since final sensing of cell state is not done right after precharging. see Fig. 11: 1105 low during and after Pre-Prech),
wherein the coupling the first digit line (Fig. 10: DL) with the input of the sense amplifier (Fig. 10: 1010) is subsequent to the isolating the input of the sense amplifier from the output of the sense amplifier (Fig. 13: 1310 and See also Fig. 11: DL_sel ramping timing).
Regarding claim 5, Vimercati teaches the memory device of claim 2, wherein the one or more controllers are further configured to cause the memory device to:
couple (using access transistor) a memory cell (Fig. 10 1070) of the one or more memory arrays with the first digit line (Fig. 10: DL),
wherein the transfer of charge from the first digit line to the input of the sense amplifier is based at least in part on a transfer of the charge from the memory cell to the first digit line in response to the coupling the memory cell with the first digit line (Fig. 10 circuit configuration in context of col. 30, lines 33-37).
Regarding claim 6, Vimercati teaches the memory device of claim 5, wherein the second digit line (Fig. 10: digit line with RefCap) is different from the first digit line (Fig. 10: DL) and is associated with a second memory cell (Fig. 10: RefCap which holds charge of reference voltage) that is not associated with an access operation (not associated with read/ write cell access operation. See Fig. 10-Fig. 11 in context of col. 31, lines 56-67; col. 32, lines 1-2).
Regarding claim 7, Vimercati teaches the memory device of claim 5, wherein the charge transferred from the memory cell to the first digit line is based at least in part on a logic state stored by the memory cell (Fig. 10: logic state 1 or 0 of memory cell is determines amount of charge that is configured to be transferred from cell to digit line), and
wherein the output of the sense amplifier indicates the logic state stored by the memory cell (Fig. 10: sensing_out indicates logic state. Col 34, lines 57-63).
Regarding claim 8, Vimercati teaches the memory device of claim 5, wherein the one or more controllers are further configured to cause the memory device to: couple a plate of the memory cell with a voltage source based at least in part on the memory cell being associated with an access operation (see col. 11, lines 37-53).
Regarding claim 9, Vimercati teaches the memory device of claim 2, wherein the one or more memory arrays comprise a plurality of ferroelectric memory cells (col. 4, lines 26-28; col. 10, lines 51-56: ferroelectric memory).
Regarding independent claim 10, Vimercati teaches a method by a memory device (sensing method using Fig. 10: 1000 memory circuit. See applicable illustrated method, circuit components and functionality in Fig. 10-Fig. 15), comprising:
precharging (Fig. 13: 1305) an input of a sense amplifier (Fig. 10: 1010 “access line”) with a first voltage (col. 34, lines 31-38: “first voltage”),
the sense amplifier col. 30, lines 26-27: folded cascode “sense amplifier”) having a gain stage that comprises a single transistor (Fig. 1: 1020, see col. 31, lines 23-24: “…sense amplifier 1020 may comprise a transistor…a PMOS device…”), and
the first voltage associated with a threshold voltage of the single transistor (see col. 31, lines 33-37: “…precharge voltage of the access line 1010 may reflect or otherwise be based on any offset voltage of the sense amplifier 1020…any variation in threshold voltage of the transistor…”);
transferring, after precharging the input of the sense amplifier (See Fig. 13: 1310), a first charge (col. 34, lines 31-38: “charge”) from a first digit line (Fig. 10: DL) to the input of the sense amplifier (Fig. 10: 1010) based at least in part on coupling (Fig. 10: 1055 switch coupling) the first digit line with the input of the sense amplifier (col. 34, lines 39-47: “…transfer charge between the access line and a memory cell after the precharging…”);
transferring (Fig. 13: 1315) a second charge (Fig. 10: charge in RefCap) from a second digit line (Fig. 10: digit line with RefCap) to the input of the sense amplifier (Fig. 10: 1010) based at least in part on coupling (Fig. 10: 1050, 1045 switch coupling) the second digit line with the input of the sense amplifier (col. 34, lines 48-56); and
outputting, by the sense amplifier (Fig. 13: 1320), a signal (Fig. 10: sensing_out) indicating a logic state that is based at least in part on a voltage of the input of the sense amplifier (col. 34, lines 48-56: “third voltage” in access line) as a result of transferring the first charge and the second charge to the input of the sense amplifier (col. 34, lines 57-63: “…determine a state of the memory cell based on amplifying the third voltage using the sense amplifier”).
Regarding claim 11, Vimercati teaches the method of claim 10, further comprising: precharging the second digit line to a reference voltage based at least in part on a capacitance of the second digit line (See in context of col. 31, lines 56-65: charge store in RefCap charges the digitline with Vref and digit line cap also partially impacts charge transfer),
wherein the coupling the second digit line with the input of the sense amplifier is subsequent to the precharging the second digit line to the reference voltage (Fig. 11 in context of col. 31, lines 56-67; col. 32, lines 1-2).
Regarding claim 12, Vimercati teaches the method of claim 10, further comprising: isolating (by turning off Fig. 10: 1040 switch) the input of the sense amplifier (Fig. 10: 1010) from an output of the sense amplifier (Fig. 10: sensing_out) after precharging the input of the sense amplifier (this is required since final sensing of cell state is not done right after precharging. see Fig. 11: 1105 low during and after Pre-Prech),
wherein the coupling the first digit line (Fig. 10: DL) with the input of the sense amplifier (Fig. 10: 1010) is subsequent to the isolating the input of the sense amplifier from the output of the sense amplifier (Fig. 13: 1310 and See also Fig. 11: DL_sel ramping timing).
Regarding claim 13, Vimercati teaches the method of claim 10, further comprising: coupling (using access transistor) a memory cell of the memory device (Fig. 10 1070) with the first digit line (Fig. 10: DL), wherein the transfer of charge from the first digit line to the input of the sense amplifier is based at least in part on a transfer of the charge from the memory cell to the first digit line in response to the coupling the memory cell with the first digit line (Fig. 10 circuit configuration and function in context of col. 30, lines 33-37).
Regarding claim 14, Vimercati teaches the method of claim 13, wherein the second digit line (Fig. 10: digit line with RefCap) is different from the first digit line (Fig. 10: DL) and is associated with a second memory cell (Fig. 10: RefCap which holds charge of reference voltage) that is not associated with an access operation (not associated with read/ write cell access operation. See Fig. 10-Fig. 11 in context of col. 31, lines 56-67; col. 32, lines 1-2).
Regarding claim 15, Vimercati teaches the method of claim 13, wherein the charge transferred from the memory cell to the first digit line is based at least in part on a logic state stored by the memory cell (Fig. 10: logic state 1 or 0 of memory cell is determines amount of charge that is configured to be transferred from cell to digit line), and wherein the output of the sense amplifier indicates the logic state stored by the memory cell (Fig. 10: sensing_out indicates logic state. Col 34, lines 57-63).
Regarding claim 16, Vimercati teaches the method of claim 13, further comprising: coupling a plate of the memory cell with a voltage source based at least in part on the memory cell being associated with an access operation (see col. 11, lines 37-53).
Regarding claim 17, Vimercati teaches the method of claim 13, wherein the memory cell is a ferroelectric memory cell (col. 4, lines 26-28; col. 10, lines 51-56: ferroelectric memory).
Regarding independent claim 18, Vimercati teaches a non-transitory computer-readable medium storing code comprising instructions which, when executed by one or more controllers of a memory device (see col. 36, lines 56-67, col. 37, lines 1-6: “… a non-transitory computer-readable medium storing instructions executable by a processor…” which employs operation method. See Fig. 10-Fig. 15 sensing method and apparatus), cause the memory device to:
precharge (Fig. 13: 1305) an input of a sense amplifier (Fig. 10: 1010 “access line”) with a first voltage (col. 34, lines 31-38: “first voltage”),
the sense amplifier (col. 30, lines 26-27: folded cascode “sense amplifier”) having a gain stage that comprises a single transistor (Fig. 1: 1020, see col. 31, lines 23-24: “…sense amplifier 1020 may comprise a transistor…a PMOS device…”), and
the first voltage associated with a threshold voltage of the single transistor (see col. 31, lines 33-37: “…precharge voltage of the access line 1010 may reflect or otherwise be based on any offset voltage of the sense amplifier 1020…any variation in threshold voltage of the transistor…”);
transfer, after precharging the input of the sense amplifier (See Fig. 13: 1310), a first charge (col. 34, lines 31-38: “charge”) from a first digit line to the input of the sense amplifier based at least in part on coupling (Fig. 10: 1055 switch coupling) the first digit line with the input of the sense amplifier (col. 34, lines 39-47: “…transfer charge between the access line and a memory cell after the precharging…”);
transfer (Fig. 13: 1315) a second charge (Fig. 10: charge in RefCap) from a second digit line (Fig. 10: digit line with RefCap) to the input of the sense amplifier (Fig. 10: 1010) based at least in part on coupling (Fig. 10: 1050, 1045 switch coupling) the second digit line with the input of the sense amplifier (col. 34, lines 48-56); and
output, by the sense amplifier (Fig. 13: 1320), a signal indicating a logic state that is based at least in part on a voltage of the input of the sense amplifier (col. 34, lines 48-56: “third voltage” in access line) as a result of transferring the first charge and the second charge to the input of the sense amplifier (col. 34, lines 57-63: “…determine a state of the memory cell based on amplifying the third voltage using the sense amplifier”).
Regarding claim 19, Vimercati teaches the non-transitory computer-readable medium of claim 18, wherein the instructions, when executed by the one or more controllers of the memory device, further cause the memory device to:
precharge the second digit line to a reference voltage based at least in part on a capacitance of the second digit line (See also col. 31, lines 56-65: charge store in RefCap charges the digitline with Vref and digit line capacitance will also impact the charge transfer),
wherein the coupling the second digit line with the input of the sense amplifier is subsequent to the precharging the second digit line to the reference voltage (Fig. 11 in context of col. 31, lines 56-67; col. 32, lines 1-2).
Regarding claim 20, Vimercati teaches the non-transitory computer-readable medium of claim 18, wherein the instructions, when executed by the one or more controllers of the memory device, further cause the memory device to:
isolate (by turning off Fig. 10: 1040 switch) the input of the sense amplifier (Fig. 10: 1010) from an output of the sense amplifier (Fig. 10: sensing_out) after precharging the input of the sense amplifier (this is required since final sensing of cell state is not done right after precharging. see Fig. 11: 1105 low during and after Pre-Prech),
wherein the coupling the first digit line (Fig. 10: DL) with the input of the sense amplifier (Fig. 10: 1010) is subsequent to the isolating the input of the sense amplifier from the output of the sense amplifier (Fig. 13: 1310 and See also Fig. 11: DL_sel ramping timing).
Regarding claim 21, Vimercati teaches the non-transitory computer-readable medium of claim 18, wherein the instructions, when executed by the one or more controllers of the memory device, further cause the memory device to:
couple (using access transistor) a memory cell (Fig. 10 1070) of the memory device with the first digit line (Fig. 10: DL), wherein the transfer of charge from the first digit line to the input of the sense amplifier is based at least in part on a transfer of the charge from the memory cell to the first digit line in response to the coupling the memory cell with the first digit line (Fig. 10 circuit configuration in context of col. 30, lines 33-37).
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure: US 12073870 B2: claims are applicable for double patenting rejection and the area may be visited in future. Di Vincenzo (US 2019/0333563 A1) is applicable for claim rejection: Di Vincenzo teaches an apparatus (Fig. 1 apparatus. See Fig. 1 - Fig. 9 for illustrated circuitry and functionality).
It is suggested that applicant consider all prior arts made of record.
Conclusion
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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