DETAILED ACTION
The action is responsive to the following communications: the Application filed August 01, 2024 and the information disclosure statement (IDS) filed August 01, 2024 and September 30, 2025. This application is a CON of 17/849,903.
Claims 1-12 are pending. Claim 1 is independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 01, 2024 and September 30, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-33 of US Patent No. 12,087,356. Although the claims at issue are not identical, they are not patentably distinct from each other.
Instant Application
US Patent 12,087,356
Comment
Claim 1. A method for accessing a memory array during an in-memory compute operation, the memory array including a plurality of memory cells, each memory cell comprising a latch circuit including a first side with a first data node and a first low supply node coupled to a first modulated reference supply voltage and further including a second side with a second data node and a second low supply node coupled to a second modulated reference supply voltage, wherein the plurality of memory cells are arranged in a matrix with plural rows and plural columns, each column including a pair of bit lines connected to the memory cells of the column, and each row including a first word line connected to the first side of the latch circuit and a second word line connected to the second side of the latch circuit, the method comprising:
simultaneously applying pulses only to the first word lines in a first phase of the in-memory compute operation;
switching the second modulated reference supply voltage at the second low supply node from a ground voltage to a negative voltage during the first phase;
then simultaneously applying pulses only to the second word lines in a second phase of the in-memory compute operation;
switching the first modulated reference supply voltage at the first low supply node from the ground voltage to the negative voltage during the second phase; and
processing analog voltages developed on the pairs of bit lines in response to the first and second phases of the in-memory compute operation to generate a decision output for the in-memory compute operation.
Claim 1. A circuit, comprising:
a memory array storing weight data for an in-memory compute operation and including a plurality of static random access memory (SRAM) cells arranged in a
matrix with plural rows and plural columns, each column including a pair of bit lines connected to the
SRAM cells of the column, and each row including:
…
a row controller circuit configured to simultaneously actuate only the first word lines in a first phase of the in-memory compute operation by applying pulses having pulse widths modulated by feature data of the in-memory compute operation through the first word line driver circuits to the first word lines and then simultaneously actuate only the second word lines in a second phase of the in-memory compute operation by
applying pulses having pulse widths modulated by feature data of the in-memory compute operation through the second word line driver circuits to the
second word lines;
a column processing circuit connected to the pair of bit
lines for each column and configured to process analog
voltages developed on the pairs of bit lines in response to the first and second phases of the in-memory compute operation to generate a decision output for the in-memory compute operation; and
a source supply modulation circuit configured to independently switch a modulated reference supply voltage for the second and first data storage nodes of the SRAM
cells, respectively, from a ground voltage to a negative voltage during the first and second phases of the in-memory compute operation, respectively.
Claim 8. wherein the first data storage node on a first side of a latch for the SRAM cell is read during the first phase and the
second data storage node on a second side of the latch
for the SRAM cell is read during the second phase; and
wherein the source supply modulation circuit is configured
to switch a low supply node for the first side of the latch for the SRAM cell from the ground voltage to the
negative voltage during the second phase and switch a low supply node for the second side of the latch for the SRAM cell from the ground voltage to the negative
voltage during the first phase.
Note footnote1
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 and 12 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ichihashi (US 2018/0012648) in view of Chu et al. (US 9,336,865).
Regarding independent claim 1, Ichihashi teaches a method for accessing a memory array during an in-memory compute operation, the memory array (see e.g., FIG. 3) including a plurality of memory cells (see FIGS. 1 and 3: 10), each memory cell comprising a latch circuit including a first side (FIG. 3: 10, M3 side) with a first data node (FIG. 3: 10 along with FIG. 1: M3 drain node) and a first low supply node (FIG. 3: M3 source node) coupled to a first modulated reference supply voltage (FIG. 3: VSS1) and further including a second side (FIG. 3: 10, M1 side) with a second data node (FIG. 3: 10 along with FIG. 1: M1 drain node) and a second low supply node (FIG. 3: M1 source node) coupled to a second modulated reference supply voltage (FIG. 3: VSS2), wherein the plurality of memory cells are arranged in a matrix with plural rows and plural columns, each column including a pair of bit lines connected to the memory cells of the column, and each row including a first word line connected to the first side of the latch circuit and a second word line connected to the second side of the latch circuit, the method comprising:
Simultaneously (see FIG. 3, 22 connection to driver WL for M3) applying pulses only to the first word lines (FIG. 3: 22, e.g., para. 0025: WL driver 22) in a first phase of the in-memory compute operation (FIG. 4 and e.g., para. 0027: … during the read cycle, nodes VSS1 … will be negative …);
switching the second modulated reference supply voltage at the second low supply node from a ground voltage to a negative voltage (FIG. 3: VSS2, and e.g., para. 0027: … during the read cycle, nodes … VSS2 will be negative …) during the first phase; and
then simultaneously (see FIG. 3, 22 connection to driver WL for M1) applying pulses only to the second word lines in a second phase of the in-memory compute operation;
switching the first modulated reference supply voltage at the first low supply node from the ground voltage to the negative voltage (FIG. 3: VSS1, e.g., para. 0027: … during the read cycle, nodes VSS1 … will be negative …) during the second phase; and
processing (FIG. 3: 40 sense amp) analog voltages developed on the pairs of bit lines in response to the first and second phases of the in-memory compute operation to generate a decision output for the in-memory compute operation (see e.g., FIG. 3 and accompanying disclosure).
Ichihashi is silent with respect to each row including a first word line connected to the first side of the latch circuit and a second word line connected to the second side of the latch circuit, and switching the second modulated reference supply voltage; and switching the first modulated reference supply voltage.
Chu et al. teach the deficiencies, i.e., each row including a first word line (FIGS. 1-2: WLA) connected to the first side of the latch circuit and a second word line (WLB) connected to the second side of the latch circuit,
switching (FIG. 5: WLA) the second modulated reference supply voltage at the second low supply node from a ground voltage to a negative voltage (see primary reference Ichihashi’s negative voltage, VSS1) during the first phase (FIG. 6: WLA active phase); and
switching (FIG. 5: WLB) the first modulated reference supply voltage at the first low supply node from the ground voltage to the negative voltage (see primary reference Ichihashi’s negative voltage, VSS2) during the second phase (FIG. 6: WLB active phase).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Chu et al. to the teaching of Ichihashi et al. such that a memory access operation, as taught by Ichihashi et al., utilizes a word line switching operation, as taught by Chu et al., for the purpose of enabling proper word line, thereby enhancing memory read operation by suppressing the read disturb.
Regarding claims 2-4, Ichihashi and Chu et al., as combined, teach the limitations of claim 1.
Ichihashi does not explicitly disclose controlling a level of the negative voltage dependent on information concerning integrated circuit process conditions; controlling a level of the negative voltage dependent on information concerning integrated circuit temperature conditions; and switching to the negative voltage comprises performing a voltage boosting to generate said negative voltage, and wherein a level of the negative voltage is dependent on information concerning integrated circuit process and/or temperature conditions.
However, integrated circuits with PVT variations are a well-known technology in semiconductor integrated circuits.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize PVT immunized memory operation because these conventional technology are well established in the art of the memory devices.
Regarding claim 5, Ichihashi and Chu et al., as combined, teach the limitations of claim 1.
Ichihashi further teaches switching to the negative voltage comprises: generating the negative voltage; and controlling a level of the negative voltage in response to a control signal; wherein the control signal is configured to cause modulation of the level of the negative voltage away from a nominal level in response to an applicable integrated circuit process corner for transistor devices of the memory cells (see e.g., FIGS. 3-5 and accompanying disclosure).
Regarding claim 6, Ichihashi and Chu et al., as combined, teach the limitations of claim 5.
Ichihashi does not explicitly disclose the applicable integrated circuit process corner is indicated by a programmed code, and further comprising storing the programmed code in a lookup table (LUT) which correlates the programmed code to a value of the control signal.
However, storing programmed data in a lookup table in a memory circuits is a well-known technology in semiconductor integrated circuits.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize LUT for storing programmed data because these conventional technology are well established in the art of the memory devices.
Regarding claims 7-8 and 9-10, Ichihashi and Chu et al., as combined, teach the limitations of claims 5 and 1, respectively.
Ichihashi does not explicitly disclose sensing temperature, and wherein the control signal is configured to cause a temperature dependent tuning of the level of the negative voltage; and storing in a lookup table (LUT) a correlation between temperature and a tuning level for the value of the control signal.
However, temperature dependent level of negative voltage in a memory circuits is a well-known technology in semiconductor integrated circuits.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize PVT immunized memory operation because these conventional technology are well established in the art of the memory devices.
Regarding claim 12, Ichihashi and Chu et al., as combined, teach the limitations of claim 1.
Chu et al. further teach reading data from the first data node on the first side of the latch during the first phase; and reading data from the second data node on the second side of the latch during the second phase (FIG. 6 and 9, and accompanying disclosure, see e.g., col. 5, lines 50-65: … WLA, WLB and corresponding read operation).
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SUNG IL CHO/Primary Examiner, Art Unit 2825
1 Re independent claim 1, claims of US Patent recites all the claimed limitations. The various dependent claims are anticipated by/obvious in view of the conflicting patent.