Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Foreign Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been placed in the file of record.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/forms/. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-23 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-27 of U.S. Patent No. 12087367.
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Current Application # 18791943
US Pat # 12087367
For example:
Claim 1:
1. A non-volatile memory device, comprising: a memory cell array including a plurality of word lines; and a control logic circuit configured to apply a first target voltage level to a selected word line as a selected word line voltage for a first sensing operation in a first sensing time and apply a second target voltage level to the selected word line as the selected word line voltage for a second sensing operation in a second sensing time, wherein the control logic circuit is further configured to: set the selected word line voltage to be a first voltage level in a first section of the first sensing time, set the selected word line voltage to be a second voltage level in a second section of the first sensing time which follows the first section of the first sensing time, wherein the second voltage level is different than the first voltage level, set the selected word line voltage to be the first target voltage level in a third section of the first sensing time which follows the second section of the first sensing time, wherein the first target voltage level is different than the second voltage level, set the selected word line voltage to be a third voltage level in a first section of a second sensing time which follows the third section of the first sensing time, and set the selected word line voltage to be the second target voltage level in a second section of the second sensing time which follows the first section of the second sensing time, wherein the first target voltage level is less than the second target voltage level, wherein the third voltage level is different than the second target voltage level, wherein the memory cell array includes a three-dimensional memory cell array including NANDJ strings, each of the NANDJ strings including memory cells respectively connected to the word lines that are vertically stacked on a substrate, wherein the memory cell array is included in a memory cell region, and the control logic circuit is included in a peripheral circuit region, and wherein the memory cell region further includes a first metal pad, the peripheral circuit region further includes a second metal pad, and the peripheral circuit region is vertically connected to the memory cell region by the first metal pad and the second metal pad.
For example:
Claim 16:
16. A non-volatile memory device, comprising: a memory cell array comprising a plurality of word lines; and a control logic circuit configured to apply a first target voltage level to a selected word line as a selected word line voltage for a first sensing operation in a first sensing time and apply a second target voltage level to the selected word line as the selected word line voltage for a second sensing operation in a second sensing time, the control logic circuit further configured to set the selected word line voltage to be a first voltage level in a first section of the first sensing time, set the selected word line voltage to be a second voltage level in a second section of the first sensing time which follows the first section of the first sensing time, wherein the second voltage level is different than the first voltage level, set the selected word line voltage to be the first target voltage level in a third section of the first sensing time which follows the second section of the first sensing time, wherein the first target voltage level is different than the second voltage level, set the selected word line voltage to be a third voltage level in a first section of a second sensing time which follows the third section of the first sensing time, and set the selected word line voltage to be the second target voltage level in a second section of the second sensing time which follows the first section of the second sensing time, wherein the first target voltage level is greater than the second target voltage level, and wherein the second target voltage level in greater than the third voltage level.
17. The non-volatile memory device of claim 16, wherein the first voltage level is greater than the first target voltage level.
18. The non-volatile memory device of claim 17, wherein the first voltage level becomes greater as the first target voltage level becomes greater.
19. The non-volatile memory device of claim 18, wherein a duration of the first section of the first sensing time is varied based on the first target voltage level.
20. The non-volatile memory device of claim 19, wherein memory cell array includes a three-dimensional memory cell array including NAND strings, each of the NAND strings including memory cells respectively connected to the word lines that are vertically stacked on a substrate.
22. The non-volatile memory device of claim 16, wherein the memory cell array is included in a memory cell region, and the control logic circuit is included in a peripheral circuit region, and wherein the memory cell region further includes a first metal pad, the peripheral circuit region further includes a second metal pad, and the peripheral circuit region is vertically connected to the memory cell region by the first metal pad and the second metal pad.
Even though the claims at issue are not identical but overall scope of the claims are identical and they are not patentably distinct from each other. For example, the above limitation “wherein the third voltage level is different than the second target voltage level” in current application 18791943 and the limitation “wherein the second target voltage level in greater than the third voltage level” in US Pat # 12087367 are not identical but they anticipate each other because the second target voltage in greater than the third voltage level clearly indicate the second target voltage in different than the third voltage level. So, they are not patentably distinct from each other.
Claims 1-23 would be allowable if the double patenting rejection set forth in this office action is overcome.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824