Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-19 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Ikeda (Patent Application Publication 2011/0182109).
Claim 1. A memory cell, comprising: a substrate (501 Ikeda Fig 5); a bottom electrode over the substrate (503 Ikeda Fig 5); a variable resistance film over the bottom electrode (504 Ikeda Fig 5, resistance changes in layer taught in Ikeda [0335]); and a top electrode over the variable resistance film (505 Ikeda Fig 5), wherein the variable resistance film exhibits a first polarization in response to a first voltage sweep operation within a first voltage range (M11 at time T2, Ikeda Fig 31A), exhibits a second polarization in response to a second voltage sweep operation within a second voltage range (M11 at time T3, Ikeda Fig 31A), and exhibits a third polarization in response to a third voltage sweep operation within a third voltage range (M11 at time T4, Ikeda Fig 31A), wherein the first voltage range, the second voltage range, and the third voltage range are different from one another (as seen in Fig 31A).
Claim 2. The memory cell of claim 1, wherein the first voltage range comprises a negative voltage (negative voltage taught in, Ikeda [0374]. Voltage goes down in negative direction Fig 31A).
Claim 3. The memory cell of claim 1, wherein the first voltage range is not positive (negative voltage taught in, Ikeda [0374]).
Claim 4. The memory cell of claim 1, wherein the third voltage range comprises a positive voltage (positive voltage taught in, Ikeda [0374] as seen as T4 in Fig 31A).
Claim 5. The memory cell of claim 1, wherein the third voltage range is not negative (positive voltage taught in, Ikeda [0374] as seen as T4 in Fig 31A).
Claim 6. The memory cell of claim 1, wherein the second voltage range comprises a positive voltage and a negative voltage (negative and positive voltages in T3 Ikeda Fig 31A. Positive and negative voltages taught in, Ikeda [0374]).
Claim 7. A memory cell, comprising: a substrate (501 Ikeda Fig 5); a bottom electrode over the substrate (503 Ikeda Fig 5); a variable resistance film over the bottom electrode (504 Ikeda Fig 5, resistance changes in layer taught in Ikeda [0335]); and a top electrode over the variable resistance film (505 Ikeda Fig 5), wherein the variable resistance film exhibits a first polarization in response to a first voltage sweep operation applied to the memory cell (M11 at time T2, Ikeda Fig 31A), a second polarization in response to a second voltage sweep operation applied to the memory cell (M11 at time T3, Ikeda Fig 31A), and a third polarization in response to a third voltage sweep operation applied to the memory cell (M11 at time T4, Ikeda Fig 31A), with the first polarization, the second polarization, and the third polarization being different from one another in magnitude (as seen in Fig 31A).
Claim 8. The memory cell of claim 7, wherein the first polarization and the second polarization are negative (negative voltage taught in, Ikeda [0374]. Voltage goes down in negative direction Fig 31A).
Claim 9. The memory cell of claim 7, wherein the second polarization and the third polarization are positive (positive voltages in T3 and T4 Ikeda Fig 31A. Positive and negative voltages taught in, Ikeda [0374]).
Claim 10. The memory cell of claim 7, wherein the second polarization is positive (positive voltages at end of T3 Fig 31A. Positive voltage taught in, Ikeda [0374]).
Claim 11. A method of operating a memory cell comprising a top electrode (505, Ikeda Fig 5), a variable resistance film (504 Fig 5) and a bottom electrode stacked in sequence (503 Fig 5), comprising: performing a first unipolar voltage sweep operation to the memory cell (unipolar taught sweep taught at T2 in Ikeda Fig 31A); performing a first bipolar voltage sweep operation to the memory cell (bipolar taught in Ikeda [0056] as seen in T3 Fig 31A); and performing a second unipolar voltage sweep operation to the memory cell (unipolar taught sweep taught at T4 in Ikeda Fig 31A).
Claim 12. The method of claim 11, wherein performing the first unipolar voltage sweep operation is performed such that the variable resistance film has a negative polarity (negative voltage taught in, Ikeda [0374]. Voltage goes down in negative direction Fig 31A).
Claim 13. The method of claim 11, wherein performing the second unipolar voltage sweep operation is performed such that the variable resistance film has a positive polarity (unipolar sweep taught to have positive polarity at T4 in Ikeda Fig 31A).
Claim 14. The method of claim 11, further comprising: after performing the second unipolar voltage sweep operation to the memory cell, performing a second bipolar voltage sweep operation to the memory cell (A second bipolar voltage sweep operation occurs when the selected cell is accessed a second time. T3 teaches bipolar sweep operation Fig 31A.)
Claim 15. The method of claim 11, further comprising: after performing the second unipolar voltage sweep operation to the memory cell, performing a third unipolar voltage sweep operation to the memory cell using a voltage range different from a voltage range of the second unipolar voltage sweep operation (A third bipolar voltage sweep operation occurs when the selected cell is accessed a third time. T3 teaches bipolar sweep operation Fig 31A.)
Claim 16. The method of claim 11, wherein performing the first unipolar voltage sweep operation comprises applying a first voltage range to the memory cell (applying volage range show at time T2 Ikeda Fig 31A. First range at low end), performing the second unipolar voltage sweep operation comprises applying a second voltage range to the memory cell (applying volage range show at time T4 Ikeda Fig 31A. Second range at high end.), and the first voltage range non-overlaps the second voltage range (range at high and range at low end do not overlap).
Claim 17. The method of claim 16, wherein performing the first bipolar voltage sweep operation comprises applying a third voltage range to the memory cell, and the third voltage range non-overlaps the first voltage range (T3 teaches bipolar sweep operation with a third voltage range to the memory cell Fig 31A. Ranges in T3 and T2 do not overlap.)
Claim 18. The method of claim 16, wherein performing the first bipolar voltage sweep operation comprises applying a third voltage range to the memory cell, the third voltage range non-overlaps the second voltage range (T3 teaches bipolar sweep operation with a positive voltage range to the memory cell Fig 31A. The positive and neutral range of voltage at T3 do not overlap.)
Claim 19. The method of claim 16, wherein the variable resistance film comprises hafnium zirconium oxide (HZO) (Hafnium and zirconium oxide addressed in [0599]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Ikeda (Patent Application Publication 2011/0182109) in view of KR 101017713 B1 (herein ‘713).
Claim 20. Ikeda discloses the method of claim 16, but does not disclose wherein the variable resistance film comprises Hf1-xZrxO2, in which x is greater than 50% and less than 100%.
‘713 discloses hafnium zirconium oxide (Hf.sub.x Zr.sub.1-x O2 where x is between 0 and 1). This is an optimum value. It has been held that the discovery of the optimum value of a result effective variable in a known process is ordinarily within the skill in the art. In re Boesch and Slaney, 205 USPQ 215 (CCPA 1980).
Since Ikeda and ‘713 are both from the same field of endeavor (nonvolatile semiconductor memory), the purpose disclosed by ‘713 would have been recognized in the pertinent art of Ikeda.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use the concentration taught by ‘713 in the circuit taught by Ikeda since the optimum value of a result effective variable in a known process is ordinarily within the skill in the art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Lappas whose telephone number is (571) 270-1272. The examiner can normally be reached on M-F 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON LAPPAS/
Primary Examiner, Art Unit 2827