Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Wada et al. (US 2013/0153899), hereinafter Wada, in view of Sato (US 7,467,341).
Regarding claim 1, Wada teaches a semiconductor device (Wada, Figs. 3A and 3B show a stacked semiconductor device including a plurality of semiconductor chips C1-C4 connected through TSVs and bump electrodes) comprising: a base chip configured to, during a scan operation, connect a first signal path and a second signal path to a first voltage source (Wada, para. [0119], lines 1-8, “when signals are supplied to the test pads TP11 to TP14 of the chip C1 (Slice0) and the gate potentials of the NMOS transistors NMOS2 are changed, a potential change occurs on the bump electrodes B11 and the test pads TP11 of the chips C1 to C4 (Slice0 to Slice3). This makes it possible to obtain the test result (whether a current flows through third paths including the penetration electrodes TSV12) on each chip (slice)”); a first memory chip configured to, during the scan operation, connect the first signal path to a second voltage source (Wada, Figs. 3A and 3B teach stacked memory chips C1-C4 connected through TSVs; para. [0042], lines 1-3, “As shown in FIG. 5, the chip C1 includes the channels a to d, a boundary scan control circuit 50 (hereinafter, BS control circuit 50)”) to generate a first fail result signal (Wada, para. [0119], lines 1-8, “when signals are supplied to the test pads TP11 to TP14 of the chip C1 (Slice0) and the gate potentials of the NMOS transistors NMOS2 are changed, a potential change occurs on the bump electrodes B11 and the test pads TP11 of the chips C1 to C4 (Slice0 to Slice3). This makes it possible to obtain the test result (whether a current flows through third paths including the penetration electrodes TSV12) on each chip (slice)”; para. [0225], lines 3-6, “If the first paths include any defect such as an open penetration electrode, the corresponding node (node Node1 (Slice1)) fails to be provided with a first signal. The node is thus not precharged and maintains a discharged state”; para. [0167], lines 3-6, “If the second paths include any defect such as an open penetration electrode, the corresponding node Node1 (Slice1) fails to be provided with a second signal, whereby the potential of the node (node Node2 (Slice1)) is discharged”) and output the first fail result signal to the base chip (Wada, para. [0102], lines 3-4, “the test data output to the scan data output terminal SDO can be obtained via the test pad SDO of the chip C1”); and a second memory chip configured to, during the scan operation, connect the second signal path to a third voltage source (Wada, Figs. 3A and 3B teach stacked memory chips C1-C4 connected through TSVs; para. [0097], lines 1-4, “The BS test is performed by using these signals described above. For example, the BS test to detect an open defect between the chips C1 and C2 is performed by a following sequence”; C2 equates to a second memory chip) to generate a second fail result signal (Wada, para. [0119], lines 1-8, “when signals are supplied to the test pads TP11 to TP14 of the chip C1 (Slice0) and the gate potentials of the NMOS transistors NMOS2 are changed, a potential change occurs on the bump electrodes B11 and the test pads TP11 of the chips C1 to C4 (Slice0 to Slice3). This makes it possible to obtain the test result (whether a current flows through third paths including the penetration electrodes TSV12) on each chip (slice)”) and to output the second fail result signal to the base chip (Wada, para. [0102], lines 3-4, “the test data output to the scan data output terminal SDO can be obtained via the test pad SDO of the chip C1”).
Wada fails to teach the first memory chip outputting a first fail result signal to the base chip when a chip identification (ID) has a first combination and the second memory chip outputting a second fail result signal to the base chip when the chip ID has a second combination.
However, Sato, in an analogous art, teaches the first memory chip outputting a first fail result signal to the base chip when a chip identification (ID) has a first combination and the second memory chip outputting a second fail result signal to the base chip when the chip ID has a second combination (Sato, col. 7, lines 5-10, “in the case where the identification data is stored in the storage means and where the comparison information indicates the agreement between the identification data and the fixed data, the data derivation section outputs the same data as the test result data which is outputted from the data output section”).
Wada and Sato are both considered to be analogous to the claimed invention because both are in the same field of semiconductor devices with a plurality of chips, performing boundary scan testing.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Wada’s boundary scan testing system to incorporate the teachings of Sato by including the functionality of outputting signals based on identification data comparison.
The suggestion/motivation for doing so would be to improve testing and fault isolation/diagnosis of stacked semiconductor devices.
Regarding claim 2, the combination of Wada in view of Sato teaches the semiconductor device of claim 1, wherein during the scan operation, the base chip connects the first signal path to one of a first PMOS transistor and a first NMOS transistor and connects the second signal path to one of a second PMOS transistor and a second NMOS transistor (Wada, para. [0128]-[0130] and para. [0188]-[0193] teaches using PMOS and NMOS transistors for driving a test node to respective voltage levels, including a PMOS transistor coupled to power supply voltage VDD and an NMOS transistor coupled to ground GND).
Regarding claim 3, the combination of Wada in view of Sato teaches the semiconductor device of claim 1, wherein the first memory chip connects the first signal path to one of a third PMOS transistor and a third NMOS transistor and generates the first fail result signal according to a logic level at the first signal path (Wada, para. [0185]-[0193] and para. [0209]-[0212] teaches each stacked chip including test circuitry that has PMOS and NMOS transistors coupled to a signal-path note, and that the resulting logic/potential level of the node is used in obtaining the test result corresponding to the connection state of the single path).
Regarding claim 4, the combination of Wada in view of Sato teaches the semiconductor device of claim 1, wherein the second memory chip connects the second signal path to one of a fourth PMOS transistor and a fourth NMOS transistor and generates the second fail result signal according to a logic level at the second signal path (Wada, para. [0185]-[0193] and para. [0209]-[0212] teaches each stacked chip including test circuitry that has PMOS and NMOS transistors coupled to a signal-path note, and that the resulting logic/potential level of the node is used in obtaining the test result corresponding to the connection state of the single path; the test result equates to a fail result signal).
Regarding claim 5, the combination of Wada in view of Sato teaches the semiconductor device of claim 1, the first signal path and the second signal path are stacked through the base chip, the first chip, and the second chip that are stacked (Wada, para. [0099]-[0106] teaches signal paths extending through stacked memory chips C1 and C2 through penetration electrodes/TSVs and bump electrodes formed in and between the stacked memory chips).
Regarding claim 6, the combination of Wada in view of Sato teaches the semiconductor device of claim 1, wherein the first signal path includes a first plurality of through vias and a first plurality of bumps and the second signal path includes a second plurality of through vias and a second plurality of bumps, and wherein the first plurality of through vias and the first plurality of bumps included in the first signal path are electrically connected, and the second plurality of through vias and the second plurality of bumps included in the second signal path are electrically connected (Wada, para. [0099]-[0106] and para. [0116]-[0119] teaches that the signal paths include penetration electrodes/TSVs and bump electrodes, with the penetration electrodes electrically connecting corresponding bump electrodes of the memory chips).
Regarding claim 27, Wada teaches a semiconductor device (Wada, Figs. 3A and 3B show a stacked semiconductor device including a plurality of semiconductor chips C1-C4 connected through TSVs and bump electrodes) comprising: a base chip configured to drive a signal path to a first voltage level during a scan operation (Wada, para. [0135]-[0142] & para. [0167]-[0171] teaches a memory chip C1, also referred to as Slice0, applying H/L test signals, and predetermined potentials to inter-chip test paths during boundary scan testing) and to detect a connection fail of the signal path from a fail information signal generated based on a fail result signal (Wada, para. [0097]-[0102] teaches returning test result data from C2 to C1 and uses the returned logic pattern to detect an open defect in the TSV/bump signal path; the returned test data equates to a fail result/fail information relationship); and a memory chip configured to drive the signal path to a second voltage level during the scan operation (Wada, para. [0135]-[0143] teaches a memory chip C2, also referred to as Slice1, with the C2’s test circuitry developing H/L node states and pulling the test path to ground depending on the test path condition) to generate the fail result signal (Wada, para. [0097]-[0102] and para. [0167]-[0170] teaches a test result that indicates whether the inter-chip connection is good or defective; it also teaches the returned pattern and node/potential conditions reveal the defect; the test result information equates to a fail result signal) and output the fail result signal to the base chip (Wada, para. [0101]-[0102] teaches memory chip C2’s outputs stored test data through its scan data output signal SDO, and C2’s SDO electrically connected to memory chip’s C1’s test pad SDO, so C2’s output is obtained through C1), wherein the signal path extends through the base chip and the memory chip (Wada, para. [0106]-[0108] & para. [0166]-[0168] teaches penetration electrodes being formed in memory chip C1 and memory chip C2, and corresponding bump electrodes of the chips are connected through the penetration electrodes; it also teaches signal paths connecting C1 to C2 through TSVs).
Wada fails to teach the memory chip outputting a fail result signal to the base chip according to a chip identification.
However, Sato, in an analogous art, teaches the memory chip outputting a fail result signal to the base chip according to a chip identification (Sato, col. 7, lines 5-10, “in the case where the identification data is stored in the storage means and where the comparison information indicates the agreement between the identification data and the fixed data, the data derivation section outputs the same data as the test result data which is outputted from the data output section”).
Wada and Sato are both considered to be analogous to the claimed invention because both are in the same field of semiconductor devices with a plurality of chips, performing boundary scan testing.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Wada to incorporate the teachings of Sato by including the functionality of outputting test result information according to chip identification data.
The suggestion/motivation for doing so would be to selectively obtain test result information from an identified chip and preventing chips that are not selected, from interfering with the test result output.
Claims 7-15 are rejected under 35 U.S.C. 103 as being unpatentable over Wada in view of Sato, as applied to claim 1 above, and further in view of Maliuk et al. (US 10,571,520), hereinafter Maliuk.
Regarding claim 7, the combination of Wada in view of Sato teaches the semiconductor device of claim 1, a fail information signal generation circuit configured to serialize the first fail result signal and the second fail result signal to generate a first fail information signal and a second fail signal, respectively (Wada, para. [0100]-[0102] teaches storing received teste information in boundary scan circuits and then serially outputting the stored test data through a scan data output signal SDO), generating the first fail information signal and the second fail information signal (Wada, para. [0097]-[0102] teaches obtaining test information corresponding to the electrical state of connection paths and serially returns that information for determining whether the paths are defective); and a fail detection circuit configured to detect connection fails of the first signal path and the second signal path based on logic levels of the first fail information signal and the second fail information signal (Wada, para. [0102] teaches detecting a connection/open failure by comparing returned logic patterns).
The combination of Wada in view of Sato, taken singly or combined, fails to teach wherein the base chip includes: a test signal generation circuit configured to generate a scan enable signal that is enabled during the scan operation, generate a scan-down signal and a scan-up signal that are selectively enabled, and generate a down-latch signal and an up-latch signal that are selectively enabled and connecting the first signal path and the second signal path based on the scan enable signal, the scan-down signal, the scan-up signal, the down-latch signal, and the up-latch signal.
However, Maliuk, in an analogous art, teaches wherein the base chip includes: a test signal generation circuit configured to generate a scan enable signal that is enabled during the scan operation (Maliuk, col. 4, lines 9-13, “The SE or scan-enable input allows selection between two modes of operation: on the next edge of the clock (CLK), the memory will store either incoming data D, or the memory may store the state of the neighbor latch as presented on the SI (scan in) input”; teaches the scan-enable input controlling scan-chain operation and selection of scan data), generate a scan-down signal and a scan-up signal that are selectively enabled (Maliuk, Figs. 3 and 4; col. 5, lines 21-28, “The direction of movement of data through latch 200 is controlled by the Sc_dir signal. When this signal is low, as in FIG. 3, the output of component latch 202 is applied to component latch 204, and data moves in the forward direction through latch circuit 200. When the Sc_dir signal is high, as in FIG. 4, the output of component latch 204 is applied to component latch 202, and data moves in the reverse direction through latch circuit 200”), and generate a down-latch signal and an up-latch signal that are selectively enabled (Maliuk, col. 2, lines 19-32 teaches first and second latches associated with the bidirectional scan arrangement and applying scan direction control to the latches to determine whether the latch circuit operates in the forward or reverse mode) and connecting the first signal path and the second signal path based on the scan enable signal, the scan-down signal, the scan-up signal, the down-latch signal, and the up-latch signal (Maliuk, col. 2, lines 19-32 teaches first and second latches associated with the bidirectional scan arrangement and applying scan direction control to the latches to determine whether the latch circuit operates in the forward or reverse mode).
Wada, Sato, and Maliuk are considered to be analogous to the claimed invention because they are in the same field of scan testing in memory devices.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Wada in view of Sato to incorporate the teachings of Maliuk by including the functionality of having a bidirectional scan and direction-controlled latch technique.
The suggestion/motivation for doing so would be to allow for test data/information to be shifted and stored no matter the scan direction, which improves testing and fault detection capabilities.
Regarding claim 8, the combination of Wada in view of Sato, further in view of Maliuk teaches the semiconductor device of claim 7, wherein the fail information signal generation circuit includes: a first fail signal generation circuit configured to generate first base data from the first fail result signal when the scan enable signal is enabled (Wada, para. [0088]-[0090] teaches boundary scan circuits that receive test-related signals, retain them internally, and subsequently output the retained values) and connect the first signal path to the first voltage source through one of the first PMOS transistor and the first NMOS transistor (Wada, para. [0128]-[0130] and para. [0188]-[0193] teaches using PMOS and NMOS transistors for driving a test node to respective voltage levels, including a PMOS transistor coupled to power supply voltage VDD and an NMOS transistor coupled to ground GND; para. [0185]-[0193] and para. [0209]-[0212] teaches each stacked chip including test circuitry that has PMOS and NMOS transistors coupled to a signal-path note, and that the resulting logic/potential level of the node is used in obtaining the test result corresponding to the connection state of the single path) based on the scan-down signal and the scan-up signal to generate a first fail signal when the scan enable signal is enabled (Maliuk, Figs. 3 and 4; col. 5, lines 21-28, “The direction of movement of data through latch 200 is controlled by the Sc_dir signal. When this signal is low, as in FIG. 3, the output of component latch 202 is applied to component latch 204, and data moves in the forward direction through latch circuit 200. When the Sc_dir signal is high, as in FIG. 4, the output of component latch 204 is applied to component latch 202, and data moves in the reverse direction through latch circuit 200”); a second fail signal generation circuit configured to generate second base data from the second fail result signal when the scan enable signal is enabled (Wada, para. [0088]-[0090] teaches boundary scan circuits that receive test-related signals, retain them internally, and subsequently output the retained values) and connect the second signal path to the first voltage source through one of the second PMOS transistor and the second NMOS transistor (Wada, para. [0128]-[0130] and para. [0188]-[0193]) based on the scan-down signal and the scan-up signal to generate a second fail signal when the scan enable signal is enabled (Maliuk, Figs. 3 and 4; col. 5, lines 21-28); and a fail information signal output circuit configured to serialize the first base data and the second base data (Wada, para. [0081] teaches the boundary scan circuit receiving multiple signals in parallel, retains them, and outputs the retained signals in series through scan-data output buffer OBT2) based on a test read signal (Wada, para. [0079] teaches using a serial output enable signal SOE to enable serial output of retained test signals during a test operation) in synchronization with a test clock signal (Wada, para. [0090] teaches that during boundary scanning, circuits fetch signals in synchronism with scan clock SCK and shift them through successive stages) to output the serialized first base data and second base data as the first fail information signal and the second fail information signal (Wada, para. [0096] teaches outputting the retained scan/test data serially as SD0; the serialized test result values equate to fail information outputs) and to serialize the first fail signal and the second fail signal to output the serialized first fail signal and second fail signal as the first fail information signal and the second fail information signal when a base read signal is enabled (Wada, para. [0078]-[0079] and para. [0091]-[0096] teaches different output selection/control modes: a parallel output selection signal PDS, serial output enable S0E, and different normal/test output behavior).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Wada in view of Sato to incorporate the teachings of Maliuk by including the functionality of having a bidirectional scan and direction-controlled latch technique.
The suggestion/motivation for doing so would be to allow for test data/information to be shifted and stored no matter the scan direction, which improves testing and fault detection capabilities.
Regarding claim 9, the combination of Wada in view of Sato, further in view of Maliuk teaches the semiconductor device of claim 8, wherein the first fail signal generation circuit includes: a first switching circuit configured to connect the first signal path to a first node to generate the first base data from the first fail result signal when the scan enable signal is enabled (Wada, para. [0121]-[0125] teaches the bump/test path node is coupled through an input buffer to switch circuit 54a, and the input buffer receives the signal from the bump/test node and outputs the signal to the switch circuit); a first driving circuit configured to drive a voltage level of the first node by one of the first PMOS transistor and the first NMOS transistor (Wada, para. [0188]-[0193] teaches PMOS and NMOS transistors driving the voltage of Node1 and PMOS1 has its source connected to VDD and drain connected to Node1, as well as NMOS3 has its drain connected to Node1 and source grounded) based on the scan-down signal and the scan-up signal to generate the first base data (Maliuk, Figs. 3 and 4; col. 5, lines 21-28, “The direction of movement of data through latch 200 is controlled by the Sc_dir signal. When this signal is low, as in FIG. 3, the output of component latch 202 is applied to component latch 204, and data moves in the forward direction through latch circuit 200. When the Sc_dir signal is high, as in FIG. 4, the output of component latch 204 is applied to component latch 202, and data moves in the reverse direction through latch circuit 200”); a first storage circuit configured to store the first base data based on the down-latch signal and the up-latch signal (Maliuk, Figs. 3 and 4; col. 5, lines 21-28) and generate a first base comparison signal from the stored first base data (Wada, para. [0209]-[0215] teaches using stored/propagated test logic levels to determine whether the connection is normal or defective); and a first test mode control circuit configured to output the first base comparison signal as the first fail signal (Wada, para. [0185] teaches test circuitry using the resulting logic/potential state to produce a test result indicating whether the corresponding TSV path is connected or defective).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Wada in view of Sato to incorporate the teachings of Maliuk by including the functionality of having a bidirectional scan and direction-controlled latch technique.
The suggestion/motivation for doing so would be to allow test information to be transferred and stored in either scan direction to use in generating a signal indicating the test result of the signal path.
Claim 10 teaches the second signal path counterpart of the circuitry taught in claim 9. Wada teaches that the respective test circuits associated with the stacked memory chip signal paths have th3e same circuit configuration. Accordingly, the rejection of claim 9 applies to the corresponding limitations of claim 10.
Regarding claim 11, the combination of Wada in view of Sato, further in view of Maliuk teaches the semiconductor device of claim 8, wherein the fail information signal output circuit includes: a first fail information signal output circuit configured to generate the first fail information signal based on the first base data when the base read signal is disabled in synchronization with the test clock signal (Wada, para. [0075] and [0090] teaches the boundary scan circuit having latch/fetch test related signals in synchronization with scan clock SCK and retain those signals for output, as well as the SCK controlling signals to select which source of data is captured/output) and to generate the first fail information signal based on the first fail signal when the base read signal is enabled (Wada, para. [0054] teaches selectable signal routing through switch circuit 54a and different output behavior depending on test/control signals, and the switch circuit 54a selects between normal and test command, clock, and data signals); and a second fail information signal output circuit configured to generate the second fail information signal based on the second base data to output the second fail information signal to an output pad when the base read signal is disabled and the test read signal is disabled in synchronization with the test clock signal (Wada, para. [0089]-[0096] teaches retaining respective channel/path signals and outputting them through output buffers, with output determined by control signals such as PDS, POE, SOE, and SSH), to generate the second fail information signal based on the first fail information signal to output the second fail information signal to the output pad when the base read signal is disabled and the test read signal is enabled in synchronization with the test clock signal (Wada, para. [0090] teaches the output of a boundary scan circuit becoming the input to node N2 of the next stage, which allows stored data to move through the chain toward the last output buffer; it also teaches that during the test operation, the input data’s movement occurs in synchronization with the scan clock signal SCK ), and to generate the second fail information signal based on the second fail signal to output the second fail information signal to the output pad when the base read signal is enabled in synchronization with the test clock signal (Wada, para. [0096] teaches selectable test data routing/output, with the serial output enable signal SOE causes the retained signals in the respective boundary scan circuits to be output in succession through the final output buffer OBT2 as scan data output signal SDO).
Regarding claim 12, the combination of Wada in view of Sato, further in view of Maliuk teaches the semiconductor device of claim 1, wherein the first memory chip further includes a first fail result signal generation circuit connected to the first signal path (Wada, para. [0164]-[0166] teaches memory chip C2 including a test circuit that is connected with its terminal/bump electrodes and the corresponding TSV signal paths, and the CS test circuit responds to the electrical state of the path and produces the corresponding test-result condition) and is configured to connect the first signal path to the second voltage source (Wada, para. [0161]-[0165] teaches memory chip test circuitry that includes transistor controlled connections to supply/ground, specifically the test circuitry responds to path/node potential and can turn on NMOS transistors to produce a current path corresponding to the test result) based on the scan-down signal and the scan-up signal (Maliuk, Figs. 3 and 4; col. 5, lines 21-28 teaches controlling scan operation in opposite directions using its scan direction signal, with low selecting forward operation and high selecting reverse operation) to generate the first fail result signal (Wada, para. [0167]-[0171] teaches generating an observable electrical/test result condition based on whether the TSC connection is intact or defective, and the defect changes the relevant node potential and causes a current/potential change used to determine the failing slice/path) when the chip ID has the first combination (Sato, col. 7, lines 5-10, “in the case where the identification data is stored in the storage means and where the comparison information indicates the agreement between the identification data and the fixed data, the data derivation section outputs the same data as the test result data which is outputted from the data output section”) and output the first fail result signal to the first signal path (Wada, para. [0102] and para. [0226]-[0230] teaches the memory chip test condition is communicated through the stacked chip test paths as a current/potential change corresponding to the tested slice/path; it also teaches that test data from chip C2 is returned through the connected scan/test path of chip C1).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Wada in view of Sato to incorporate the teachings of Maliuk by including the functionality of having a bidirectional scan control technique.
The suggestion/motivation for doing so would be to allow the memory chip test circuit to operate with selectable scan directions while outputting test result information for the selected memory chip and signal path.
Regarding claim 13, the combination of Wada in view of Sato, further in view of Maliuk teaches the semiconductor device of claim 12, wherein the first fail result signal generation circuit includes: a first memory control circuit configured to generate a first switching signal and a first memory read signal that are enabled when a core read signal is enabled (Wada, para. [0096] teaches selectable test data routing/output, with the serial output enable signal SOE causes the retained signals in the respective boundary scan circuits to be output in succession through the final output buffer OBT2 as scan data output signal SDO) and the chip ID has the first combination (Sato, col. 7, lines 5-10, “in the case where the identification data is stored in the storage means and where the comparison information indicates the agreement between the identification data and the fixed data, the data derivation section outputs the same data as the test result data which is outputted from the data output section”); a third switching circuit configured to connect the first signal path to a third node and output first memory data as the first fail result signal when the first switching signal is enabled (Wada, para. [0121]-[0125] teaches the bump/test path node is coupled through an input buffer to switch circuit 54a, and the input buffer receives the signal from the bump/test node and outputs the signal to the switch circuit); a third driving circuit configured to drive a voltage level of the third node by one of the third PMOS transistor and the third NMOS transistor (Wada, para. [0188]-[0193] teaches PMOS and NMOS transistors driving the voltage of Node1 and PMOS1 has its source connected to VDD and drain connected to Node1, as well as NMOS3 has its drain connected to Node1 and source grounded) based on the scan-down signal and the scan-up signal to generate the first memory data when the first memory read data is disabled (Maliuk, Figs. 3 and 4; col. 5, lines 21-28, “The direction of movement of data through latch 200 is controlled by the Sc_dir signal. When this signal is low, as in FIG. 3, the output of component latch 202 is applied to component latch 204, and data moves in the forward direction through latch circuit 200. When the Sc_dir signal is high, as in FIG. 4, the output of component latch 204 is applied to component latch 202, and data moves in the reverse direction through latch circuit 200”) and to drive a voltage level of the third node by one of the third PMOS transistor and the third NMOS transistor based on a first pass signal to generate the first memory data when the first memory read signal is enabled (Wada, para. [0209]-[0215] teaches that logic generated from the tested node controls downstream transistor conduction, for example, the resulting node/NOR/ inverter state determines whether associated NMOS transistors turn on or remain off); a third storage circuit configured to store the first memory data based on the down-latch signal and the up-latch signal (Maliuk, Figs. 3 and 4; col. 5, lines 21-28) and to generate a first memory comparison signal from the stored first memory data (Wada, para. [0209]-[0215] teaches using stored/propagated test logic levels to determine whether the connection is normal or defective); and a first core test mode control circuit configured to output the first memory comparison signal as the first pass signal (Wada, para. [0119] teaches test logic converting the detected node state into a control/output condition that determines transistor activation and thereby the test result).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Wada in view of Sato to incorporate the teachings of Maliuk by including the functionality of having a bidirectional scan and latch control technique.
The suggestion/motivation for doing so would be to allow for test information in a selected memory chip can be selectively driven, stored, and used to control test operations in either scan direction.
Claim 14 teaches the second memory chip counterpart of the circuitry taught in claim 12. Wada teaches corresponding test circuitry and signal paths for the stacked memory chip, Sato teaches chip ID-based selection of test result output, and Maliuk teaches selectable bidirectional scan control. Accordingly, the rejection of claim 12 applies to the corresponding limitations of claim 14.
Claim 15 teaches the second memory chip counterpart of the circuitry taught in claim 13. Wada teaches corresponding test circuitry for the respective stacked memory chip signal paths, Sato teaches chip ID-based selection, and Maliuk teaches selectable bidirectional scan/latch control. Accordingly, the rejection of claim 13 applies to the corresponding limitations of claim 15.
Claims 16-19 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Wada in view of Sato, and further in view of Damodaran et al. (US 7,325,178), hereinafter Damodaran.
Regarding claim 16, Wada teaches a semiconductor device (Wada, Figs. 3A and 3B show a stacked semiconductor device including a plurality of semiconductor chips C1-C4 connected through TSVs and bump electrodes) comprising: a base chip (Wada, Figs. 3A and 3B; para. [0042], lines 1-3, “As shown in FIG. 5, the chip C1 includes the channels a to d, a boundary scan control circuit 50 (hereinafter, BS control circuit 50)”; C1 equates to the base chip) configured to drive a signal path to a first voltage level during a scan operation (Wada, para. [0167]-[0171] & para. [0218]-[0224] teach electrically testing inter-chip paths during the scan/test operation, as well as applying electrical signals to paths containing penetration electrodes and observing resulting node potentials/currents to determine connectivity), and to generate the fail information signal based on a fail result signal to detect a connection fail of the signal path (Wada, para. [0097]-[0102] & para. [0218]-[0224] teach C2 returning test data through an inter-chip connection to C1 with the returned test result data indicating whether the penetration electrode/bump path is properly connected); and a memory chip (Wada, para. [0097]-[0102] teaches memory chip C2 receiving test data through the penetration electrodes from C1 and subsequently outputs stored test data back toward C1) configured to drive the signal path to a second voltage level to generate the fail result signal during the scan operation (Wada, para. [0167]-[0171] & para. [0218]-[0224] teaches driving inter-chip test path from the other chip/test circuitry and evaluating resulting logic/node states), and output the fail result signal to the base chip (Wada, para. [0097]-[0102] teach that after C2 receives/stores test data, the stored data are serially output through C2’s scan data output signal SDO, as well as C2’s SDO is electrically connected to the test pad SDO of C1, in a way that the data output from C2 can be obtained through C1).
Wada fails to teach the base chip being configured to generate a fail information signal at a second logic level after generating the fail information signal at a first logic level during a test mode, the memory chip being configured to generate the fail result signal at the second logic level after generating the fail result signal at the first logic level during the test mode, and the memory chip outputting the fail result signal to the base chip according to a chip identification (ID).
However, Sato, in an analogous art, teaches the memory chip outputting the fail result signal to the base chip according to a chip identification (ID) (Sato, col. 7, lines 5-10, “in the case where the identification data is stored in the storage means and where the comparison information indicates the agreement between the identification data and the fixed data, the data derivation section outputs the same data as the test result data which is outputted from the data output section”).
Wada and Sato are both considered to be analogous to the claimed invention because both are in the same field of semiconductor devices with a plurality of chips, performing boundary scan testing.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Wada to incorporate the teachings of Sato by including the functionality of outputting test result information according to chip identification data.
The suggestion/motivation for doing so would be to selectively obtain test result information from an identified chip and preventing chips that are not selected, from interfering with the test result output.
The combination of Wada in view of Sato, taken singly or combined, fails to teach the base chip being configured to generate a fail information signal at a second logic level after generating the fail information signal at a first logic level during a test mode, and the memory chip being configured to generate the fail result signal at the second logic level after generating the fail result signal at the first logic level during the test mode.
However, Damodaran, in an analogous art, teaches the base chip being configured to generate a fail information signal at a second logic level after generating the fail information signal at a first logic level during a test mode, and the memory chip being configured to generate the fail result signal at the second logic level after generating the fail result signal at the first logic level during the test mode (Damodaran, col. 10, lines 1-32 teaches a 1-bit FSRF fail flag is cleared when reset, start, or PBIST_enable is activated, which represents failure status of the current execution phase, and is then driven high the moment a negative comparison occurs; FSRF also drives the pBIST_fail output).
Wada, Sato, and Damodaran are considered to be analogous to the claimed invention because they are in the same field of memory testing operations.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Wada in view of Sato to incorporate the teachings of Damodaran by including the functionality of initially setting a failure status signal to a first logic level when testing begins, and then changed to a second logic level when a failure is detected.
The suggestion/motivation for doing so would be to provide an initial test status and indicate when the test detects a failure.
Claim 17 is a device with limitations similar to the device of claim 2, and is rejected under the same rationale.
Regarding claim 18, the combination of Wada in view of Sato, further in view of Damodaran teaches the semiconductor device of claim 16, wherein the memory chip drives the signal path to the second voltage level by one of a second PMOS transistor and a second NMOS transistor during the scan operation (Wada, para. [0185]-[0193] and para. [0209]-[0212] teaches each stacked chip including test circuitry that has PMOS and NMOS transistors coupled to a signal-path note, and that the resulting logic/potential level of the node is used in obtaining the test result corresponding to the connection state of the single path).
Regarding claim 19, the combination of Wada in view of Sato, further in view of Damodaran teaches the semiconductor device of claim 16, wherein the base chip detects no fail in the signal path when the fail information signal is generated at the first logic level after the scan operation (Wada, para. [0136] and [0148] teaches determining whether a signal path is properly connected based on the resulting logic/potential state of the test signal, wherein, when an open defect does not exist, the monitored test node remains in the expected state, thereby indicating no failure of the tested path).
Regarding claim 21, the combination of Wada in view of Sato, further in view of Damodaran teaches the semiconductor device of claim 16, wherein the base chip detects an open fail including a disconnect in the signal path when the fail information signal is generated at one of the first logic level and the second logic level during the test mode and the fail information is generated at a same logic level as the fail information signal during the test mode during the scan operation (Wada, para. [0135] and [0149] teaches detecting an open connection based on a failure of the tested signal to transition from its prior logic state, wherein, when the inter-chip connection is open, the corresponding nose is not changed to the expected H level and instead remains at its prior L level; it also teaches determining an open failure when the logic state after the test operation remains the same as the logic state prior to the attempted signal transfer).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Wada in view of Sato, further in view of Damodaran, as applied to claim 16 above, and further in view of Chakrabarty et al. (US 10,444,279), hereinafter Chakrabarty.
Regarding claim 20, the combination of Wada in view of Sato, further in view of Damodaran teaches the semiconductor device of claim 16, wherein the base chip is configured to detect fail information (Wada, para. [0170] teaches a defect indication of chip C1 that when the inter-chip TSV is defective, the condition in chip C2 causes a potential change in a signal applied at a test pad for chip C1, and that potential change is used to determine that a defect exists in the path) and when the fail information signal is generated at the second logic level (Damodaran, col. 10, lines 1-32 teaches a 1-bit FSRF fail flag is cleared when reset, start, or PBIST_enable is activated, which represents failure status of the current execution phase, and is then driven high the moment a negative comparison occurs; FSRF also drives the pBIST_fail output) after the scan operation (Wada, para. [0101]-[0102] teaches that following the boundary scan transfer and storage operation , the stored test data are serially output, and the resulting output logic levels are subsequently used to determine whether the tested signal path contains a defect).
The combination of Wada in view of Sato, further in view of Damodaran, taken singly or combined, fails to teach the base chip being configured detects a resistance fail in the signal path.
However, Chakrabarty, in an analogous art, teaches the base chip being configured detects a resistance fail in the signal path (Chakrabarty, col. 8, lines 18-22 teaches dete4cting a resistance failure in a TSV signal path, wherein a resistive-open defect increases the resistance of the TSV and produces a measurable deviation from a fault-free test response).
Wada, Sato, Damodaran, and Chakrabarty are considered to be analogous to the claimed invention because they are in the same field of memory testing operations.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Wada in view of Sato, further in view of Damodaran to incorporate the teachings of Chakrabarty by including the functionality of detecting resistive connection failures.
The suggestion/motivation for doing so would be to detect additional defects of the tested TSV signal path, including defects that increase the resistance of the TSV.
Claims 22-26 are rejected under 35 U.S.C. 103 as being unpatentable over Wada in view of Sato, further in view of Damodaran, as applied to claim 16 above, and further in view of Maliuk.
Claim 22 teaches scan and latch control limitations similar to those taught in claim 7. Maliuk teaches the bidirectional scan and direction-controlled latch operations relied upon with respect to claim 7. Accordingly, it would have been obvious to further modified the combination of Wada in view of Sato, further in view of Damodaran, to incorporate the teachings of Maliuk for the reasons discussed in claim 7’s rejection.
Claim 23 is a device with limitations similar to the device of claim 8, and is rejected under the same rationale.
Claim 24 is a device with limitations similar to the device of claim 9, and is rejected under the same rationale.
Claim 25 is a device with limitations similar to the device of claim 12, and is rejected under the same rationale.
Claim 26 is a device with limitations similar to the device of claim 13, and is rejected under the same rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kang (US 2012/0138927) teaches stacked memory devices, utilizing TSV connection testing and defect measurement.
Takeoka et al. (US 7,348,595) teaches multi-chip boundary scan and inter-chip wiring defect detection.
Alvarez-Icaza Rivera et al. (US 9,244,124) teaches scan testing, scan-out results, and pass/fail defect determination.
Goel et al. (US 10,156,607) teaches bidirectional scan chain and forward/backward shifting.
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/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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