Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) based upon an application filed in CHINA on 08/16/2023.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 and 14-19 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over US20180226378A1; Hung et al.; (hereinafter “Hung”).
Regarding Claim 1, Hung teaches a package structure (Figures 20-21, [0010]), comprising:
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a plurality of second interconnect metal traces and bonding pads in a same plane, wherein the bonding pads are electrically connected to a portion of the plurality of second interconnect metal traces (#34, Figure 20 of Hung annotated, redistribution layers comprise known interconnected metal traces/pads, [0031] and [0035]), and the plurality of second interconnect metal traces and the bonding pads comprise first surfaces (#S1) and second surfaces (#S2) that are opposite;
a plurality of first surface metal bumps (#56, solder regions) and first interconnect metal traces (#44) disposed on the first surfaces (#S1) of the plurality of second interconnect metal traces (#34);
a plurality of passive devices (#54) correspondingly mounted on top surfaces of the plurality of first surface metal bumps (#56), wherein the plurality of passive devices (#54) are correspondingly electrically connected to the first surface metal bumps (#56) and the first interconnect metal traces (#44);
a first molding layer (#58 and #26, encapsulate/insulating layer) encapsulating the plurality of passive devices (#54), the plurality of first surface metal bumps (#56), and the first interconnect metal traces (#44), and covering the first surfaces (#S1) of the bonding pads (#34);
a dielectric layer (#24-26) covering the second surfaces (#S2) of the second interconnect metal traces (#34) and a bottom surface of the first molding layer (#58), wherein openings exposing the second surfaces of the bonding pads are defined in the dielectric layer ([0035], Figure 19, openings #84 form in dielectric #24 prior);
a first chip (#90) comprising a back face (#BF) and a functional face (#FF) that are opposite, wherein second bonding pads (#BP2) are arranged on the functional face (#FF) of the first chip, and the back face (#BF) of the first chip is mounted on a surface of the dielectric layer (#24); and
metal wires (#MW) electrically connecting the second bonding pads to the second surfaces of the bonding pads ([0036], #MW connects pad #BP2 to #34 through metal pads of package/interposer #92 and bump #88 in overlying package #86).
Regarding Claim 2, Hung teaches the package structure as described in claim 1, wherein Hung further teaches the bonding pads (#34, Figure 20 of Hung annotated) are disposed outside the plurality of first surface metal bumps (#56); and the package structure further comprises a plurality of second metal bumps (#MB2, portions of metal post #50, [0020]) on the first surfaces (#S1) of the bonding pads (#34), wherein the plurality of second metal bumps (#MB2) are disposed outside the plurality of first surface metal bumps (#56), the bonding pads (#34) are correspondingly electrically connected to the plurality of first surface metal bumps (#56) and the first interconnect metal traces (#44) via a portion of the plurality of second interconnect metal traces (#34), and the first molding layer (#58) at least further covers sidewall surfaces of the plurality of second metal bumps (#MB2).
Regarding Claim 3, Hung teaches the package structure as described in claim 1, wherein Hung further teaches the bonding pads (#34, Figure 20 of Hung annotated) are disposed on bottom surfaces of a portion of the plurality of first surface metal bumps (#56).
Regarding Claim 4, Hung in view of Herald teaches the package structure as described in claim 1, wherein Hung further teaches a third metal bump (#MB5, Figure 20 of Hung annotated) disposed on the first surfaces (#S1) of a portion of the plurality of second interconnect metal traces (#34-44); and
a first heat sink (#50, [0026], metal posts comprise material such as copper which is commonly used in thermal management structure, as also disclosed in [0088] of the instant application), wherein the first heat sink (#50) is mounted on a top surface of the third metal bump (#MB5), and the first molding layer further covers at least covers sidewall surfaces of the first heat sink.
Regarding Claim 5, Hung in view of Herald teaches the semiconductor package as described in claim 4, wherein Hung further teaches the third metal bump (#MB5, Figure 20 of Hung annotated) is disposed between the plurality of first surface metal bumps (#56), and is opposite to a mount position of the first chip (#MB5 disposes on surface #S1 opposite to surface #S2).
Regarding Claim 6, Hung in view of Herald teaches the semiconductor package as described in claim 4, wherein Hung further teaches in a case that plurality of second metal bumps (#MB2, Figure 20 of Hung annotated) are formed on the first surfaces (#S1) of the bonding pads (#34), the package structure further comprises second heat sinks (#50, copper metal posts), wherein the second heat sinks (#50) are mounted on top surfaces of the plurality of second metal bumps (#MB2), and the first molding layer (#58) at least further covers sidewall surfaces of the second heat sinks (#50).
Regarding Claim 7, Hung teaches the package structure as described in claim 1, wherein Hung further teaches a plurality of discrete fourth metal bumps (#MB3, Figure 20 of Hung annotated) disposed on the first surfaces (#S1) of the plurality of second interconnect metal traces (#34); and a second chip (#52), wherein the second chip (#52) is flip-mounted on top surfaces of the fourth metal bumps (#MB3), and the second chip (#52) is electrically connected to the fourth metal bumps (#MB3); wherein the first molding layer (#58) further covers sidewall surfaces of the fourth metal bumps (#MB3) and surfaces of the second chip (#52).
Regarding Claim 14, Hung teaches the package structure as described in claim 1, wherein Hung further teaches a portion of the plurality of first surface metal bumps are discrete (Figure 20 of Hung annotated, bumps #56 include discreet portions such as bumps #MB3), and a portion of the plurality of first surface metal bumps (#56) are connected via the first interconnect metal traces (#44).
Regarding Claim 15, Hung teaches a method for forming a package structure ([0010]), comprising:
providing a metal foil (#30, Figure 3, [0015], seed layer), wherein the metal foil comprises a first surface and a second surface that are opposite (#30 comprises opposite surfaces);
forming a plurality of first surface metal bumps and first interconnect metal traces on the first surface of the metal foil (Figure 10, solder regions/bumps #56 and RDLs #44 form on the first surface of seed layer #30 where RDLs #34 form);
mounting a plurality of passive devices (#54) on top surfaces of the plurality of first surface metal bumps (#56), wherein the plurality of passive devices (#54) are correspondingly electrically connected to the plurality of first surface metal bumps (#56) and the first interconnect metal traces (#44);
forming a first molding layer (#58, Figure 12), wherein the first molding layer encapsulates the plurality of passive devices, the plurality of first surface metal bumps, and the first interconnect metal traces, and covers the first surface of the metal foil (encapsulate/insulating layer #58 and #26 cover devices #54, bumps #56 and RDLs #44 and top surface of seed layer #30/RDLs #34);
etching the metal foil from the second surface of the metal foil to form a plurality of second interconnect metal traces and bonding pads (Figure 4, [0016], RDLs/metal traces/pads #34 are formed by known methods such as metal plating and etching process of seed layer #30) that are correspondingly electrically connected to the plurality of first surface metal bumps (#56) and the first interconnect metal traces (#44);
forming a dielectric layer (#24-26/36, Figure 12) covering the plurality of second interconnect metal traces (#34) and a bottom surface of the first molding layer (#58), wherein openings (#84, Figure 19) exposing surfaces of the bonding pads (#34) are defined in the dielectric layer (#24);
providing a first chip (#90, Figure 20 of Hung annotated), wherein the first chip comprises a back face (#BF) and a functional face (#FF) that are opposite, second bonding pads (#BP2) being arranged on the functional face (#FF);
mounting the back face (#BF) of the first chip (#90) on a surface of the dielectric layer (#24); and
forming metal wires (#MW) electrically connecting the second bonding pads to the bonding pads ([0036], #MW connects pad #BP2 to #34 through metal pads of package/interposer #92 and bump #88 in overlying package #86).
Regarding Claim 16, Hung teaches the package structure as described in claim 15, wherein Hung further teaches a portion of the plurality of first surface metal bumps are discrete (Figure 20 of Hung annotated, bumps #56 include discreet portions such as bumps #MB3), and a portion of the plurality of first surface metal bumps are connected via the first interconnect metal traces (RDLs #44 connect bumps #56); and the method further comprises: providing a carrier plate (#20, [0012]), wherein the metal foil is disposed on a surface of the carrier plate (Figure 3, seed layer #30 disposes on carrier #20); and removing the carrier plate prior to etching the second surface of the metal foil or after forming the first molding layer ([0034], carrier #20 is removed after forming encapsulating layer #58).
Regarding Claim 17, Hung teaches the package structure as described in claim 15, wherein Hung further teaches forming a plurality of discrete second metal bumps (#MB2, Figure 20 of Hung annotated) on the first surface (#S1) of the metal foil, wherein the plurality of discrete second metal bumps (#MB2) are disposed outside the plurality of first surface metal bumps (#56), the bonding pads (#34) are formed on bottom surfaces of the plurality of discrete second metal bumps (#56), and the bonding pads are correspondingly electrically connected to the plurality of first surface metal bumps and the first interconnect metal traces via a portion of the plurality of second interconnect metal traces (metal traces/pads #34 connect to bumps #56 and RDLs #44); wherein the first molding layer (#58) further at least covers sidewall surfaces of the plurality of discrete second metal bumps (#MB2) and the first interconnect metal traces (encapsulating layer #58-#26 cover bumps #MB2 and RDLs #44).
Regarding Claim 18, Hung teaches the package structure as described in claim 15, wherein Hung further teaches forming a third metal bump (#MB5, Figure 20 of Hung annotated) on the first surface (#S1) of the metal foil, wherein a portion of the plurality of second interconnect metal traces (#44) formed upon etching the metal foil are electrically connected to the third metal bump (#MB5); and providing a first heat sink (#50, [0026], metal posts comprise material such as copper which is commonly used in thermal management structure, see also [0088] of the instant application), wherein the first heat sink (#50) is mounted on a top surface of the third metal bump (#MB5); wherein the first molding layer (#58) further covers sidewall surfaces of the third metal bump (#MB5) and at least covers sidewall surfaces of the first heat sink (#50).
Regarding Claim 19, Hung teaches the package structure as described in claim 18, wherein Hung further teaches in a case that a plurality of discrete second metal bumps (#MB2, Figure 20 of Hung annotated) are formed on the first surface (#S1) of the metal foil, the method further comprises: providing second heat sinks (#50, copper metal posts), wherein the second heat sinks (#50) are mounted on top surfaces of the plurality of discrete second metal bumps (#MB2); wherein the first molding layer (#58) at least further covers sidewall surfaces of the second heat sinks (#50).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 8-13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hung in view of US20160307872A1; Chen et al.; (hereinafter “Chen”).
Regarding Claim 8, Hung teaches the package structure as described in claim 1.
Hung does not explicitly teach a plurality of external pads are arranged on the functional face of the first chip; and the first chip further comprises external protrusions that protrude from a surface of the functional face and are electrically connected to a portion of the plurality of external pads.
However, Chen teaches a comparable package structure ([0014]), comprising a plurality of external pads (#56, Figure 21, metal pillars) arranged on the functional face of a first chip (top/functional surface of device die #52); and the first chip further comprises external protrusions (#68, electrical connectors) that protrude from a surface of the functional face (top/functional surface of die #52) and are electrically connected to a portion of the plurality of external pads (#56, [0033]).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Hung with the teaching of Chen by known methods to yield predictable results (providing electrical connection between the chip and other devices). See MPEP 2143(I)(A).
Regarding Claim 9, Hung in view of Chen teaches the package structure as described in claim 8, wherein Hung further teaches the external protrusions (see rejection of claim 8, #68, Figure 21 of Chen) are electrically bonded to a portion of the plurality of external pads, or the external protrusions are electrically connected to a portion of the plurality of external pads via redistribution layers ([0033] of Chen, connectors #68 connects to metal pillars #56 via RDLs #64).
Regarding Claim 10, Hung in view of Chen teaches the package structure as described in claim 9.
Hung does not explicitly teach a portion of the plurality of external pads are directly used as the second bonding pads, or a portion of the redistribution layers are used as the second bonding pads.
However, Chen teaches a portion of the plurality of external pads are directly used as the second bonding pads, or a portion of the redistribution layers are used as the second bonding pads (Figure 21, metal pillar #56 of die #52 connects to die #36 via RDLs #64 and metal post #50).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Hung with the teaching of Chen for reason set forth in rejection of claim 8.
Regarding Claim 11, Hung in view of Chen teaches the package structure as described in claim 9, wherein Hung further teaches a second molding layer encapsulating the first chip, the metal wires, and the second bonding pads (Figure 20 of Hung annotated, an encapsulation layer encapsulates dies #90, wires #MW and pads #BP2).
Regarding Claim 12, Hung in view of Chen teaches the package structure as described in claim 9, wherein Hung further teaches the external protrusions are solder balls or metal core balls, or the external protrusions comprise metal pillars and solder balls disposed on top surfaces of the metal pillars (see rejection of claim 8, Figure 21 of Chen, [0033], connectors #68 comprise metal pillars and/or solder balls).
Regarding Claim 13, Hung teaches the package structure as described in claim 1, wherein Hung further teaches fifth metal bumps (#MB5, Figure 20 of Hung annotated) disposed on the first surfaces (#S1) of the plurality of second interconnect metal traces (#34); a plurality of sixth metal bumps (#50), wherein the plurality of sixth metal bumps (#50) are respectively mounted on top surfaces of plurality of second metal bumps (#BM2) and the fifth metal bumps (#BM5), and the first molding layer (#58) further covers sidewall surfaces of the plurality of sixth metal bumps and exposes top surfaces of the plurality of sixth metal bumps (encapsulating layer #58 only covers sidewalls of metal posts #50); and solder balls (#60/#76) disposed on the top surfaces of the plurality of sixth metal bumps (#50).
Hung does not teach a plurality of external pads are arranged on the functional face of the first chip; and the first chip further comprises: third heat sinks that protrude from a surface of the functional face and are electrically connected to a portion of the plurality of external pads.
However, Chen teaches a plurality of external pads (#56, Figure 21, metal pillars) are arranged on the functional face of the first chip (top/functional surface of device die #52); and the first chip (#52) further comprises: third heat sinks ([0027], metal pillars #56 comprise conductive material such as copper/aluminum, which is commonly used in thermal management structure, as also disclosed in [0088] of the instant application) that protrude from a surface of the functional face (#56 protrude from top/functional surface of device die #52) and are electrically connected to a portion of the plurality of external pads (Figure 21, [0031], RDLs #64 electrically couple multiple of pillars #56).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Hung with the teaching of Chen by known methods to yield predictable results (providing electrical connection between the chip and other devices and further heat dissipating capability to the chip).
Regarding Claim 20, Hung teaches the package structure as described in claim 17, wherein Hung further teaches forming a plurality of discrete fifth metal bumps (#MB5, Figure 20 of Hung annotated) on the first surface (#S1) of the metal foil, wherein a portion of the metal traces (#34) formed upon etching the metal foil are electrically connected to the fifth metal bumps (#MB5); providing a plurality of sixth metal bumps (#50), wherein the plurality of sixth metal bumps (#50) are respectively mounted on top surfaces of the plurality of discrete second metal bumps (#MB2) and the fifth metal bumps (#MB5), and the first molding layer (#58) further covers sidewall surfaces of the plurality of sixth metal bumps and exposes top surfaces of the plurality of sixth metal bumps (encapsulating layer #58 only covers sidewalls of metal posts #50); and forming solder balls (#60/#76) on the top surfaces of the plurality of sixth metal bumps (#50).
Hung does not teach a plurality of external pads are arranged on the functional face of the first chip; the first chip further comprises third heat sinks that protrude from a surface of the functional face and are electrically connected to a portion of the plurality of external pads.
However, Chen teaches a plurality of external pads (#56, Figure 21, metal pillars) are arranged on the functional face of the first chip (top/functional surface of device die #52); and the first chip (#52) further comprises: third heat sinks ([0027], metal pillars #56 comprise conductive material such as copper/aluminum, which is commonly used in thermal management structure, as also disclosed in [0088] of the instant application) that protrude from a surface of the functional face (#56 protrude from top/functional surface of device die #52) and are electrically connected to a portion of the plurality of external pads (Figure 21, [0031], RDLs #64 electrically couple multiple of pillars #56).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Hung with the teaching of Chen by known methods to yield predictable results (providing electrical connection between the chip and other devices and further heat dissipating capability to the chip).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US20210118757A1 – Figures 1A-R and 10
US20190067207A1 – Figures 13-17
US20190057911A1 – Figures 2A-G
US20170062383A1 – Figures 13-16
US20130077262A1 – Figures 1 or 9
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/TIEN TRAN/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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