DETAILED ACTION
This non-final action is responsive to the following communications: application filed on 08/01/2024.
Claims 1-20 are pending. Claims 1, 8, and 15 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. D) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103. E) MPEP 2163 guidelines teach that drawing and specification must be examined to assess whether an originally-filed claim has adequate support in the written disclosure and/or the drawings. Possession may be shown by a clear depiction of the invention in detailed drawings.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Domestic Priority
4. See ADS for domestic CON priority details.
Information Disclosure Statement
5. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 08/01/2024. This IDS has been considered.
Specification Objection
6. The Title is objected to because the title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
“Memory device with replica circuity to detect voltage drop in memory cells and method of compensation”.
Drawing Objection
7. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following claim language (see strike-out limitations) must be shown or the feature(s) canceled from the claim(s). Claims are directed to Figure 4 which do not show these features. Other drawings e.g. Figures 1-3 also do not show these features. No new matter should be entered.
Claim 1. A voltage regulation circuit for a memory device, comprising:
a first circuit including: a
(Drawings do not show parallel setup and one selection. Further, drawings do not show clearly muxes, switches)
a second circuit including: a
configured to control operations of the first switching mechanism and the second switching mechanism. (Drawings do not show clearly muxes, switches, signals)
Claim 7. The voltage regulation circuit of claim 1, wherein
Corrected drawing sheets in compliance with 37 CFR 1.121 (d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as "amended." If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either "Replacement Sheet" or "New Sheet" pursuant to 37 CFR 1.121 (d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objection
8. Claims 1, 7 and all dependent claims inclusive of claims 1-7 are objected to because the claims (claim language) are not readable on the drawings. See drawing objection above.
Claim Rejections - 35 USC § 112
9. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
10. Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
MPEP 2173.02(II) instructs examiners that definiteness of claim language is determined, not in a vacuum, but in light of: (A) the content of the originally filed disclosure; (B) the prior art; and (C) the perspective of one having ordinary skill in the art. Further, the Federal Circuit explained that for definiteness requirement rejections, the USPTO initially issues a well-grounded rejection by "identifying ways in which language in a claim is ambiguous, vague, incoherent, opaque, or otherwise unclear in describing and defining the claimed invention." see In re Packard,751 F.3d 1307, 1311 (Fed. Cir. 2014).
Following limitations in claim 1 and claim 7 are undefined, vague and incoherent in its use:
“first switching mechanism” (claim 1, lines 4, 12-13)
“second switching mechanism” (claim 1, lines 9, 12-13)
“control mechanism” (claim 1, line 12; claim 7, line 1)
Switching mechanism can be a system with different combinations of switches (transistor combinations), pass gates, muxes, interconnected parts, components, or processes that work together to perform a specific function. Types of “switching mechanism” can be indefinite. Similarly, control mechanism can be a system with different combinations of control signals, pass gates, muxes, interconnected parts, components to perform a specific function. Thus “switching mechanism” and “control mechanism” can be implemented in numerous different ways.
Applicant's disclosure only provides three examples of the "switching mechanism": para [0017] teaches switching mechanism capable of programmatically selecting between supplying two voltages. Para [0022] teaches switching mechanism is configured to select between two regulators. Para [0052] and Fig. 4 teaches switching mechanism can include a two input CMOS multiplexer that is controlled by a signal from a register file. Applicant's disclosure only provides limited citing of the "control mechanism" in Fig. 4 where register value or, signals are used to select between regulators and output signals. No other "switching mechanism" or “control mechanism” are described (for example it can be). Thus, it is unknown what other "switching mechanism" or “control mechanism” would be included. In other words, the claims have unlimited scope on this term leading to confusion, or zone of uncertainty, that would inhibit the public from knowing what constitutes infringement.
All dependent claims inclusive of claims 1-7 are rejected under this category.
No art rejection is provided for these claims.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
9. Claims 8-13, 15-17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YUH et al. (US 2022/0028453 A1).
Regarding independent claim 8, YUH teaches a memory system with voltage drop compensation (Fig. 1A: 100 “memory circuit” uses method of adjusting voltage drop due temperature or process. See Fig. 1A-Fig. 7, especially Fig. 2 for illustrated components and functionality), comprising:
a memory cell (Fig. 2: 111 “resistance-based memory”);
a source follower (Fig. 2: 202) having a source terminal (Fig. 2: BN3, see para [0070]) communicatively coupled (communicatively coupled interpreted as operably coupled for circuitry function) to the memory cell (see Fig. 1B: 150 and Fig. 2: 111);
a voltage source (Fig. 2: Vref generator, see para [0040]);
an operational amplifier (Fig. 2: 143, para [0040]) having a non-inverting input (Fig. 2: NIT input of 143, para [0040]) communicatively coupled to the voltage source (Fig. 2: Vref generator);
a replica source follower (Fig. 2: 120R which is located in replica circuit 145A) having a gate terminal (Fig. 2: gate of 120R) communicatively coupled to an output of the operational amplifier (Fig. 2: coupled to VG via BN2) and
a source terminal (Fig. 2: FBN) communicatively coupled to an inverting input of the operational amplifier (Fig. 2: IT input of 143) via a feedback loop (see Fig. 2 and para [0053]: “feedback node”); and
control circuitry (Fig. 2: 120 control gate) coupled between the source follower (Fig. 2: 202) and the memory cell (Fig. 2: 111).
Regarding claim 9, YUH teaches the memory system of claim 8, further comprising replica control circuitry (Fig. 2: 206) coupled between the source terminal of the replica source follower (Fig. 2: 120R vdd) and the feedback loop (Fig. 2: IT terminal as feedback input).
Regarding claim 10, YUH teaches the memory system of claim 9, wherein the replica control circuitry (Fig. 2: 206) is substantially identical to the control circuitry (Fig. 2: 120) coupled between the source follower and the memory cell (see Fig. 2 transistor construction).
Regarding claim 11, YUH teaches the memory system of claim 8, further comprising a current source (Fig. 2: 204) coupled to the feedback loop (Fig. 2 in context of para [0050], para [0060]).
Regarding claim 12, YUH teaches the memory system of claim 8, wherein drain terminals of the replica source follower (Fig. 2: drain of 120R) and the source follower (Fig. 2: drain of 202) are communicatively coupled to a fixed voltage source (Fig. 2: VDD, see para [0053], para [0069]).
Regarding claim 13, YUH teaches the memory system of claim 8, wherein the output of the operational amplifier (Fig. 2: VG) is further communicatively coupled to a gate terminal of the source follower (Fig. 2: 202).
Regarding independent claim 15, YUH teaches a method for compensating voltage drops in a memory device (method of read operation of Fig. 1A: 100 “memory circuit” by adjusting voltage drop due temperature or process. See Fig. 1A-Fig. 7, especially Fig. 3 for illustrated components and functionality), comprising:
sampling voltage drops (Fig. 3: drop in VGB is sensed, measured, monitored) across one or more circuit elements (Fig. 3 in context of para [0065]: see “voltage drop” during t2-t3);
adjusting a target voltage (Fig. 2, para [0059]: voltage level of drive voltage VD) based on the sampled voltage drops (Fig. 3: drop in VGB) to obtain an adjusted target voltage (Fig. 2, Fig. 3 in context of para [0059]; adjusted voltage level of drive voltage VD. See also para [0065]);
determining whether voltage drop compensation is enabled (Fig. 2, para [0059]: based on replica current, VRBL to Vref difference, VG level it is determined that compensation is enabled in the circuit); and
supplying either the adjusted target voltage or a non-adjusted voltage to a memory cell based on the determination (Fig. 2, Fig. 3 in context of para [0059]: supplying adjusted voltage level of drive voltage VD. See also para [0065]).
Regarding claim 16, YUH teaches the method of claim 15, wherein sampling voltage drops across one or more circuit elements (Fig. 2: 11 memory) comprises sampling a voltage drop of a replica source follower by hardwiring (Fig. 2: see feed-back wiring) a source terminal of the replica source follower (Fig. 2: FBN terminal of 120R) to an inverting input of an operational amplifier (Fig. 2: IT of 143. See also para [0039], para [0040], para [0053]).
Regarding claim 17, YUH teaches the method of claim 15, wherein adjusting the target voltage based on the sampled voltage drops comprises increasing an output voltage of an operational amplifier (Fig. 2: 206 amplifier gain is used in the process).
Regarding claim 20, YUH teaches the method of claim 15, further comprising monitoring the voltage supplied to the memory cell using a monitor circuit (Fig. 2: 145A replica circuit is used for monitor and control).
Allowable Subject Matter
Claims 14, 18, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims listed, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations describe in the following:
14. The memory system of claim 8, wherein the memory cell comprises a NAND Flash memory cell.
18. The method of claim 15, wherein sampling voltage drops across one or more circuit elements comprises sampling a voltage drop of a replica source follower and one or more replica control circuit elements.
19. The method of claim 15, wherein determining whether voltage drop compensation is enabled comprises receiving a control signal from a register.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure: US 12057178 B2 claims 1-18 are applicable for NSDP double patenting rejection and this area will be visited in future. OH (US 7894236 B2): Fig. 1-Fig. 5 applicable for all claims. HAM (US 2018/0108407 A1) is applicable for all claims. HAM teaches a circuit (Fig. 2 circuitry. See Fig. 1-Fig. 8 for illustrated components and functionality) comprising: a first voltage regulator (Fig. 2: bottom regulator), the first voltage regulator generating a first voltage (Fig. 2: WL voltage); a second voltage regulator (Fig. 2: top regulator), the second voltage regulator generating a second voltage (Fig. 2: BL voltage coupled to VOUT from regulator), the second voltage comprising an adjusted voltage determining by sampling one or more voltage drops across one or more circuit elements (Fig. 2, Fig. 3A, para [0053]: “compensate” for voltage drop. See also para [0044], para [0045]); and a switching mechanism, the switching mechanism capable of programmatically selecting between supplying the first voltage and the second voltage to a memory cell (para [0037], para [0038], Fig. 2: selection switches used as required for programming. See also para [0032]-para [0042]). Fifield et al. (US 20140003164 A1) is applicable for all claims. Fifield teaches circuit comprising a third voltage regulator and a fourth voltage regulator, the third voltage regulator generating a third voltage output, and the fourth voltage regulator generating a fourth adjusted voltage (para [0008], para [0029]-para [0030], Fig. 3), wherein the third voltage regulator and the fourth voltage regulator are coupled to a negative side of the memory cell. (para [0008], para [0029]-para [0030], Fig. 3).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached on (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825