DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-15 are objected to because of the following informalities:
Claim 1 recites limitations “an inner element region surrounded by the output region and insulated and isolated from the output region with a first element different from the output elements being arranged in the inner element region;” which should be replaced with
“an inner element region surrounded by the output region and insulated and isolated from the output region, with a first element different from the output elements being arranged in the inner element region;” to improve claim language.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0335622 to Hiyoshi in view of Miyata (US Patent No. 8,431,998).
With respect to claim 1, Hiyoshi discloses a semiconductor device (e.g., insulated-gate transistor (MOSFET) including an active region and a temperature sense region spaced from the active region and isolated with the isolation trench) (Hiyoshi, Figs. 2, 6-7, 9-10, ¶0004, ¶0032-¶0092, ¶0098-¶0106) comprising:
a semiconductor chip (MOSFET 100) having a main surface (1) (Hiyoshi, Figs. 6-7, 9-10, ¶0032-¶0033, ¶0078, ¶0098-¶0100);
an output region (e.g., active region 10 of the MOSFET providing output current to be estimated to control operation of the MOSFET) (Hiyoshi, Figs. 6-7, 9-10, ¶0078, ¶0090-¶0092, ¶0098-¶0100) formed over the main surface (1) with output elements (e.g., MOSFET cells including gate trenches 19) (Hiyoshi, Figs. 6-7, ¶0034, ¶0042, ¶0078) being arranged in the output region (10);
an inner element region (e.g., sense region 20 including a temperature sensor) (Hiyoshi, Figs. 2, 6-7, 9-10, ¶0043-¶0044, ¶0047, ¶0079-¶0081, ¶0098-¶0104) surrounded by the output region (10) and insulated and isolated from the output region (10) with a first element (e.g., the temperature sensor of the sense region 20 in Fig. 6-7 or current sensor in Figs. 9-10 is isolated with the isolation region 30 including isolation trench 39) (Hiyoshi, Figs. 6-7,9-10, ¶0047, ¶0079-¶0080, ¶0098-¶0104) different from the output elements (e.g., MOSFET cells including gate trenches 19) being arranged in the inner element region (e.g., the sense region 20);
a first wiring layer (e.g., a first electrode layer on the first interlayer insulating film 71 and including the source electrode 45/44) (Hiyoshi, Figs. 6-7, 9-10, ¶0032, ¶0042, ¶0087, ¶0098-¶0104) formed over the main surface (1) so as to cover the output region (10) and including a first output wiring (e.g., the source wire 44) electrically connected to the output elements (e.g., the source regions 14 of the MOSFET cells); and
a connection wiring (e.g., a connection wire 103/94 and 104/97) (Hiyoshi, Figs. 6-7, 9-10, ¶0086-¶0087, ¶0098-¶0104) insulated and isolated from the first output wirings (44), the connection wiring (103/104) extending across the output region (10) from the inner element region (e.g., the sense region 20 surrounded by the isolation trench 39) to an outer region (e.g., pad region including pads 101/102) outside the output region (10),
wherein the output elements (e.g., MOSFET cells including gate trenches 19) (Hiyoshi, Figs. 6-7, 9-10, ¶0038-¶0041, ¶0098-¶0104) include a trench electrode structure (42).
Further, Hiyoshi does not specifically disclose a second wiring layer formed over the first wiring layer and including second output wirings electrically connected to the first output wiring and a connection wiring insulated and isolated from the second output wirings, wherein the output elements are arranged below the connection wiring and include a trench electrode structure overlapping with the connection wiring in a thickness direction of the semiconductor chip.
However, Miyata teaches forming MOSFET device (Miyata, Figs. 1B, 2A-2B, 3, Col. 1, lines 12-17; lines 25-28; Col. 6, lines 26-67; Cols 7-13) capable of reducing a region where no transistor cells are provided, and to reduce resistance in an electrode portion, the MOSFET device comprises two-layer electrode structure including a second wiring layer (e.g., a second electrode layer 27/28 including a second source electrode layer 27) (Miyata, Figs. 2A-2B, 3, Col. 7, lines 37-44; Col. 10, lines 22-27) formed over the first wiring layer (e.g., a first electrode layer 17/18 including a first source electrode layer 17) and including second output wirings (e.g., the second source electrode layer 27 and the second gate layer 28) electrically connected to the first output wiring (e.g., the first source electrode layer 17) (Miyata, Figs. 2A-2B, 3, Col. 6, lines 60-67; Col. 7, lines 1-5; lines 22-27) and a connection wiring (e.g., wiring portion 28w) (Miyata, Figs. 1B, 3, Col. 7, lines 61-63; Col. 8, lines 10-12; Col. 10, lines 7- 17; Col. 11, lines 49-27; Col. 13, lines 27-32) insulated and isolated from the second output wirings (e.g., the second source electrode layer 27), wherein the output elements (e.g., MOSFET cells are arranged below the wiring portion 28w) are arranged below the connection wiring (28w) and include a trench electrode structure (7/13) overlapping with the connection wiring (28w) in a thickness direction of the semiconductor chip.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Hiyoshi by forming a two-layer electrode structure as taught by Miyata to have the semiconductor device comprising: a second wiring layer formed over the first wiring layer and including second output wirings electrically connected to the first output wiring and a connection wiring insulated and isolated from the second output wirings, wherein the output elements are arranged below the connection wiring and include a trench electrode structure overlapping with the connection wiring in a thickness direction of the semiconductor chip, in order to provide MOSFET device capable of reducing a region where no transistor cells are provided, and to reduce resistance in an electrode portion (Miyata, Col. 1, lines 12-17; lines 25-28; Col. 7, lines 37-44; Col. 13, lines 27-32).
Regarding claim 2, Hiyoshi in view of Miyata discloses the semiconductor device of Claim 1. Further, Hiyoshi discloses the semiconductor device, wherein the connection wiring (e.g., a connection wire 103/94 and 104/97) (Hiyoshi, Figs. 6-7, 9-10, ¶0086-¶0087, ¶0098-¶0104) is sandwiched between the first output wirings (e.g., the source wiring 44) in a second direction (e.g., a horizontal direction in Fig. 7 or Fig. 10) intersecting a first direction (e.g., a vertical direction in Fig. 7 or Fig. 10) in which the trench electrode structure (19/42) extends, but does not specifically disclose that the connection wiring is sandwiched between the second output wirings.
However, Miyata teaches forming the MOSFET device comprising two-layer electrode structure including the second output wiring (e.g., the second source electrode layer 27) (Miyata, Figs. 2A-2B, 3, Col. 7, lines 37-44; Col. 10, lines 22-27) and the connection wiring (28w) (Miyata, Figs. 1B, 3) in the second electrode layer, wherein the connection wiring (28w) is sandwiched between the second output wirings (27), to provide MOSFET device with reduced resistance in an electrode portion (Miyata, Col. 1, lines 12-17; lines 25-28; Col. 7, lines 37-44; Col. 13, lines 27-32).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Hiyoshi/Miyata by forming the two-layer electrode structure including the second source layer and the connection wiring in the second electrode layer as taught by Miyata to have the semiconductor device, wherein the connection wiring is sandwiched between the second output wirings, in order to provide MOSFET device with reduced resistance in an electrode portion (Miyata, Col.1, lines 12-17;lines 25-28; Col.7, lines 37-44; Col.13, lines 27-32).
Regarding claim 3, Hiyoshi in view of Miyata discloses the semiconductor device of Claim 1. Further, Hiyoshi does not specifically disclose the semiconductor device, wherein the first output wiring included in the first wiring layer overlaps with the connection wiring in the thickness direction of the semiconductor chip.
However, Miyata teaches forming the MOSFET device, wherein the first output wiring (e.g., the first source electrode layer 17) (Miyata, Fig. 3, Col. 6, lines 60-67; Col. 7, lines 1-5; lines 22-27) included in the first wiring layer overlaps with the connection wiring (28w) in the thickness direction of the semiconductor chip, to provide MOSFET device capable of reducing a region where no transistor cells are provided, and to reduce resistance in an electrode portion (Miyata, Col. 1, lines 12-17; lines 25-28; Col. 7, lines 37-44; Col. 13, lines 27-32).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Hiyoshi/Miyata by forming the two-layer electrode structure as taught by Miyata to have the semiconductor device, wherein the first output wiring included in the first wiring layer overlaps with the connection wiring in the thickness direction of the semiconductor chip, in order to provide MOSFET device capable of reducing a region where no transistor cells are provided, and to reduce resistance in an electrode portion (Miyata, Col.1, lines 12-17;lines 25-28; Col.7, lines 37-44; Col.13, lines 27-32).
Regarding claim 4, Hiyoshi in view of Miyata discloses the semiconductor device of Claim 1. Further, Hiyoshi discloses the semiconductor device, wherein the output elements (e.g., MOSFET cells including gate trenches 19) (Hiyoshi, Figs. 6-7, ¶0034, ¶0042, ¶0078) include output transistors formed on the main surface (1), wherein the semiconductor device further comprises an interlayer insulating layer (71) configured to cover the main surface (1), wherein the first wiring layer (e.g., a first electrode layer on the first interlayer insulating film 71 and including the source electrode 45/44) (Hiyoshi, Figs. 6-7, ¶0032, ¶0042, ¶0087) is formed in the interlayer insulating layer (71), and wherein the first output wiring (44) includes a source wiring connected to the output transistors (e.g., the source regions 14 of the MOSFTE cells), but does not specifically disclose that the second wiring layer is formed in the interlayer insulating layer, and wherein each of the first output wiring and the second output wirings includes a source wiring connected to the output transistors.
However, Miyata teaches forming the MOSFET device, wherein the second wiring layer (27) is formed in the interlayer insulating layer (16/23/25) (Miyata, Fig. 3, Col. 9, lines 37-51; Col. 10, lines 7-40), and wherein each of the first output wiring (17) and the second output wirings (27) includes a source wiring connected to the output transistors (e.g., the source regions 15 of the MOSFTE cells), to provide MOSFET device capable of reducing a region where no transistor cells are provided, and to reduce resistance in an electrode portion (Miyata, Col. 1, lines 12-17; lines 25-28; Col. 7, lines 37-44; Col. 13, lines 27-32).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Hiyoshi/Miyata by forming the two-layer electrode structure as taught by Miyata to have the semiconductor device, wherein the second wiring layer is formed in the interlayer insulating layer, and wherein each of the first output wiring and the second output wirings includes a source wiring connected to the output transistors, in order to provide MOSFET device capable of reducing a region where no transistor cells are provided, and to reduce resistance in an electrode portion (Miyata, Col.1, lines 12-17; lines 25-28; Col. 7, lines 37-44; Col. 13, lines 27-32).
Regarding claim 5, Hiyoshi in view of Miyata discloses the semiconductor device of Claim 1. Further, Hiyoshi discloses the semiconductor device, wherein the trench electrode structure (e.g., gate trenches 19) (Hiyoshi, Figs. 2, 6-7, ¶0038-¶0042, ¶0047, ¶0086-¶0088) is arranged in a region of the output region (10) sandwiched between the outer region (e.g., pad region including pads 101/102) and the inner element region (e.g., the sense region 20 surrounded by the isolation trench 39) in a first direction (e.g., a vertical direction in Fig. 7) in which the trench electrode structure extends such that the trench electrode structure (19) is arranged over an entire region (e.g., the active region 10 including gate trenches 19 has an annular shape surrounding the sense region 20, thus an entire region of the active region 10 between the pad region and the sense region has trench gate electrode structure), in a second direction (e.g., a horizontal direction in Fig. 7) intersecting the first direction, of the region of the output region (e.g., the active region 10 including gate trenches 19 has an annular shape) sandwiched between the outer region and the inner element region in the first direction.
Regarding claim 6, Hiyoshi in view of Miyata discloses the semiconductor device of Claim 5. Further, Hiyoshi discloses the semiconductor device, wherein the output region (e.g., the active region 10 including gate trenches 19 has an annular shape) (Hiyoshi, Figs. 2, 6-7, ¶0047, ¶0086-¶0088)is formed in an annular shape surrounding the inner element region (the sense region 20), and wherein the output elements (MOSFET cells) are arranged in an annular shape surrounding the inner element region.
Regarding claim 7, Hiyoshi in view of Miyata discloses the semiconductor device of Claim 1. Further, Hiyoshi discloses the semiconductor device, further comprising an annular isolation structure (e.g., isolation region 30 has an annular shape) (Hiyoshi, Figs. 2, 6-7, ¶0047) configured to surround the inner element region (20) and insulate and isolate the inner element region (20) from the output region (10).
Regarding claim 8, Hiyoshi in view of Miyata discloses the semiconductor device of Claim 7. Further, Hiyoshi discloses the semiconductor device, wherein the isolation structure (e.g., isolation trench 39) (Hiyoshi, Figs. 2, 6-7, ¶0043-¶0047) includes an isolation electrode (62) buried in an isolation trench (39) with an isolation insulator (61) interposed between the isolation electrode (62) and the isolation trench (39).
Regarding claim 9, Hiyoshi in view of Miyata discloses the semiconductor device of Claim 1. Further, Hiyoshi discloses the semiconductor device, wherein the connection wiring (e.g., a connection wire 103/94 and 104/97) (Hiyoshi, Figs. 6-7, ¶0086-¶0087) includes a plurality of connection wirings, and wherein at least one (103/94) of the plurality of connection wirings has a width (e/g/. a width of the wire 94) different from widths of the other connection wirings (104/970.
Regarding claim 10, Hiyoshi in view of Miyata discloses the semiconductor device of Claim 1. Further, Hiyoshi discloses the semiconductor device, wherein the first element (e.g., the sense region 20 including a temperature sensor element) (Hiyoshi, Figs. 2, 6-7, ¶0079-¶0081) includes a temperature sensor element configured to detect a temperature of the output region (10).
Regarding claim 12, Hiyoshi in view of Miyata discloses the semiconductor device of Claim 1. Further, Hiyoshi discloses the semiconductor device, wherein a second element (e.g., a current sensor element 84) different from the first element (e.g., the temperature sensor element 85) is further arranged in the inner element region (20) (Hiyoshi, Figs. 9-10, ¶0038-¶0041, ¶0098-¶0104).
Regarding claim 13, Hiyoshi in view of Miyata discloses the semiconductor device of Claim 12. Further, Hiyoshi discloses the semiconductor device, wherein the second element (e.g., the current sensor element 84) (Hiyoshi, Figs. 9-10, ¶0098-¶0104) includes a current monitor element configured to detect an output current generated by the output elements (e.g., MOSFEFT cells).
Regarding claim 14, Hiyoshi in view of Miyata discloses the semiconductor device of Claim 1. Further, Hiyoshi discloses the semiconductor device, wherein the first element (e.g., the current sensor element 84) (Hiyoshi, Figs. 9-10, ¶0098-¶0104) includes a current monitor element configured to detect an output current generated by the output elements.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0335622 to Hiyoshi in view of Miyata (US Patent No. 8,431,998) as applied to claim 10, and further in view of Oda (US 2020/0168714).
Regarding claim 11, Hiyoshi in view of Miyata discloses the semiconductor device of Claim 10. Further, Hiyoshi does not specifically disclose the semiconductor device, wherein the temperature sensor element includes a temperature sensing diode and a diode wiring configured to connect the temperature sensing diode and the connection wiring, and wherein the diode wiring is included in the first wiring layer.
However, Hiyoshi teaches a temperature sensor wiring (94/97) (Hiyoshi, Figs. 6-7, 9-10, ¶0086-¶0087, ¶0098-¶0104) configured to connect the temperature sensing element (85) and the connection wiring (103/104), and wherein the temperature sensor wiring (94/97) is included in the first wiring layer (e.g., a first electrode layer including a source wiring 44).
Further, Oda teaches forming a MOSFET element (Oda, Fig. 1, ¶0004, ¶0056, ¶0068-¶0072) and a temperature sensing element (18) including a diode formed on the first main surface of the semiconductor device and comprising a diode wiring (24b), wherein the diode wiring (24b) is included in the first wiring layer as the source wiring (23b), to provide a semiconductor device with suppressed degradation of the accuracy of detection with a diode element (Oda, Fig. 1, ¶0004, ¶0056, ¶0068-¶0072).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Hiyoshi/Miyata by forming a temperature sensing element including a diode as taught by Oda, wherein the source electrode wiring and the diode wiring are included in the first electrode layer to have the semiconductor device, wherein the temperature sensor element includes a temperature sensing diode and a diode wiring configured to connect the temperature sensing diode and the connection wiring, and wherein the diode wiring is included in the first wiring layer, in order to provide a semiconductor device with suppressed degradation of the accuracy of detection with a diode element (Oda, ¶0004, ¶0056, ¶0068-¶0072).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0335622 to Hiyoshi in view of Miyata (US Patent No. 8,431,998) as applied to claim 1, and further in view of Fukuda et al. (US 2020/0312975, hereinafter Fukuda).
Regarding claim 15, Hiyoshi in view of Miyata discloses the semiconductor device of Claim 1. Further, Hiyoshi does not specifically disclose the semiconductor device, wherein the outer region includes a control region configured to generate a control signal.
However, Fukuda teaches forming a semiconductor device (e.g., a switching device) (Fukuda, Fig. 1, ¶0002, ¶0076-¶0083) comprising an output region (e.g., an output region 6 including a power MISFET transistor) and an outer region (e.g., input region including a control circuit region to generate a gate control signal which drives and controls the power MISFET) (Fukuda, Fig. 1, ¶0082), wherein the outer region includes a control region configured to generate a control signal, to provide intelligent power device.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Hiyoshi/Miyata by forming an integrated control circuit in an outer region as taught by Fukuda to have the semiconductor device, wherein the outer region includes a control region configured to generate a control signal, in order to provide an intelligent power device (Fukuda, ¶0002, ¶0082).
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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