DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fukui et al. (US 2015/0333126).
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(Claim 1) Fukui et al. teach a semiconductor device comprising:
a semiconductor layer structure comprising a drift region (4) that comprises a wide band-gap semiconductor material (SiC) that has a first conductivity type (N, paragraph 37),
a well region (5) that has a second conductivity type (P, paragraph 37), and
a source region (6) that has the first conductivity type (N, paragraph 37); and
a gate structure (9/10) in a gate trench (7) in the semiconductor layer structure, the gate structure (9) surrounding the well region (75) in plan view (fig. 17).
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(Claim 2) Fukui et al. teach wherein in plan view the well region (5) comprises two sidewalls that are connected to each other to form an oblique angle.
(Claim 3) Fukui et al. teach wherein the oblique angle is in a range of from about 100 degrees to about 140 degrees in plan view (120 degrees, sum of interior angles of a hexagon is 720 degrees).
(Claim 4) Fukui et al. teach wherein the well region (5) and/or the source region has a hexagonal shape, a circular shape or an octagonal shape in plan view.
(Claim 5) Fukui et al. teach wherein the well region (5) is one of a plurality of spaced-apart well regions, and wherein the gate trench (7) comprises a continuous gate trench that at least partially surrounds each of the well regions (5).
Claims 11 – 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aichinger et al. (US 2018/0114856).
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(Claim 11) Aichinger et al. teach a semiconductor device comprising:
a semiconductor layer structure that comprises a drift region (121) that comprises a wide band-gap semiconductor material (paragraph 38) that has a first conductivity type (N, paragraph 54),
a common deep shielding region (116a, #pn3, paragraph 74) that has a second conductivity type (paragraph 45), and
a plurality of spaced-apart well regions (115) that have the second conductivity type (paragraph 44); and
a gate trench (155) in the semiconductor layer structure,
wherein a portion of the gate trench surrounds the common deep shielding region (116, fig. 4A) in plan view.
(Claim 12) Aichinger et al. teach wherein a sub-set of the spaced-apart well regions 115) surround the portion of the gate trench (155) that surrounds the common deep shielding region (116a) in plan view.
(Claim 13) Aichinger et al. teach wherein the semiconductor layer structure further comprises a deep shielding region (116b) that has the second conductivity type, the deep shielding region underneath the gate trench.
(Claim 14) Aichinger et al. teach wherein the common deep shielding region (fig. 4C #116a) electrically connects the deep shielding region (116b) to a source contact (110) that is on an upper surface of the semiconductor layer structure (paragraph 43).
(Claim 15) Aichinger et al. teach wherein the common deep shielding region (116a) extends to an upper surface of the semiconductor layer structure.
(Claim 16) Aichinger et al. teach wherein each well region in the sub-set of the spaced-apart well regions has a hexagonal shape, a circular shape or an octagonal shape in plan view (paragraphs 82, 83).
(Claim 17) Aichinger et al. teach wherein the common deep shielding region has a hexagonal shape or a rectangular shape in plan view (paragraphs 82, 83).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Fukui et al. (US 2015/0333126) in view of Aichinger et al. (US 2016/0190301).
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(Claim 10) Fukui et al. lack wherein the gate structure comprises a first side surface facing the well region and a second side surface opposite the first side surface,
the semiconductor layer structure further comprises a deep shielding region that is beneath the gate structure, has the second conductivity type, and
has a higher concentration of second conductivity type dopants than that of the well region, and
the deep shielding region continuously extends from a lower surface of the gate structure onto an uppermost portion of the second side surface of the gate structure.
However, Aichinger et al. teach wherein the gate structure (155) comprises a first side surface facing the well region (115) and a second side surface opposite the first side surface,
the semiconductor layer structure further comprises a deep shielding region (116) that is beneath the gate structure, has the second conductivity type, and
has a higher concentration of second conductivity type dopants than that of the well region, and
the deep shielding region (116) continuously extends from a lower surface of the gate structure (155) onto an uppermost portion of the second side surface of the gate structure for the benefit of forming a diode region (paragraph 74).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of forming a diode region.
Allowable Subject Matter
Claims 6 – 9 and 18 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 21 – 23 are allowable, because prior art does not render obvious:
(Claim 21) a plurality of spaced-apart deep shielding connection patterns that have the second conductivity type;
wherein the deep shielding connection patterns extend through the gate structure and are spaced around the well region in plan view.
Conclusion
Prior art made of record and not relied upon, considered pertinent to applicant's disclosure are listed in PTO – 892 Form.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IGWE U ANYA whose telephone number is (571)272-1887. The examiner can normally be reached 8:00 AM - 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272- 1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/IGWE U ANYA/Primary Examiner, Art Unit 2891
August 21, 2026
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