DETAILED ACTION
This non-final action is responsive to the following communications: application filed on 08/02/2024.
Claims 1-16 are pending. Claims 1 and 9 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
4. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
5. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 08/02/2024. This IDS has been considered.
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
8. Claims 1, 3, 6-9, 11, and 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 10,978,118 B1).
Regarding independent claim 1, Yu teaches a memory signal calibration apparatus (Fig. 5: 100 “DDR SDRAM signal calibration device”. See also Fig. 1-Fig. 9 for illustrated components and functionality), comprising:
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an enablement signal setting circuit (Fig. 5: 110 “enablement signal setting circuit”) configured to generate a setting control signal (Fig. 5: DQS_EN_Setting);
a gating circuit (Fig. 5: 130: “signal gating circuit”) configured to generate a data strobe enablement setting signal (Fig. 5: DQS_EN_SET) having a single pulse (see e.g., Fig. 8a, Fig. 8c: single pulse of DQS_EN_SET signal shown within operation cycle) according to the setting control signal (Fig. 5: DQS_EN_Setting as input to 130),
to begin to generate and maintain an enablement state of a data strobe enablement signal (Fig. 5: DQS_EN signal. See Fig. 8a, Fig. 8c) for a predetermined time period (Fig. 8a, Fig. 8c: duration of DQS_EN signal “duration of the DQS_EN signal”) according to the single pulse (Fig. 8a, Fig. 8c: single pulse of DQS_EN_SET signal. Col. 6, lines 54-54), and
to perform gating on a data strobe signal (See Fig. 5: see output DQS_gated. See col. 3, lines 16-23) having a receiving timing according to the enablement state to generate a gated data strobe signal (Fig. 8a, Fig. 8c in context of col. 3, lines 16-35: "...signal gating circuit 130 generates the DQS enablement setting signal according to the DQS enablement setting, then determines the timing of the DQS enablement signal changing from a low level to a high level according to the DQS enablement setting signal, and then performs an logical AND operation to the DQS enablement signal and the DQS signal in order to output the gated DQS signal..."); and
a calibration circuit (Fig. 5: 140, 210, 120 combined. See “calibration circuit” and “ZQ calibration circuit”. See also Fig. 6) configured to:
generate a pulse indicating signal (Fig. 8a, Fig. 8c: DQS_Tristate_High signal. See Fig. 5) having an indicating state (Fig. 8a, Fig. 8c: DQS tristate signal pulled to high state) corresponding to a clock pulse section of the data strobe signal (Fig. 8a, Fig. 8c: clock section of DQS signal);
delay (Fig. 8a, Fig. 8c: shown delay between tristate pulled up state and DQS_EN_SET pulse) the data strobe enablement setting signal (Fig. 8c: DQS_EN_SET) to generate a first delay signal (Fig. 6, Fig. 8c: DQS_EN_SET pulse, timing input to 620);
delay the first delay signal (Fig. 6: delay DQS_EN_SET using 630 “delay circuit”) to generate a second delay signal (Fig. 6, Fig. 8c: delayed DQS_EN_SET pulse, timing input to 640);
sample (“sample” using Fig. 6: 620, 640 d-type flip-flop) the pulse indicating signal (Fig. 8a, Fig. 8c: DQS_Tristate_High signal) according to the first delay signal (Fig. 6, Fig. 8c: DQS_EN_SET pulse, timing input to 620) and the second delay signal (Fig. 6, Fig. 8c: delayed DQS_EN_SET pulse, timing input to 640) to generate a sampling result (Fig. 6: DQS_Early, DQS_Late); and
control the enablement signal setting circuit (Fig. 5: 110) to adjust the setting control signal (Fig. 5: DQS_EN_Setting) according to the sampling result (see Fig. 5: DQS_Early, DQS_Late calibration feedback to 110. See col. 2, lines 6-12) so as to control the gating circuit (Fig. 5: 130) to adjust timings of the data strobe enablement setting signal (Fig. 5, Fig. 8c: timing of DQS_EN_SET) and the data strobe enablement signal (Fig. 5, Fig. 8c: timing of DQS_EN).
Regarding claim 3, Yu teaches the memory signal calibration apparatus of claim 1, wherein the calibration circuit (Fig. 5: 140, 210, 120 combined) comprises:
a pulse indicating signal generation circuit (Fig. 5: 210, 120 combined) to receive the data strobe signal (Fig. 5: DQS) to generate the pulse indicating signal (Fig. 5: DQS_Tristate_high);
a first sampling flip-flop (Fig. 6: 620) configured to receive the pulse indicating signal (Fig. 6: DQS_Tristate_high) and the first delay signal (Fig. 6, Fig. 8c: DQS_EN_SET pulse and timing) to perform sampling to generate a first sampled state comprised by the sampling result (Fig. 6: DQS_Early); and
a second sampling flip-flop (Fig. 6: 640) configured to receive the pulse indicating signal (Fig. 6: DQS_Tristate_high) and the second delay signal (Fig. 6, Fig. 8c: delayed DQS_EN_SET pulse and timing) to perform sampling to generate a second sampled state comprised by the sampling result (Fig. 6: DQS_Late).
Regarding claim 6, Yu teaches the memory signal calibration apparatus of claim 1, wherein the first delay signal and the second delay signal respectively have a first delay pulse and a second delay pulse (Fig. 8c: delayed DQS_EN_SET pulse and timing, delayed DQS_EN_SET pulse and timing), and the first delay signal and the second delay signal respectively sample the pulse indicating signal according to the first delay pulse and the second delay pulse (Fig. 6 in context of col. 4, lines 40-57).
Regarding claim 7, Yu teaches the memory signal calibration apparatus of claim 1, wherein the memory signal calibration apparatus is disposed in a memory access interface apparatus in a memory system that accesses a memory apparatus according to the control of a memory access controller (in context of col. 1, lines 8-67: suggested controller to memory device communication signals teaches that the signal calibration device is located in memory controller interface in memory system and thus the limitation is satified).
Regarding claim 8, Yu teaches the memory signal calibration apparatus of claim 1, wherein the gating circuit adjusts the timing of the data strobe enablement signal (See Fig. 8a: DQS_EN signal timing) to perform gating corresponding to a preamble section and the clock pulse section of the data strobe signal (See Fig. 8a: DQS_gated timing) generate the gated data strobe signal (See Fig. 8a).
Regarding independent claim 9, which is drafted as in method format, substantially identical to the functionality recited in claim 1, and is therefore rejected for the same reasons as claim 1. Yu teaches a memory signal calibration method used in a memory signal calibration apparatus, comprising:
generating a setting control signal by an enablement signal setting circuit;
generating a data strobe enablement setting signal having a single pulse according to the setting control signal by a gating circuit, to begin to generate and maintain an enablement state of a data strobe enablement signal for a predetermined time period according to the single pulse, and to perform gating on a data strobe signal having a receiving timing according to the enablement state to generate a gated data strobe signal;
generating a pulse indicating signal having an indicating state corresponding to a clock pulse section of the data strobe signal by a calibration circuit;
delaying the data strobe enablement setting signal to generate a first delay signal by the calibration circuit;
delaying the first delay signal to generate a second delay signal by the calibration circuit;
sampling the pulse indicating signal according to the first delay signal and the second delay signal to generate a sampling result by the calibration circuit; and
controlling the enablement signal setting circuit to adjust the setting control signal according to the sampling result by the calibration circuit so as to control the gating circuit to adjust timings of the data strobe enablement setting signal and the data strobe enablement signal.
(This claim is drafted as in method format, substantially identical to the functionality recited in claim 1, and is therefore rejected for the same reasons as claim 1).
Regarding claim 11, which is drafted as in method format, substantially identical to the functionality recited in claim 3, and is therefore rejected for the same reasons as claim 3. Yu teaches the memory signal calibration method of claim 9, further comprising: receiving the data strobe signal by a pulse indicating signal generation circuit of the calibration circuit to generate the pulse indicating signal; receiving the pulse indicating signal and the first delay signal to perform sampling by a first sampling flip-flop of the calibration circuit to generate a first sampled state comprised by the sampling result; and receiving the pulse indicating signal and the second delay signal to perform sampling by a second sampling flip-flop of the calibration circuit to generate a second sampled state comprised by the sampling result.
(This claim is drafted as in method format, substantially identical to the functionality recited in claim 3, and is therefore rejected for the same reasons as claim 3).
Regarding claim 14, which is drafted as in method format, substantially identical to the functionality recited in claim 6, and is therefore rejected for the same reasons as claim 6. Yu teaches the memory signal calibration method of claim 9, wherein the first delay signal and the second delay signal respectively have a first delay pulse and a second delay pulse, and the first delay signal and the second delay signal respectively sample the pulse indicating signal according to the first delay pulse and the second delay pulse.
(This claim is drafted as in method format, substantially identical to the functionality recited in claim 6, and is therefore rejected for the same reasons as claim 6).
Regarding claim 15, which is drafted as in method format, substantially identical to the functionality recited in claim 7, and is therefore rejected for the same reasons as claim 7. Yue teaches the memory signal calibration method of claim 9, wherein the memory signal calibration apparatus is disposed in a memory access interface apparatus in a memory system that accesses a memory apparatus according to the control of a memory access controller.
(This claim is drafted as in method format, substantially identical to the functionality recited in claim 7, and is therefore rejected for the same reasons as claim 7).
Regarding claim 16, which is drafted as in method format, substantially identical to the functionality recited in claim 8, and is therefore rejected for the same reasons as claim 8. Yu teaches the memory signal calibration method of claim 9, further comprising: adjusting the timing of the data strobe enablement signal by the gating circuit to perform gating corresponding to a preamble section and the clock pulse section of the data strobe signal to generate the gated data strobe signal.
(This claim is drafted as in method format, substantially identical to the functionality recited in claim 8, and is therefore rejected for the same reasons as claim 8).
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
Fender et al. (US 8,929,162 B1): Fender teaches a device (Fig. 2A: 200 “tracking and gating circuitry”. See Fig. 1-Fig. 6 for illustrated circuitry and functionality) comprising: an enablement signal setting circuit (Fig. 2A) configured to generate data strobe (DQS) enablement setting (Fig. 2A: 213 DQS ENABLE input); a signal gating circuit (Fig. 2A: All circuitry except Cal and S) coupled to the enablement signal setting circuit (Fig. 2A), the signal gating circuit (Fig. 2A) configured to generate a DQS enablement setting signal (Fig. 2A: En1) and a DQS enablement signal (Fig. 2A: En2) according to the DQS enablement setting (Fig. 2A: 213), and the signal gating circuit (Fig. 2A) further configured to output a gated DQS signal (Fig. 2A: 216 “GATED DQS”. See Fig. 3: 216 and column 1, lines 55-62, col. 5, lines 10-12) according to the DQS enablement signal (Fig. 2A: En2) and a DQS signal (Fig. 2A: 211 DQS); and a calibration circuit (Fig. 2A: Cal. See col. 7, line 51: “leveling process”) coupled to the enablement signal setting circuit (Fig. 2A) and the signal gating circuit (Fig. 2A) , the calibration circuit (Fig. 2A) configured to generate a first delay signal (Fig. 2A: delay introduced in signal 214, see col. 6, lines 16-22: output of programmable delay 240) according to the DQS enablement setting signal (Fig. 2A: En1) and then generate a second delay signal (Fig. 2A: output of D2) according to the first delay signal (Fig. 2A: delay introduced in signal 214 which is input to D2), the calibration circuit further configured to output a calibration signal (e.g. Fig. 2A: “late2”. See col. 6, lines 6-22: see 254 circuit output used for delay adjustment of 240) according to the first delay signal (Fig. 2A: delay introduced in signal 214 which is input to 254), the second delay signal (Fig. 2A: output of D2 which is input to 254), and the DQS signal (Fig. 2A: DQS which is input to 254), wherein the enablement signal setting circuit (Fig. 2A: S) maintains or adjusts the DQS enablement setting (Fig. 3: 213. See Fig. 2A: 213) according to the calibration signal (Fig. 2A and Fig. 3: according to 214 which uses delay introduced by e.g. late2).
Fung (US 2016/0260465 A1): Fig. 2-Fig. 16 disclosure applicable for all claims. Fung teaches concepts relate generally to information or data transfer techniques and circuitry. More specifically, the disclosed concepts provide techniques and circuitry for successfully gating strobe signals in relatively tight or narrow timing windows before the signals enter the tri-state condition (e.g., during post-amble), and un-gating the strobe before the signal is needed (e.g., during pre-amble). Apparatus and methods according to the disclosed concepts facilitate the proper gating of non-free-running strobes to eliminate glitches when the strobe signals enter tri-state. The proper gating of strobe signals in turn facilitates proper operation of modern interface circuits that rely on strobe signals for source-synchronous capture.
It is suggested that applicant consider all prior arts made of record.
Allowable Subject Matter
Claims 2, 4-5, 10, and 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims listed, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims.
Claim 2. “… the sampling result indicates that different sampling states are generated according to the sampling of the first delay signal and the second delay signal such that the enablement signal setting circuit determines that the receiving timing of the data strobe signal corresponds to an aligned state and controls the gating circuit to not move the timings of the data strobe enablement setting signal and the data strobe enablement signal by using the setting control signal….”
Claims 4-5. “…a second non-inverted delay flip-flop configured to receive the first delay signal and the clock signal to generate a second non-inverted delay result delayed for a cycle relative to the first delay signal delay; a second inverted delay flip-flop configured to receive the first delay signal and the inverted clock signal to generate a second inverted delay result delayed for a half cycle relative to the first delay signal delay; and a second multiplexer configured to select one of the second non-inverted delay result and the second inverted delay result to be the second delay signal…”
Claim 10. “… sampling result indicates that different sampling states are generated according to the sampling of the first delay signal and the second delay signal such that the enablement signal setting circuit determines that the receiving timing of the data strobe signal corresponds to an aligned state and controls the gating circuit to not move the timings of the data strobe enablement setting signal and the data strobe enablement signal by using the setting control signal…”
Claims 12-13. “…receiving the first delay signal and the inverted clock signal by a second inverted delay flip-flop of the second delay circuit of the calibration circuit to generate a second inverted delay result delayed for a half cycle relative to the first delay signal delay; and selecting one of the second non-inverted delay result and the second inverted delay result to be the second delay signal by a second multiplexer of the second delay circuit of the calibration circuit…”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached on (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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