CTNF 18/793,154 CTNF 81308 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of Species I in the reply filed on 05/29/2026 is acknowledged. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1, 3-5, 8-12, are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Hwang (US Pub. 2004/0179418) . Regarding claim 1 , Fig. 8 of Hwang discloses a method comprising: receiving a read command [READ, Fig. 7] and an address [paragraph 0021] associated with the read command, wherein the address is associated with a first physical address space [first address for bank BANK-1 (UPPER DQ)] or a second physical address space in a memory array [second address for BANK-1 (LOWER DQ), since BANK-1 LOWER is different BANK-1 UPPER, they each has different access address]; activating a word line of the array based at least in part of the address [paragraph 0021] providing data via the activated word line[data on DL1U] at interface connections in a first time after [when BANK-1 UPPER is accessed during reading] receiving the read command [READ] if the address is associated with the first physical address space [address for BANK-1 UPPER], or in a second time [a second time when BANK-1 LOWER is accessed for reading] which is shorter than the first time if the address is associated with the second physical address space [since data line of DL1U is shorter than DL2U, access time (time to transfer data from the memory bank to the data interface is shorter)]. Regarding claims 3 and 10 , Fig. 8 of Hwang discloses wherein activating the word line happens an activation time after receiving the read command and the address [READ, Fig. 7, paragraph 0021], wherein the first physical address space includes digit lines of a first length [longer DL2U line] and the second physical address space includes digit lines of a second length [DL1U, shorter] shorter than the first length, and wherein the activation time for word lines of the first physical address space is longer than the activation time of word lines of the second physical address space. Regarding claims 4 and 11 , Fig. 8 of Hwang discloses wherein providing the data happens a read time after activating the word line [paragraph 0021], wherein the first physical address space is within a first distance [address for BANK-1 UPPER] of the interface connections and the second physical address space is within a second distance [address for BANK-1 LOWER] of the interface connections which is shorter than the first distance, and wherein the read time of the first physical address space is longer than the read time of the second physical address space [since data line for first address is longer, it take longer to transfer data]. Regarding claims 5 and 12 , Fig. 1 of Hwang discloses reading the data from the activated word line with a voltage threshold compensating (VTC) sense amplifier [VSA] when the address is associated with the first physical address space and reading the data from the activated word line with a non-VTC sense amplifier [CSA] when the address is in the second physical address space. Regarding claim 8 , Fig. 8 of Hwang discloses system comprising: a memory device configured to provide data at an interface connection responsive to receiving a read command [READ, Fig. 7] and an address [as discloses in paragraph 0021], wherein the memory device comprises a first performance region [BANK-1 UPPER] and a second performance region [BANK-1 LOWER], and wherein the memory is configured to provide the data at a first time after receiving the read command when the address is associated with the first performance region [during reading operation of bank BANK-1 UPPER] or a second time after receiving the read command when the address is associated with the second performance region [during reading operation for bank BANK-1 LOWER]; and a controller [since reading operation is controlled, a controller is inherent] configured to: identify, based on the address, whether the read command is for the first performance region or the second performance region [paragraph 0021, controller determines which bank will perform reading operation according to address]; provide the read command and the address to the memory device [paragraph 0021]; and receive the data via the interface connection at the first time after receiving the read command when the address is associated with the first performance region [when reading operation for bank BANK-1 UPPER] or the second time after [when reading operation for bank BANK-1 UPPER] receiving the read command when the address is associated with the first performance region or the second time after receiving the read command when the address is associated with the second performance region [as discloses in paragraph 0021, controller to select BANK-1 UPPER or BANK-1 LOWER for reading operation depending on the address]. Regarding claim 9 , Fig. 7 of Hwang discloses wherein the first time is represented by a first number of clock cycles [CLK], and the second time is represented by a second number of clock cycles [can be the same CLK], and wherein the controller is configured to retrieve the data via the interface connection after the first number of clock cycles when the address is associated with the first performance region [when BANK-1 UPPER is accessed] or the second number of clock cycles when the address is associated with the second performance region [when BANK-1 LOWER is accessed] . 07-15 AIA Claim s 1, 6-7, and 13-15 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Richter et al. (US Pub. 2011/0205828) . Regarding claim 1 , Fig. 1 of Richter discloses a method comprising: receiving a read command [as discloses in paragraph 0012, controller 34 controls read operation. Therefore, a read command is inherent] and an address [paragraph 0012] associated with the read command, wherein the address is associated with a first physical address space [address for bank 38 and 40, Fig. 3] or a second physical address space in a memory array [address for bank 42 and 44, Fig. 3, since bank 38 is different from bank 42, they each has different access address]; activating a word line of the array based at least in part of the address [paragraphs 0021 and 0022] providing data via the activated word line[data on BL] at interface connections in a first time after [as disclose in paragraph 0022, bank 38 and 40 are slower] receiving the read command [read command from controller 34] if the address is associated with the first physical address space [address for bank 38 or 40]], or in a second time [a second time when bank 42 or 44 is accessed for reading] which is shorter than the first time if the address is associated with the second physical address space [as discloses in paragraph 0022, bank 42 and 44 are faster (less latency), they take shorter time to access]. Regarding claims 6, 7, 13, 14, and 15 , Fig. 1 of Richter discloses storing, in a storage area [54], performance information associated with addresses in the first physical address space and addresses associated with the second physical address space; and providing the performance information to a controller responsive to a command [paragraph 0026], wherein the storage area comprises a mode register [REG] and the command comprises a mode register read command [paragraph 0026]. Regarding claim 8 , Fig. 1 of Richter discloses system comprising: a memory device configured to provide data at an interface connection responsive to receiving a read command and an address [as discloses in paragraph 0012, controller 34 control reading operation corresponding to addresses], wherein the memory device comprises a first performance region [bank 38 and 40] and a second performance region [bank 42 and 44], and wherein the memory is configured to provide the data at a first time after receiving the read command when the address is associated with the first performance region [during reading operation of bank 38 or bank 40] or a second time after receiving the read command when the address is associated with the second performance region [during reading operation for bank 42 or 44]; and a controller [34] configured to: identify, based on the address, whether the read command is for the first performance region or the second performance region [paragraph 0012, controller 34determines which bank will perform reading operation]; provide the read command and the address to the memory device [paragraph 0012]; and receive the data via the interface connection at the first time after receiving the read command when the address is associated with the first performance region [when reading operation for bank 38 or 40] or the second time after [when reading operation for bank 42 or 44] receiving the read command when the address is associated with the first performance region or the second time after receiving the read command when the address is associated with the second performance region [as discloses in paragraph 0022, bank 42 and 44 is faster, less latency. Therefore, it takes shorter time to access] . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 2, the prior art does not teach or suggest either alone or in combination wherein the first time is represented by a first number of clock cycles, and the second time is represented by a second number of clock cycles, which is less than the first number of clock cycles . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANTHAN TRAN/Primary Examiner, Art Unit 2825 Application/Control Number: 18/793,154 Page 2 Art Unit: 2825 Application/Control Number: 18/793,154 Page 3 Art Unit: 2825 Application/Control Number: 18/793,154 Page 4 Art Unit: 2825 Application/Control Number: 18/793,154 Page 5 Art Unit: 2825 Application/Control Number: 18/793,154 Page 6 Art Unit: 2825 Application/Control Number: 18/793,154 Page 7 Art Unit: 2825 Application/Control Number: 18/793,154 Page 8 Art Unit: 2825 Application/Control Number: 18/793,154 Page 9 Art Unit: 2825
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