DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed on March 19, 2024. It is noted, however, that applicant has not filed a certified copy of application KR10-2024-0337688 as required by 37 CFR 1.55.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on August 2, 2024 has been considered by the examiner.
Election/Restrictions
Claims 12-19 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on August 5, 2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 6,982,902 B2 to Dietmar Gogl, et al. (hereafter Gogl) in view of US 10,522,462 B2 to Jhon Jhy Liaw (hereafter Liaw).
Regarding Amendment Claim 1, Gogl discloses a resistive memory device, comprising:
a data cell array comprising a plurality of memory cells (A data cell array: Gogl, col.4:26-27),
each column of the plurality of memory cells having an electrically separated first bit line and a second bit line (Each column of memory cells connected to at least two separated bit lines, including a global bit line and a local bit line: Gogl, col.4:29-33 and Gogl, Figure 2A);
a row decoder configured to decode a row address and
select one or more word lines of the plurality of memory cells in response to the row address (Selecting a memory cell by bit line and word line being known in the industry: Gogl, col.2:11-13); and
a column decoder configured to decode a column address (Selecting a memory cell by bit line and word line being known in the industry: Gogl, col.2:11-13) and
select one of the first bit line and the second bit line in response to the row address
decoded by the row decoder and the column address (Disclosing a segmented bitline, that is a series of local bit lines, wherein groups of cells are connected to the individual local bit lines. Decoding an address necessarily requires identifying both the proper word line, row address, and the correct local bit line segment, as determined by the row address: Gogl, Figure 4A).
Gogl fails to teach a MRAM memory array wherein the first bit line comprises a first metal layer and the second bit line comprise the first metal layer and a second metal layer. Liaw, however, discloses a MRAM memory array, wherein:
wherein the first bit line comprises a first metal layer (Disclosing the first bit line deposed on a first metal layer: Liaw, col.8:34-35), and
the second bit line comprises the first metal layer and a second metal layer (The second bit line deposed on a second metal layer: Liaw, col.8:35-36; The second bit line layer connected through to the first layer by vias: Liaw, Figure 14A)
Liaw teaches the use of multiple metal layers for the bitlines reduces the resistance when addressing the memory cells, allowing for less bit line IR drop during operations (Liaw, col.5:55-62). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the low resistance bit line separation of Liaw with the dual bit line construction of Gogl, with a reasonable expectation of success. Both inventions are well known in the field of MRAM array architecture and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 2, Gogl discloses the resistive memory device of claim 1, wherein the data cell array comprises:
a first data cell array comprising one or more memory cells from the plurality of memory cells connected to the first bit line (First bit cell array, 232-K-1 through 232K+2, coupled to bit line 402S: Gogl, Figure 4A); and
a second data cell array comprising one or more memory cells from the plurality of memory cells connected to the second bit line (Second bit cell array, 232-K+3 through 232K+6, coupled to bit line 402S+1: Gogl, Figure 4A).
Regarding Claim 3, Liaw and Gogl discloses the resistive memory device of claim 2, wherein
a first distance between the first data cell array and the column decoder is less than a second distance between the second data cell array and the column decoder (Liaw discloses the bit line extending in the direction of the column decoders: Liaw, col.4:48-53; With the segmented bit line configuration of Gogl, this would necessarily result in one data cell array being farther from the column decoder than the other: Gogl, Figure 4A).
Regarding Claim 4, Gogl discloses the resistive memory device of claim 3, wherein
the second bit line comprises the second metal layer in an area of the first data cell array (The global bit line comprising the area above each data cell array, including the first: Gogl, col.4:58-59).
Regarding Claim 5, Gogl discloses the resistive memory device of claim 4, wherein
the second bit line comprises a via connecting the first metal layer and the second metal layer (Vias being a common method of connecting electrically separated metal layers: Liaw, col.2:53-57)
in an area of the second data cell array (The global bit line comprising the area above each data cell array, including the second: Gogl, col.4:58-59).
Regarding Claim 6, Gogl discloses the resistive memory device of claim 2, wherein
at least one of the first metal layer and the second metal layer is located on top of a magnetic tunnel junction element (The first metal layer, comprising the local bit line, located on top of a magnetic tunnel junction element: Gogl, Figure 4A).
Regarding Claim 7, Gogl discloses the resistive memory device of claim 6, wherein
the second metal layer is located on top of the first metal layer (The second metal layer deposited on top of the first metal layer: Gogl, Figure 4A).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 6,982,902 B2 to Dietmar Gogl, et al. (hereafter Gogl) and US 10,522,462 B2 to Jhon Jhy Liaw (hereafter Liaw) in view of US 2019/0206928 A1 to Pinghui Li, et al. (hereafter Li).
Regarding Claim 8, Gogl discloses the resistive memory device of claim 2, but fails to disclose the further limitations of Claim 8. Li, however, discloses a MRAM memory array, wherein
a dummy cell is between the first data cell array and the second data cell array to separate an array area (A known solution to producing a uniform magnetic environment in connection with MRAM devices includes placing dummy magnetic cells at the perimeter of the memory array: Li, ¶[0002]).
Li teaches placing dummy magnetic cells at the perimeter of the memory array helps produce a uniform magnetic environment in a MRAM memory array (Li, ¶[0002]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the dummy cells of Li with the segmented bit line architecture of Gogl, with a reasonable expectation of success. Both inventions are well known in the field of MRAM architecture and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 9-11 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 6,982,902 B2 to Dietmar Gogl, et al. (hereafter Gogl) and US 10,522,462 B2 to Jhon Jhy Liaw (hereafter Liaw) in view of US 2006/0077737 A1 to Tsukasa Ooishi (hereafter Ooishi).
Regarding Claim 9, Gogl discloses the resistive memory device of claim 1, but fails to disclose the further limitations of Claim 9. Ooishi, however, discloses a resistive memory device as in Claim 1, further comprising:
a reference cell array sharing a word line with the data cell array (Showing reference cells RMCmx and RMCmn sharing a word line [here vertical] with the data cell array: Ooishi, Figure 15),
wherein the reference cell array comprises
a reference bit line connecting a lower metal layer of a magnetic tunnel junction and an upper metal layer of the magnetic tunnel junction (The reference cells having the same configuration as the memory cells: Ooishi, ¶[0120]).
Ooishi teaches the use of reference memory cells allows for more reliable reading of memory cells by providing a reference value for comparison (Ooishi, ¶[0138]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the reference values of Ooishi with the segmented bitline architecture of Gogl, with a reasonable expectation of success. Both inventions are well known in the field of MRAM architecture and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 10, Ooishi discloses the resistive memory device of claim 9, wherein the reference bit line comprises:
a first metal line located above the magnetic tunnel junction in the reference cell array (A metal line located above the magnetic tunnel junction: Ooishi, Figure 15);
a second metal line located below the magnetic tunnel junction (A second metal line located below the magnetic tunnel junction: Ooishi, Figure 15);
a first connection structure
comprising at least one via and a first metal layer connected through the first metal line and the second metal line (Vias being a common method of connecting electrically separated metal layers: Liaw, col.2:53-57); and
a second connection structure
comprising at least one via and a second metal layer connected through the first metal line and the second metal line (Vias being a common method of connecting electrically separated metal layers: Liaw, col.2:53-57).
Regarding Claim 11, Ooishi discloses the resistive memory device of claim 10, wherein
the first connection structure is at a first edge of the reference cell array (Showing a joint structure at the wordlines connected to the first end of the reference array: Ooishi, Figure 15), and
the second connection structure is at a second edge of the reference cell array (Showing a second joint structure at the second end of the wordlines connected to the reference array: Ooishi, Figure 15).
Regarding Independent Claim 20, Gogl discloses a resistive memory device, comprising:
a first data cell array connected to a first word line group and a first bit line group (A first data cell array: Gogl, Figure 2A);
a second data cell array connected to a second word line group and a second bit line group (A second data cell array connected to a separate segmented bit line and word lines: Gogl, Figure 2A),
the second data cell array sharing a column with the first data cell array (Each column of memory cells connected to at least two separated bit lines, including a global bit line and a local bit line: Gogl, col.4:29-33 and Gogl, Figure 2A);
a row decoder configured to decode a row address and
select a word line of the first word line group and the second word line group in response to the row address (Selecting a memory cell by bit line and word line being known in the industry: Gogl, col.2:11-13); and
a column decoder configured to decode a column address and select a bit line from one of the first bit line group and the second bit line group in response to the row address and the column address (Disclosing a segmented bitline, that is a series of local bit lines, wherein groups of cells are connected to the individual local bit lines. Decoding an address necessarily requires identifying both the proper word line, row address, and the correct local bit line segment, as determined by the row address: Gogl, Figure 4A),
wherein the column decoder selects the first bit line group based on the row address corresponding to the first word line group, and selects the second bit line group based on the row address corresponding to the second word line group (Disclosing a segmented bitline, that is a series of local bit lines, wherein groups of cells are connected to the individual local bit lines. Decoding an address necessarily requires identifying both the proper word line, row address, and the correct local bit line segment, as determined by the row address: Gogl, Figure 4A).
Gogl fails to teach a memory array including a reference cell array connected to the first word line group and the second word line group. Ooishi, however, discloses a memory cell array, wherein:
a reference cell array connected to the first word line group and the second word line group (Showing reference cells RMCmx and RMCmn sharing a word line [here vertical] with the data cell array: Ooishi, Figure 15).
Ooishi teaches the use of reference memory cells allows for more reliable reading of memory cells by providing a reference value for comparison (Ooishi, ¶[0138]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the reference values of Ooishi with the segmented bitline architecture of Gogl, with a reasonable expectation of success. Both inventions are well known in the field of MRAM architecture and the combination of known inventions with predictable results is obvious and not patentable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2021/0193204 A1 to Akhilesh Jaiswal: Teaching a MRAM array with separated reference cells on the word lines.
US 9,741,434 B2 to Akira Katayama, et al.: Teaching a bi-layer bit line MRAM array with reference memory cells.
US 12,665,008 B2 to Wen-Liang Huang, et al.: Teaching a paired, bi-level bit line arrangement for a MRAM array.
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/CHRISTOPHER LANE REECE/ Examiner, Art Unit 2824
/PHO M LUU/ Primary Examiner, Art Unit 2824
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