DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made to a claim of domestic priority to US patent application 15/097,033 filed on March 16th, 2016, which has been issued as US patent US9837350B2 on December 5th, 2017.
Information Disclosure Statement
The information disclosure statements (IDS) filed on August 8th, 2024, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 23 and 42 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 12 of U.S. Patent No. US9837350B2 (Briggs et al.) in view of Rhodes (US20050074966A1) for the following reasons:
Regarding claims 23 and 42;
Claim 12 of Briggs et al. recites A method for forming a semiconductor interconnect structure comprising (e.g. Instant application claim 23 line 1 “A method for forming a semiconductor interconnect comprising:”): forming a first conductive layer in a recess of a dielectric layer (e.g. Instant application claim 23 lines 3-4 “providing a metal line in the trench comprising a first conductive material, wherein the metal line is elongated in a first direction parallel to the substrate,”); forming a second conductive layer disposed on the first conductive layer (e.g. Instant application claim 23 lines 7-8 “adding a second conductive material to the metal line by depositing the second conductive material in the recess substantially along the length of the metal line,”); and forming a wetting layer…between the first conductive layer and the dielectric; wherein the wetting layer comprises cobalt (e.g. Instant application claim 42 “The method, further comprising: forming a first layer between the substrate and the metal line, wherein the first layer comprises cobalt.”). The method further comprising: performing a chemical-mechanical planarization process before forming the second conductive layer on the first conductive layer, wherein: the chemical-mechanical planarization process is configured to overpolish to form a recess (e.g. Instant application claim 23 lines 5-6 “removing a portion of the first conductive material to form a recess extending along the length of the metal line,”).
Claim 12 of Briggs et al. is silent to forming a trench in a substrate, as claimed.
However, Rhodes teaches a semiconductor device including an interconnect structure and a method of making said interconnect structure including a trench formation process (e.g. Fig. 5 ref 215, 218, 221; Detailed description [0018] “ trenches 215, 218, 221 are etched into the insulating layer…”) to provide electrical connection points to bond pads in the substrate (e.g. Detailed description [0022] “Trenches or depressions 215, 218, 221 are etched in insulating layer 209 and when filled with a conductive material are capable of functioning as electrical interconnects, signal carrying conductors, conductive structures, or connective structures coupling together integrated circuit elements, such as resistors, capacitors, and transistors, or coupling integrated circuit elements to bonding pads. These electrical interconnects are also suitable for use in connection with the fabrication of memory circuits or cells, logic circuits or cells, and analog circuits or cells.”).
At the effective time of filing, it would have been obvious to someone having ordinary skill in the art to further include a trench formation process to provide the semiconductor substrate which contains the interconnect structure formed by the method claimed in Briggs et al. with an internal connection point similar to the semiconductor interconnect device taught in Rhodes since doing so would result in an interconnect structure with an internal connector for coupling integrated elements to bond pads with a reasonable expectation of success. (e.g. See MPEP 2143(I)(C)).
Claim 12 of Briggs et al. is further silent to forming a via to the metal line, wherein the via extends in a second direction perpendicular to the substrate, and wherein the second conductive material of the metal line comprises a direct interface with a conductive material of the via that constitutes the majority of the conductive material of the via, as claimed.
However, Rhodes teaches a semiconductor device including an interconnect structure including a via (e.g. Fig. 5 ref 403) which couples the interconnect structure to an external connection point (e.g. Detailed description [0037] “Gold conductor 403 is wire-bonded to bonding material 400 to couple the bonding pad formed in trench 221 to an external connector”).
At the effective time of filing, it would have been obvious to someone having ordinary skill in the art to further include a via formation process to further provide the semiconductor interconnect structure formed by the method claimed in Briggs et al. with an external connection point similar to the semiconductor interconnect device taught in Rhodes since doing so would result in an interconnect structure with an external connector for sending signals to or from other external device/structures with a reasonable expectation of success. (e.g. See MPEP 2143(I)(C))
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 23-26, 28-29, and 31 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Bonilla et al. (US20090127711A1) for the following reasons:
Regarding claim 23;
Bonilla et al. teaches a method for forming a semiconductor interconnect comprising: forming a trench in a substrate (e.g. Fig. 8 ref 8, Detailed description [0030] “ …a trench 8 is formed in the dielectric layer 12.”), providing a metal line in the trench comprising a first conductive material (e.g. Fig. 8 ref 16, Detailed description [0031] “A copper layer 16 is then formed over the entire structure...”), wherein the metal line is elongated in a first direction parallel to the substrate, removing a portion of the first conductive material to form a recess extending along the length of the metal line (e.g. fig. 9-10 ref 18, Detailed description [0032]-[0033] “the copper 16 is etched to form a recess 18 within the trench. The etching may be a conventional wet etch process to form the recess 18.”), adding a second conductive material to the metal line by depositing the second conductive material in the recess substantially along the length of the metal line (e.g. Fig. 11-12 ref 32-34, Detailed description [0035] “A copper seed layer 34 is formed over the barrier metal layer 32…a copper layer also shown as reference numeral 34 is formed over the copper seed layer…”), forming a via to the metal line, wherein the via extends in a second direction perpendicular to the substrate, and wherein the second conductive material of the metal line comprises a direct interface with a conductive material of the via that constitutes the majority of the conductive material of the via (e.g. Detailed description [0040] “A via is formed within the dielectric layer 26, penetrating through the upper copper layer 34 a, the cap 24, the metal layer 32 and the lower copper layer 16.”).
Regarding claim 24;
Bonilla et al. teaches that for forming a semiconductor interconnect further comprises: forming a barrier layer between the first and second conductive materials (e.g. Fig. 11 ref 32, Detailed description [0034] “a metal layer 32 … is formed in the recess 18 and over the dielectric layer 12.”).
Regarding claims 25 and 26;
Bonilla et al. further teaches that the barrier layer comprises tantalum, or tantalum nitride respectively (e.g. Detailed description [0034] “a metal layer 32 such as, for example, tantalum or Tantalum nitride …”).
Regarding claim 28-29, and 31;
Bonilla et al. further teaches that the first and second conductive materials comprise copper (e.g. Detailed description [0037] “upper copper layer 34 a and the lower copper layer 16…”, the claim limitations of 28-29 and 31 are all substantively encompassed by the limitation of 29 and as such the direct recitation of the exact claim language of claims 28 and 31 is being omitted without loss of propriety for brevity purposes).
Claims 23, 30, 32-33, and 40 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Nomura et al. (US20090020883A1) for the following reasons:
Regarding claim 23;
Nomura et al. teaches a method for forming a semiconductor interconnect comprising: forming a trench in a substrate (e.g. Fig. 2B ref 150, Detailed description [0026] “the contact hole formation process (S104), an opening 150 to be a contact hole structure for connecting to the device portion in lithography and dry etching processes is formed inside the SiO2 film 210.”), providing a metal line in the trench comprising a first conductive material (e.g. Fig. 3A ref 260, Detailed description [0030] “the Al plug film formation process (S110), an Al film 260 to be a first-stage contact plug is caused to deposit (form) inside the opening 150 and on the surface of the substrate 200 where the Ti film 212 and the TiN film 216 are formed”), wherein the metal line is elongated in a first direction parallel to the substrate, removing a portion of the first conductive material to form a recess extending along the length of the metal line (e.g. Fig. 3B ref 152, Detailed description [0031] “the recess formation process (S112), an upper part of the Al film 260 filled up in the opening 150 is etched to form a recess 152.”), adding a second conductive material to the metal line by depositing the second conductive material in the recess substantially along the length of the metal line (e.g. Fig.3C ref 262, Detailed description [0032] “he refractory metal plug film formation process (S114), a refractory metal material film is caused to deposit inside the recess 152 formed by etching the upper part of the Al film 260.”), forming a via to the metal line (e.g. Fig. 4C+9A-9C ref 154, Detailed description [0037] “the trench formation process (S122), an opening 154, which is a trench structure for making a damascene wire in the lithography and dry etching processes is formed inside the SiOC film 222 and the dielectric film 220. The opening 154 is formed on the contact plug in the two-stage structure of the Al film 260 and the refractory metal film 262.”), wherein the via extends in a second direction perpendicular to the substrate, and wherein the second conductive material of the metal line comprises a direct interface with a conductive material of the via that constitutes the majority of the conductive material of the via (e.g. Detailed description [0050] “…the refractory metal film 262 will directly be in contact with the Cu film 264.”).
Regarding claim 30;
Nomura et al. further teaches that the first and second conductive materials are different (e.g. Detailed description [0030]-[0032] “an Al film 260…[and] at least one of tungsten (W), tungsten nitride (WN), Ti, TiN, tantalum (Ta), tantalum nitride (TaN), and cobalt (Co) can be used as a material of the refractory metal film 262.”).
Regarding claim 32 and 33;
Nomura et al. further teaches that the second conductive material comprises cobalt, or tungsten respectively (e.g. Detailed description [0032] “at least one of tungsten (W), tungsten nitride (WN), Ti, TiN, tantalum (Ta), tantalum nitride (TaN), and cobalt (Co) can be used as a material of the refractory metal film 262.”).
Regarding claim 40;
Nomura et al. further teaches that the first conductive material comprises aluminum (e.g. Detailed description [0030] “an Al film 260…”)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 27 and 42 are rejected under 35 U.S.C. 103 as being unpatentable over Bonilla et al. (US20090127711A1) in view of Hintze et al. (US 20140273436 A1) for the following reasons:
Regarding claim 27;
Bonilla et al. is silent to the barrier layer comprises titanium nitride. as claimed.
However, Hintze et al. teaches an interconnect structure and method of making which includes a multilayered barrier structure (e.g. ref 108yAx, 110yAx, 1116yAx) which contemplates Titanium Nitride as a suitable material choice (e.g. Detailed description [0029]-[0030] “the barrier layer 116.sub.YA.sub.X may simply be a thicker version of one or more of the barrier layers 108.sub.YA.sub.X, 110.sub.YA.sub.X… the Group Y materials include tantalum (Ta), niobium (Nb), Tungsten (W), vanadium (V), hafnium (Hf), titanium (Ti), or zirconium (Zr), as well as nitrides, borides or phosphides made of such materials. The Group X materials referenced herein include titanium (Ti), cobalt (Co), ruthenium (Ru), manganese (Mn), aluminum (Al), nickel (Ni), chromium (Cr) and molybdenum (Mo), as well as nitrides, carbides, carbonitrides, borides or phosphides made of such materials.”) to be selected from during formation.
At the effective time of filing, it would have been obvious to one having ordinary skill in the art to form the barrier layer taught in Bonilla from Titanium Nitride as taught in Hintze et al., since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
Regarding claim 42;
Bonilla et al. further teaches forming a first layer between the substrate and the metal line (e.g. Fig.8 ref 14, Detailed description [0031] “A barrier metal layer 14 is formed over the dielectric layers 10, 12, including lined within the via 6 and trench 8.”).
Bonilla et al. is silent to the first layer comprising Cobalt as claimed.
However, Hintze et al. teaches an interconnect structure and method of making which includes a multilayered barrier structure (e.g. ref 108yAx, 110yAx, 1116yAx) which contemplates Cobalt as a suitable material choice (e.g. Detailed description [0029]-[0030] “the barrier layer 116.sub.YA.sub.X may simply be a thicker version of one or more of the barrier layers 108.sub.YA.sub.X, 110.sub.YA.sub.X… the Group Y materials include tantalum (Ta), niobium (Nb), Tungsten (W), vanadium (V), hafnium (Hf), titanium (Ti), or zirconium (Zr), as well as nitrides, borides or phosphides made of such materials. The Group X materials referenced herein include titanium (Ti), cobalt (Co), ruthenium (Ru), manganese (Mn), aluminum (Al), nickel (Ni), chromium (Cr) and molybdenum (Mo), as well as nitrides, carbides, carbonitrides, borides or phosphides made of such materials.” ) to be selected from during formation.
At the effective time of filing, it would have been obvious to one having ordinary skill in the art to form the first layer taught in Bonilla et al. from Cobalt as taught in Hintze et al., since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
Claims 23-41 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US20090289368A1) in view of Rhodes (US20050074966A1) for the following reasons:
Regarding claim 23;
Yang et al. teaches a method for forming a semiconductor interconnect comprising: forming a trench in a substrate (e.g. Fig. 4A ref 62A, 63A-B; Detailed description [0034] “a line opening 62A for a single damascene structure, and a via opening 63A and a line opening 63B for a dual damascene structure in the second dielectric material 54B….”, [0036]-[0037] “The patterned interconnect structure 50 shown in FIG. 4A is fabricated utilizing standard back-end-of-the-line (BEOL) processes that are well known in the art including a single damascene or dual damascene process. A first via then line opening process may be used, or a first line then via opening process may be used…The process typically includes deposition, lithography, etching and filling of an opening with a diffusion barrier and then a conductive material, and thereafter planarization. Inasmuch as the processing details for fabricating such an interconnect structure are well known to those skilled in the art, the details are omitted herein to avoid obscuring of the current invention.”), providing a metal line in the trench comprising a first conductive material (e.g. Fig 4B ref 64, Detailed description [0045] “The conductive material 64 may be formed…by fully filling the at least one opening…”), wherein the metal line is elongated in a first direction parallel to the substrate, removing a portion of the first conductive material to form a recess extending along the length of the metal line (e.g. Fig 4B ref 64, Detailed description [0045] “The conductive material 64 may be formed…by fully filling the at least one opening and then recessing the conductive material to a level below the upper surface of the second dielectric material 54B.”), and adding a second conductive material to the metal line by depositing the second conductive material in the recess substantially along the length of the metal line (e.g. Fig. 4D-4E ref 68, Detailed description [0050] “ additional conductive material 68 which may comprise the same or different, preferably the same, conductor as conductive material 64 is formed. Any conventional deposition process can be used in forming the structure shown in FIG. 4D…”, [0051] “planarizing the additional conductive material 68 such that an upper surface thereof is substantially co-planar to an upper surface of the second dielectric material 54B.”).
Yang et al. is silent to forming a via to the metal line, wherein the via extends in a second direction perpendicular to the substrate, and wherein the second conductive material of the metal line comprises a direct interface with a conductive material of the via that constitutes the majority of the conductive material of the via as claimed.
However, Rhodes teaches a semiconductor device including an interconnect structure including a via (e.g. Fig. 5 ref 403) which couples the interconnect structure to an external connection point (e.g. Detailed description [0037] “Gold conductor 403 is wire-bonded to bonding material 400 to couple the bonding pad formed in trench 221 to an external connector”).
At the effective time of filing, it would have been obvious to someone having ordinary skill in the art to further include a via formation process to further provide the semiconductor interconnect structure formed by the method taught in Yang et al. with an external connection point similar to the semiconductor interconnect device taught in Rhodes since doing so would result in an interconnect structure with an external connector for sending signals to or from other external device/structures with a reasonable expectation of success. (e.g. See MPEP 2143(I)(C))
Regarding claim 24;
Yang et al. further teaches that the method for forming a semiconductor interconnect further comprises: forming a barrier layer between the first and second conductive materials (e.g. Fig 4C ref 66, Detailed description [0047] “an EM preventing liner 66 is formed on all the exposed surfaces (including horizontal and vertical) of the structure shown in FIG. 4B. ”).
Regarding claims 25-27;
Yang et al. further teaches that the barrier layer comprises tantalum, tantalum nitride, or titanium nitride respectively(e.g. Detailed description [0047] “The EM preventing liner 66 comprises Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Ir, IrCu, Co(W,B,P,Mo,Re) or any like material that can prevent EM failure.”).
At the effective time of filing, it would have been obvious to one having ordinary skill in the art to form the barrier layer taught in Yang et al. from tantalum, tantalum nitride, or titanium nitride by selecting from the list of appropriate materials contemplated by Yang et al., since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
Regarding claims 28 and 29;
Yang et al. further teaches that the first and second conductive materials comprise copper. (e.g. Detailed description [0050] “additional conductive material 68 [may] comprise the same or different, preferably the same, conductor as conductive material 64”, [0045] “Preferably, the conductive material 64 is Cu, W or Al, with Cu or a Cu alloy”; the claim limitations of 28-29 are substantively encompassed by the limitation of 29 and as such the direct recitation of the exact claim language of claims 28 is being omitted without loss of propriety for brevity purposes).
Regarding claim 30;
Yang et al. further teaches that the first and second conductive materials are different (e.g. Detailed description [0050] “additional conductive material 68 [may] comprise the same or different, preferably the same, conductor as conductive material 64”).
Claims 31-41 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US20090289368A1) in view of Rhodes (US20050074966A1) further in view of King et al. (US20080150145A1) for the following reasons:
Regarding claims 31-41;
Yang et al. further teaches that the first and/or second conductive material comprises copper, tungsten, or aluminum respectively (e.g. Detailed description [0045] “the conductive material 64 is Cu, W or Al, with Cu or a Cu alloy”).
Yang et al. and Rhodes are silent to the first conductive material comprising cobalt, ruthenium or molybdenum as claimed.
However, King et al. teaches a semiconductor interconnect structure with a conductive layer material selected from copper, aluminum, tungsten, cobalt, ruthenium, and molybdenum (e.g. Fig. 2N ref 218, Detailed description [0059] “conductive layer 218 includes e.g., copper (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), titanium (Ti), aluminum (Al), hafnium (Hf), tantalum (Ta), tungsten (W), Vanadium (V), Molybdenum (Mo), palladium (Pd), gold (Au), silver (Au), platinum Pt, or any combination thereof.”)
At the effective time of filing, it would have been obvious to one having ordinary skill in the art to form the first conductive layer taught in Yang et al. from a conductive metal material such as copper, tungsten, aluminum, cobalt, molybdenum, or ruthenium respectively as taught in King et al. to provide a first conductive material in a semiconductor interconnect structure with a reasonable expectation of success since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
Conclusion
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/WILLIAM ROBERT MANN/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
