Prosecution Insights
Last updated: August 16, 2026
Application No. 18/793,304

LEAD FRAME, SEMICONDUCTOR DEVICE, AND LEAD FRAME MANUFACTURING METHOD

Non-Final OA §102§103
Filed
Aug 02, 2024
Priority
Aug 10, 2023 — JP 2023-131267
Examiner
SABUR, ALIA
Art Unit
Tech Center
Assignee
Shinko Electric Industries Co., Ltd.
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
443 granted / 596 resolved
+14.3% vs TC avg
Moderate +6% lift
Without
With
+6.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
49 currently pending
Career history
633
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
61.4%
+21.4% vs TC avg
§102
13.4%
-26.6% vs TC avg
§112
18.8%
-21.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 596 resolved cases

Office Action

§102 §103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 3-4, 8, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rogren (U.S. PGPub 2013/0037927). Regarding claim 1, Rogren teaches a lead frame (Figs. 11-23) comprising: a lead that includes an upper surface and a lower surface, the upper surface having a larger width than a width of the lower surface (145, Fig. 13, Fig. 22, [0094]), a connection portion that is arranged on the upper surface and serves as a connection portion for a semiconductor element (147, [0081], [0086]), a plating film that covers a surface of the lead (143, [0081]-[0082]). Regarding claim 3, Rogren teaches wherein, in the plating film, a film thickness of a portion that covers the upper surface is smaller than a film thickness of a portion that covers the lower surface (Fig. 22, plating film 143 is not present on upper surface). Regarding claim 4, Rogren teaches wherein the lead includes a side surface between the upper surface and the lower surface, and in the plating film, a film thickness of a portion that covers the side surface is smaller than a film thickness of a portion that covers one of the upper surface and the lower surface (Fig. 22, plating film 143 is not present on upper surface). Regarding claim 8, Rogren teaches wherein the lead has a tapered shape in which a width of the upper surface is larger than a width of the lower surface in a cross section perpendicular to a longitudinal direction of the lead (Figs. 20-25). Regarding claim 10, Rogren teaches a semiconductor device (Figs. 11-23), comprising: a semiconductor element that is mounted on the lead frame (Fig. 25, 160, [0095]) and sealing resin that seals the semiconductor element (170, [0095]), wherein the lead frame includes a lead that includes an upper surface and a lower surface, the upper surface having a larger width than a width of the lower surface (145, Fig. 13, Fig. 22, [0094]), a connection portion that is arranged on the upper surface and serves as a connection portion for the semiconductor element (147, [0081], [0086]), a plating film that covers a surface of the lead (143, [0081]-[0082]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-6 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Seki (U.S. PGPub 2004/0232534) in view of Rogren (U.S. PGPub 2013/0037927). Regarding claim 1, Seki teaches a lead frame (Fig. 9, 1, [0101]), comprising: a lead that includes an upper surface and a lower surface (Fig. 11, [0102]), a connection portion that is arranged on the upper surface and serves as a connection portion for a semiconductor element ([0101], silver-plated layer, see Fig. 5, 3, [0091]), and a plating film that covers a surface of the lead (one or more of 7a/7b/2a, [0103]). Seki does not explicitly teach the upper surface of the lead having a larger width than a width of the lower surface. Rogren teaches a lead frame comprising a lead includes an upper surface and a lower surface, the upper surface having a larger width than a width of the lower surface (145, Fig. 13, Fig. 22, [0094]). Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Rogren with Seki such that the upper surface of the lead has a larger width than a width of the lower surface for the purpose of providing secure attachment to the encapsulant (Rogren, [0019]). Regarding claim 2, the combination of Seki and Rogren teaches wherein, in the plating film, a film thickness of a portion that covers the lower surface is smaller than a film thickness of a portion that covers the upper surface (Seki, Fig. 11, [0103]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Seki with Rogren for the reasons set forth in the rejection of claim 1. Regarding claim 3, the combination of Seki and Rogren teaches wherein, in the plating film, a film thickness of a portion that covers the upper surface is smaller than a film thickness of a portion that covers the lower surface (Seki, [0103], layer 2b selectively formed on only one surface, which may be the lower surface. It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Seki with Rogren for the reasons set forth in the rejection of claim 1. Regarding claim 4, the combination of Seki and Rogren teaches wherein the lead includes a side surface between the upper surface and the lower surface (Seki, Fig. 9; Rogren, Fig. 22), and in the plating film, a film thickness of a portion that covers the side surface is smaller than a film thickness of a portion that covers one of the upper surface and the lower surface (Seki, [0096], plating layer may be formed on the side surfaces; [0095], layer 2b selectively formed on upper and/or lower surfaces; Rogren, [0085]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Seki with Rogren for the reasons set forth in the rejection of claim 1. Regarding claim 5, the combination of Seki and Rogren teaches wherein a surface of the plating film is a roughened surface, and surface roughness of the surface of the plating film is larger than surface roughness of the surface of the lead (Seki, 2b, [0095], [0102]-[0103], Fig. 11). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Seki with Rogren for the reasons set forth in the rejection of claim 1. Regarding claim 6, the combination of Seki and Rogren teaches wherein in the plating film, surface roughness of a portion that covers the upper surface is larger than surface roughness of a portion that covers the lower surface (Seki, 2b, [0095], [0102]-[0103], Fig. 11). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Seki with Rogren for the reasons set forth in the rejection of claim 1. Regarding claim 8, the combination of Seki and Rogren teaches wherein the lead has a tapered shape in which a width of the upper surface is larger than a width of the lower surface in a cross section perpendicular to a longitudinal direction of the lead (Rogren, Figs. 20-25). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Seki with Rogren for the reasons set forth in the rejection of claim 1. Regarding claim 9, the combination of Seki and Rogren teaches a die pad that includes a mounting surface for the semiconductor element, wherein the plating film covers a surface of the die pad (Seki, Fig. 5, [0091]; [0101]-[0103]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Seki with Rogren for the reasons set forth in the rejection of claim 1. Regarding claim 10, Seki teaches a semiconductor device comprising: a lead frame (Fig. 9, 1, [0101]), a semiconductor element that is mounted on the lead frame (Fig. 9, [0101]), and sealing resin that seals the semiconductor element (9, [0101]), wherein the lead frame includes a lead that includes an upper surface and a lower surface (Fig. 11, [0102]), a connection portion that is arranged on the upper surface and serves as a connection portion for a semiconductor element ([0101], silver-plated layer, see Fig. 5, 3, [0091]), and a plating film that covers a surface of the lead (one or more of 7a/7b/2a, [0103]). Seki does not explicitly teach the upper surface of the lead having a larger width than a width of the lower surface. Rogren teaches a lead frame comprising a lead includes an upper surface and a lower surface, the upper surface having a larger width than a width of the lower surface (145, Fig. 13, Fig. 22, [0094]). Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Rogren with Seki such that the upper surface of the lead has a larger width than a width of the lower surface for the purpose of providing secure attachment to the encapsulant (Rogren, [0019]). Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Seki (U.S. PGPub 2004/0232534) in view of Rogren (U.S. PGPub 2013/0037927) and Sonehara (U.S. PGPub 2019/0157196). Regarding claim 7, the combination of Seki and Rogren teaches wherein the connection portion is formed of a plating layer of a different material from the plating film (Seki, [0091]) but does not explicitly teach wherein the connection portion is arranged on the plating film that covers the upper surface. Sonehara teaches a lead frame comprising a lead and a plating film that covers a surface of the lead (Figs. 1A-1B, [0047]-[0049], 21, 22) a connection portion arranged on the upper surface of the lead and serves as a connection portion for a semiconductor element, wherein the connection portion is arranged on the plating film ([0050], 23, [0125], 213). Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Sonehara with Seki and Rogren such that the connection portion is arranged on the plating film that covers the upper surface because the prior art teaches every element, a person of ordinary skill could have combined them as claimed and in combination each element performs the same function as it does separately, and the combination would have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143(I)A. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALIA SABUR whose telephone number is (571)270-7219. The examiner can normally be reached M-F 9:30-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALIA SABUR/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Aug 02, 2024
Application Filed
Jul 30, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12701722
Semiconductor Device and Method for Forming the Same
4y 0m to grant Granted Aug 04, 2026
Patent 12702060
Package and Method for Forming the Same
4y 2m to grant Granted Aug 04, 2026
Patent 12696499
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
2y 10m to grant Granted Jul 28, 2026
Patent 12696657
DISPLAY PANEL AND PRODUCTION METHOD THEREOF
2y 10m to grant Granted Jul 28, 2026
Patent 12684833
SEMICONDUCTOR DEVICE
3y 11m to grant Granted Jul 14, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
81%
With Interview (+6.5%)
2y 3m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 596 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month