DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 23 and 25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 23 recites the limitation “a circuit component of a memory” in line 4. It is unclear whether this limitation is different from “a circuit component of a memory” in claim 20, line 3 because it is unclear whether “the circuit component of the memory” in claim 25, lines 2-3 relates back to “a circuit component of a memory” recited in claim 20, line 3 or claim 23, line 4.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4, 7-11 and 20-25 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5-8, 16-18 and 21 of U.S. Patent No. 12,068,021. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-4 and 7-11 would have been obvious over claims 1-3, 5-8 and 10 of the patent and claims 20-25 are anticipated by claims 16-18 and 21 of the patent.
Regarding claim 1, claim 1 and claim 8 of the patent recite an apparatus, comprising:
a synchronizer (claim 1, an internal clock circuit) configured to receive an enable signal, a first clock signal, and a signal (claim 1, a command) to enter a low power mode and to provide an output signal (claim 1, a second clock signal), wherein in response to the signal to enter the low power mode the synchronizer is configured to intermittently enable and disable the output signal based on the enable signal; and
a clock driver circuit (claim 8).
It would have been obvious to one having ordinary skill in the art to recognize that the apparatus of claim 1 of the instant application and that of the patent are identical in structure; therefore the limitation of “a clock driver circuit configured to receive the first clock signal and intermittently enable and disable a second clock signal based on the output signal.” is only a functional limitation.
Regarding claim 2, It would have been obvious to one having ordinary skill in the art to use an oscillator to provide the enable signal.
Regarding claim 3, claim 7 recites the apparatus of claim 1, wherein the synchronizer comprises a plurality of serially-coupled flip-flops configured to receive the enable signal at a first one of the plurality of serially-coupled flip-flops and to propagate the enable signal to an output of a last one of the serially-coupled flip-flops in response to the first clock signal.
Regarding claim 4, claim 7 of the patent recites the apparatus of claim 3, wherein the synchronizer further comprises a reset circuit configured to provide a reset signal to each flip-flop of the plurality of serially- coupled flip-flops.
It would have been obvious to one having ordinary skill in the art to recognize that the synchronizer comprises a reset circuit to provide a reset signal o each flip-flop of the plurality of flip-flops.
Regarding claim 7, claim 2 of the patent recites the apparatus of claim 1, further comprising a mode register configured to provide the signal to enter the low power mode to the synchronizer.
Regarding claim 8, claim 3 of the patent recites the apparatus of claim 7, wherein the mode register is configured to provide the signal to enter the low power mode in response to receipt of an external command to enter a Maximum Power Savings Mode.
Regarding claim 9, claim 1 of the patent recites the apparatus of claim 1, wherein the synchronizer is configured to intermittently enable and disable the output signal based on a duty cycle of the enable signal.
Regarding claim 10, claim 5 or claim 6 of the patent recites the apparatus of claim 1, wherein: the duty cycle of the enable signal is less than fifty percent; or the duty cycle of the enable signal is less than ten percent.
Regarding claim 11, claim 10 of the patent recites the apparatus of claim 1, further comprising an on-die termination circuit configured to control on-die termination settings based on the second clock signal.
Regarding claim 20, claim 16 of the patent recites a method, comprising:
generating an enable signal based on negative-bias temperature instability (NBTI) of a circuit component of a memory (claim 16, lines 5-7); and
in response to a mode register setting (MRS) command to enter a power savings mode (claim 16, MPSM), intermittently enabling and disabling a clock signal based on the enable signal.
Regarding claim 21, claim 16 of the patent recites the method of claim 20, further comprising receiving the MRS command to enter the power savings mode, wherein the power savings mode is a Maximum Power Savings Mode (MPSM).
Regarding claim 22, claim 21 of the patent recites the method of claim 21, wherein:
the MRS command to enter the MPSM is a first MRS command to enter the MPSM;
the clock signal is a first clock signal; and
the method further comprises, in response to receipt of a second MRS command to exit the MPSM, providing a second clock signal based on a column select command.
Regarding claim 23, claim 16 of the patent recites the method of claim 20, wherein:
generating the enable signal based on the NBTI of the circuit component of the memory comprises generating the enable signal having a duty cycle based on the NBTI of a circuit component of a memory; and
in response to the MRS command to enter the power savings mode, intermittently enabling and disabling the clock signal based on the enable signal comprises in response to the MRS command to enter the power savings mode, intermittently enabling and disabling the clock signal based, on the duty cycle of the enable signal.
Regarding claim 24, claim 18 of the patent recites the method of claim 23, further comprising setting the duty cycle of the enable signal to one of less than fifty percent or less than ten percent.
Regarding claim 25, claim 17 of the patent recites the method of claim 23, further comprising determining the duty cycle of the enable signal based on an output of a counter based on the NBTI of the circuit component of the memory.
Allowable Subject Matter
Claims 12-19 are allowed.
Claims 5 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein the reset circuit comprises: a first NOR gate configured to receive an output of a first NAND gate and an output of the first of the serially-coupled flip-flops; a second NOR gate configured to receive an input of the last one of the serially- coupled flip-flops and an output of the last one of the serially-coupled flip-flops; and a second NAND gate configured to receive an output of the first NOR gate and an output of the second NOR gate and provide the reset signal to each flip-flop in the plurality of serially-coupled flip-flops.” in combination with the other limitations thereof as is recited in the claim.
Regarding claim 6, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “a NAND gate configured to receive the output signal and a column select command signal and provide a column select signal to the clock driver circuit, wherein the clock driver circuit is configured to intermittently enable and disable the second clock signal based on the column select signal.” in combination with the other limitations thereof as is recited in the claim.
Regarding claim 12, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “a clock driver circuit configured to receive the first clock signal and intermittently enable and disable provision of a second clock signal to the input/output circuit based on the output signal.” in combination with the other limitations thereof as is recited in the claim. Claims 13-19 depend on claim 12.
Conclusion
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/HUAN HOANG/Primary Examiner, Art Unit 2827