Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9, and 15-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Shin (Patent Application Publication 2021/0391019).
Claim 1. An apparatus, comprising: a memory array comprising blocks of memory cells (blocks in memory array 100, Shin Fig 1); and a controller coupled to the memory array (200 Fig 1) and configured to (configured to is functional language): determine a boundary word line in a partially written block of the memory array (configured through memory the circuit comprising memory controller to determine a boundary word line in a partially written block of the memory array 100 Fig 1, boundary among the plurality of wordlines Shin [0007]), wherein the partially written block includes a number of erased word lines adjacent to the boundary word line (the partially written block in 100 Fig 1 includes a number of erased word lines adjacent to the boundary word line taught in Shin [0007]); determine a single data pattern level to write to at least one of the number of erased word lines adjacent to the boundary word line (configured through the circuit comprising memory controller 200 to determine a single data pattern level to write to at least one of the number of erased word lines adjacent to the boundary word line); and write the single data pattern level to the at least one of the number of erased word lines adjacent to the boundary word line (configured through memory controller 200 to write the single data pattern level to the at least one of the number of erased word lines adjacent to the boundary word line).
Claim 2. The apparatus of claim 1, wherein the memory array comprises NAND flash memory cells (NAND flash taught in Shin [0046]).
Claim 3. The apparatus of claim 1, wherein the controller is configured to (configured to is functional language) determine the single data pattern level from a look-up table (configured to determine the single data pattern level from a look-up table through controller 3210, Shin Fig 20. Mapping look up table taught in Shin [0223]).
Claim 4. The apparatus of claim 3, wherein the look-up table maps word line addresses to data pattern levels (Buffer Memory 3240 Shin Fig 20 stores meta data mapping table of word line addresses to data pattern levels, Shin [0223]).
Claim 5. The apparatus of claim 3, wherein the look-up table maps word line groups to data pattern levels (Buffer Memory 3240 Shin Fig 20 stores meta data mapping word line groups to data pattern levels, Shin [0223]).
Claim 6. The apparatus of claim 3, wherein the single data pattern level is one of multiple data pattern levels to which the memory cells are programmable (the single data pattern level is at least one of a multiple data pattern levels comprising logic low or high).
Claim 7. The apparatus of claim 1, wherein the controller is configured to (configured to is functional language) write the single data pattern level to the at least one of the number of erased word lines adjacent to the boundary word line starting with an erased word line immediately adjacent to the boundary word line (the controller 200 Shin Fig 1 is configured through a bus to write the single data pattern level to the at least one of the number of erased word lines of memory device 100 adjacent to the boundary word line starting with an erased word line immediately adjacent to the boundary word line).
Claim 8. The apparatus of claim 1, wherein the controller is configured to (configured to is functional language) write the single data pattern level to only one of the number of erased word lines adjacent to the boundary word line (the controller 200, Shin Fig 1, is configured through a bus to write the single data pattern level to only one of the number of erased word lines adjacent to the boundary word line in memory device 100).
Claim 9. The apparatus of claim 1, wherein the controller is configured to (configured to is functional language) write the single data pattern level to fewer than all of the number of erased word lines adjacent to the boundary word line (the controller 200, Shin Fig 1, is configured through a bus to write the single data pattern level to fewer than all of the number of erased word lines adjacent to the boundary word line in the memory device 100).
Claim 15. A system comprising: a controller (200 Shin Fig 1); a flash memory device (NAND flash taught in Shin [0046]) comprising a number of blocks of memory cell (blocks in memory array 100); and a controller coupled to the flash memory device (200 coupled to 100 Shin Fig 1) and configured to (configured to is functional language): write data to fewer than all of the word lines of a particular block of the number of blocks such that the particular block is a partially written block having a boundary word line at which the data ends leaving one or more erased word lines in the particular block (configured to through a bus to write data to fewer than all of the word lines of a particular block of the number of blocks in memory array 100 Shin Fig 1 such that the particular block is a partially written block having a boundary word line at which the data ends leaving one or more erased word lines in the particular block); and write a single data pattern level to at least one of the one or more erased word lines after the boundary word line (configured to through bus out of controller 200 to write a single data pattern level to at least one of the one or more erased word lines after the boundary word line).
Claim 16. The system of claim 15, wherein the memory cells are programmable to one of a plurality of different data pattern levels (the memory cells are programmable to one of at least a logic low or high), and wherein the single data pattern level is a particular one of the plurality of different data pattern levels (when programming a patter of 0 or 1 the single data pattern level is a particular one of the plurality of different data pattern levels).
Claim 17. The system of claim 16, wherein the plurality of different data pattern levels comprises at least eight different data pattern levels (multi-level bit cells storing four data bits comprise at least eight different data pattern levels, Shin [0044]).
Claim 18. The system of claim 15, wherein the controller is configured to (configured to is functional language) access a look-up table to determine the single data pattern level to be written to the at least one of the one or more erased word lines after the boundary word line (configured to access a look-up table to determine the single data pattern level to be written to the at least one of the one or more erased word lines after the boundary word line through controller 3210, Shin Fig 20. Mapping look up table taught in Shin [0223]).
Claim 19. The system of claim 18, wherein the look-up table includes two or more word line groups each associated with an individual range of word line addresses and wherein each of the two or more word line groups is associated with a different single data pattern level (Buffer Memory 3240 Shin Fig 20 stores meta data mapping word line groups to different data pattern levels, Shin [0223]).
Claim 20. The system of claim 15, wherein the system comprises a managed NAND (MNAND) device (NAND flash taught in Shin [0046]. NAND is managed by controller 200 Shin Fig 1).
Allowable Subject Matter
Claims 10-14 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 10-14. writing data to a plurality of word lines of a block of memory cells, wherein the plurality of word lines includes a boundary word line at which the data ends leaving a number of erased word lines in the memory block to form a partially written block; and determining a single data pattern level to write to at least one of the number of erased word lines adjacent to the boundary word line; and writing the single data pattern level to the at least one of the number of erased word lines adjacent to the boundary word line, in combination with other limitations.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Lappas whose telephone number is (571) 270-1272. The examiner can normally be reached on M-F 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON LAPPAS/
Primary Examiner, Art Unit 2827