DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-15 are pending. Claims 1, 10 and 14 are independent.
Information Disclosure Statement
Applicant’s Information Disclosure Statement (IDS) filed September 9, 2025, has been considered.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “P2” in FIG. 4B has been used to designate both in-chip paths 1 and in-chip paths 2. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Typographical error: “In” replace with “On”
In the Specification, last sentence of paragraph 41, “For example, S2D COPY command with RAn, RAsec can be issued to write simultaneously from 8K bits of the two SRAM array 118 into their corresponding sense amplifier arrays 116 and DRAM array 112 based in the given address Ran and RAsec.”
In the Specification, last sentence of paragraph 42, “For example, D2S COPY command with RAn, RAsec can be issued to write simultaneously from DRAM array 112 and 8K bits of the sense amplifier arrays 116 into their corresponding two SRAM array 118 based in the given address Ran and RAsec.”
Misnumbering of Drawing Component: “188” replace with “118”
In the Specification, first sentence of paragraph 49, “Owing to high similarity in circuit and layout between the sense amplifier arrays 116 and the SRAM arrays 188.”
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”;
and the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims) 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsuo (U.S. Patent No 5,663,905).
Regarding independent claim 1, Matsuo discloses a hybrid memory chip, comprising (Abstract):
dynamic random-access memory (DRAM) arrays (e.g., FIG. 6: DA);
sense amplifier arrays (see FIGS. 17, 18: 16), adjacent to the DRAM arrays; and
static random-access memory (SRAM) arrays (e.g., FIG. 6: SA), adjacent to the DRAM arrays or the sense amplifier arrays, and one of static random-access memory (SRAM) arrays respectively abutted with one of the sense amplifier arrays (FIGS. 6, 17-18: SA, DA, 16, 20, para. 69-70, 118),
wherein the sense amplifier arrays are configured to perform access operations between the DRAM arrays and the SRAM arrays (FIGS. 17-18: 16, 20).
Regarding claim 2, Matsuo further discloses the hybrid memory chip according to claim 1, wherein bit lines (FIGS. 17-18: SBL1-SBLk, DBL1-DBLm, STL1-STLk, DTL1-DTLm) across the DRAM arrays extend through the sense amplifier arrays and the SRAM arrays, wherein the SRAM arrays are configured to be written with data stored in the DRAM arrays through the bit lines (see col. 23, lines 66-67), or the DRAM arrays are configured to be written with data stored in the SRAM arrays through the bit lines (see col. 24, lines 16-18).
Regarding claim 3, Matsuo further discloses the hybrid memory chip according to claim 1, further comprising: word line drivers (FIGS. 17-18: 1), adjacent to the DRAM arrays, the sense amplifier arrays and the SRAM arrays, wherein word lines (FIG. 17: WL1 . . . WLn) across the DRAM arrays and the SRAM arrays extend to the word line drivers.
Regarding claim 4, Matsuo further discloses the hybrid memory chip according to claim 3, wherein the DRAM arrays, the SRAM arrays, the sense amplifier arrays and the word line drivers are configured to perform a copy operation copying data stored in a single cell of one of the DRAM arrays to a single cell of one of the SRAM arrays (see col. 23, lines 66-67), or copying data stored in another single cell of one of the SRAM arrays to another single cell of one of the DRAM arrays (see col. 24, lines 16-18).
Regarding claim 5, Matsuo further discloses the hybrid memory chip according to claim 3, wherein the DRAM arrays, the SRAM arrays, the sense amplifier arrays and the word line drivers are configured to perform a copy operation copying data pattern stored in multiple cells of one of the DRAM arrays to multiple cells of one of the SRAM arrays (see col. 22, line 22-col. 23, line 67), or copying data pattern stored in multiple cells of one of the SRAM arrays to multiple cells of one of the DRAM arrays (see col. 22, line 22-col. 23, line 49 and col. 24, lines 1-18).
Regarding claim 6, Matsuo further discloses the hybrid memory chip according to claim 5, wherein data pattern stored in a row of cells of one of the DRAM arrays are copied to a row of cells in one of the SRAM arrays during the copy operation (see col. 22, line 22-col. 23, line 67), or data pattern stored in a row of cells of one of the SRAM arrays are copied to a row of cells in one of the DRAM arrays during the copy operation (see col. 22, line 22-col. 23, line 49 and col. 24, lines 1-18).
Regarding claim 7, Matsuo further discloses the hybrid memory chip according to claim 1, wherein two adjacent ones of the DRAM arrays (see e.g., FIG. 6: Das of block B1 and Bp) are spaced apart from each other with one of the sense amplifier arrays (see FIG. 17: 16 as applicable to FIG. 6’s blocks) and one of the SRAM arrays (e.g., FIG. 6: SA of the right block) in between (see FIGS. 6, 17-18; see col. 15, line 65-column 16, line 8; see also, col. 21, lines 46-54).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
Determining the scope and contents of the prior art.
Ascertaining the differences between the prior art and the claims at issue.
Resolving the level of ordinary skill in the pertinent art.
Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsuo (U.S. Patent No 5,663,905).
Regarding claim 8 – Matsuo discloses the hybrid memory chip according to claim 1 (See paragraph prior regarding claim 1). Matsuo does not disclose wherein two adjacent ones of the DRAM arrays are spaced apart from each other with one of the sense amplifier arrays and two of the SRAM arrays in between. The differences between the claim and the teachings of Matsuo is the arrangement of the DRAM arrays, sense amplifier arrays and the SRAM arrays. Applicant’s originally filed disclosure does not indicate any change in function or any evidence of unexpected results achieved by their claimed arrangement of the DRAM arrays, sense amplifier arrays and the SRAM arrays.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to simply rearrange the memory blocks of the chip disclosed by Matsuo (FIGS. 6, 17-18), to match the claimed invention’s chip layout. One of ordinary skill in the art would recognize that optimizing chip layout would maximize storage capacity and access speed while minimizing chip size and manufacturing costs (col. 3, lines 33-42). Also, circuit components can be rearranged without changing the function of a device granted the proper electrical connections are in place. Likewise, moving the position of the DRAM arrays, SRAM arrays, and sense amplifier arrays on the memory blocks, for the hybrid memory chip disclosed by Matsuo, would not change the electrical connections proper for exchanging data between the two different memory types. Thus, one of ordinary skill in the art according to known methods to yield predictable results could rearrange the memory block components wherein the operation of the hybrid memory device would remain unchanged (i.e., there would not have been any modification in operation by rearranging the DRAM arrays such that two SRAM arrays and one sense amplifier array are between the DRAM arrays) and the rearrangement these components would have been a mere obvious matter of design choice (See MPEP 2144.04 (VI)(C)).
Regarding claim 9, Matsuo discloses the hybrid memory chip according to claim 8 (See paragraph prior regarding claim 8). However, Matsuo does not disclose wherein each of the sense amplifier arrays is interposed between two of the SRAM arrays. The differences between the claim and the teachings of Matsuo is the arrangement of the DRAM arrays, sense amplifier arrays and the SRAM arrays. Applicant’s originally filed disclosure does not indicate any change in function or any evidence of unexpected results achieved by their claimed arrangement of the DRAM arrays, sense amplifier arrays and the SRAM arrays.
For the same rationale stated for claim 8, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to simply rearrange sense amplifier arrays with respect to the SRAM arrays in the memory blocks of the chips disclosed by Matsuo (FIGS. 6, 17-18) because the rearrangement of the sense amplifier arrays to be between two SRAM arrays would not yield any modification in the operation and the rearrangement these components would have been a mere obvious matter of design choice (See MPEP 2144.04 (VI)(C)).
Claim(s) 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over Applicant Admitted Prior Art (illustrated in Figures 1 and 2, disclosed in Specification paragraphs 2-5) in view of Matsuo (U.S. Patent No 5,663,905).
Regarding independent claim 10, Applicant Admitted Prior Art discloses a memory system, comprising: a first primary memory (AAPA Fig. 1: C102) integrated with a central processing unit (CPU) (AAPA Fig. 1: C100) in a processor chip (AAPA Fig. 1: C104) and comprising first static random-access memory (SRAM) arrays (see AAPA para. 2: C102 is an SRAM); and a main memory (AAPA Fig. 10: C106) external to the processor chip comprising dynamic random-access memory (DRAM) arrays (see AAPA para. 4: C106 is DRAM; see generally AAPA FIGS. 1-2, Spec. para. 2-5).
Matsuo discloses what Applicant Admitted Prior Art fails to disclose that is: a second primary memory, comprising second SRAM arrays; and the main memory, comprising dynamic random-access memory (DRAM) arrays, integrated with the second primary memory in a hybrid memory chip (FIGS. 6, 17-18).
It would have been obvious by a person with ordinary skill in the art, before the effective filing date of the claimed invention, to simply replace the external main memory chip disclosed by Applicant Admitted Prior Art with the hybrid memory chip disclosed by Matsuo, MPEP 2143(B) (simple substitution of one known element for another to obtain predictable results), whereby, this substitution does not render the memory system inoperable or change its principle of operation. One of ordinary skill in the art would also recognize that proper chip selection is crucial to maximizing storage capacity and access speed while minimizing chip size and manufacturing costs (Matsuo: col. 3, lines 33-42). Also, while large storage capacity is important, data transfer of an uncomplimentary speed means the system operates below full potential. Compared to inter-chip communication illustrated in Applicant Admitted Prior Art, the hybrid chip offers in-chip data communication between the different memory types which further optimizes the system.
Regarding claim 11, Applicant Admitted Prior Art and Matsuo, as combined, disclose the memory system according to claim 10 (See paragraph prior regarding claim 10).
Applicant Admitted Prior Art and Matsuo, as combined, disclose the second primary memory is configured to store data provided from the main memory, and data transfer between the second primary memory and the main memory is implemented without using an external bus extending between the processor chip and the hybrid memory chip (Matsuo: FIGS. 6, 17-18).
Regarding claim 12, Applicant Admitted Prior Art and Matsuo discloses
the memory system according to claim 10 (See paragraph prior regarding claim 10).
Applicant Admitted Prior Art and Matsuo, as combined, disclose the second SRAM arrays of the second primary memory are abutted with sense amplifier arrays around the DRAM arrays of the main memory in the hybrid memory chip (FIGS. 6, 17-18: SA, DA, 16, 20).
Regarding claim 13, Applicant Admitted Prior Art and Matsuo discloses
the memory system according to claim 12 (See paragraph prior regarding claim 12).
Applicant Admitted Prior Art and Matsuo, as combined, disclose bit lines across the DRAM arrays of the main memory extend through the sense amplifier arrays and the second SRAM arrays of the second primary memory (FIGS. 17-18: SBL1-SBLk, DBL1-DBLm, STL1-STLk, DTL1-DTLm, 18).
Regarding independent claim 14, Applicant Admitted Prior Art discloses a computing apparatus, comprising: a processor chip (AAPA Fig. 1: C104), in which a central processing unit (CPU) (AAPA Fig. 1: C100) and a first primary memory (AAPA Fig. 1: C102) are integrated, wherein the first primary memory comprises first static random-access memory (SRAM) arrays (AAPA Spec. para. 2: C102 is SRAM). The admitted prior art also discloses a main memory (AAPA Fig. 1: C106), comprising dynamic random-access memory (DRAM) arrays (AAPA Spec. para. 4: C106is DRAM), externally connected with the processor chip via an external bus (AAPA FIGS. 1-2, para. 2-5).
Matsuo further discloses what Applicant Admitted Prior Art fails to disclose that is: a hybrid memory chip wherein a second primary memory and a main memory are integrated in the hybrid memory chip, the second primary memory comprises second SRAM arrays, and the main memory is formed of dynamic random-access memory (DRAM) arrays (FIGS. 6, 17-18: SA, DA).
For the same rationale stated for claim 10 but with respect to an apparatus, it would have been obvious by a person with ordinary skill in the art before the effective filing date of the claimed invention to simply replace the external main memory chip disclosed by Applicant Admitted Prior Art with the hybrid memory chip disclosed by Matsuo, MPEP 2143(B) (simple substitution of one known element for another to obtain predictable results), whereby, the apparatus is configured the same as the claimed invention, with a hybrid memory chip in connection with the processor chip.
Regarding claim 15, Applicant Admitted Prior Art and Matsuo discloses the computing apparatus according to claim 14 (See paragraph prior regarding claim 14).
Applicant Admitted Prior Art and Matsuo, as combined, disclose the second primary memory is configured to store data provided from the main memory, and data transfer between the second primary memory and the main memory is implemented without using the external bus (FIGS. 6, 17-18: SA, DA, 16, 20).
Conclusion
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/N.T.P./Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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