CTFR 18/793,963 CTFR 100777 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Amendment This office action is responsive to communication(s) filed on March 27, 2026. Claims 1-5, 7-12, 14-15 are presented for examination. Applicant’s arguments with respect to the rejection(s) of claim(s) 1-5, 7-12, and 14-15 under 35 U.S.C. § 103 have been fully considered and are persuasive. However, upon further consideration, Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Applicants’ arguments are rendered moot in view of the present Office Action. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-5 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Moriwaki (US 20150279449 A1) in view of Rotem et al. (US 20050283625 A1) . Regarding claim 1: Moriwaki discloses an electronic device (semiconductor device, FIG. 1), comprising: a plurality of circuit blocks (plurality of word line driver blocks, par. 82, FIGs. 1 and 9); and a plurality of switch sets (control circuits with transistors e.g., TP0 and TP1 of 710-71m, FIGs. 9 and 19) respectively coupled to the plurality of circuit blocks, wherein the plurality of switch sets provide a first voltage (voltage VDD, FIGs. 18 and 20) to the plurality of corresponding circuit blocks (word line driver blocks 10-1m, FIGs. 17 and 19) in a normal mode (WL<0> increased to voltage VDD during normal operation, FIGs. 18 and 20), the plurality of switch sets respectively provide a plurality of second voltages (plurality of voltages Vst, par. 95, FIGs. 18 and 20) to the plurality of corresponding circuit blocks (word line driver blocks 10-1m, FIGs. 17 and 19) in a standby mode (WLVD and VLVS at plurality of voltages Vst during standby operation, FIGs. 18 and 20), wherein a voltage value of the first voltage (voltage VDD, FIGs. 18 and 20) is greater than a voltage value of each of the plurality of second voltages (Voltage VDD greater than plurality of voltages Vst, FIGs 18 and 20). Moriwaki does not disclose an electronic device, comprising: wherein the plurality of second voltages provided by any two of the plurality of switch sets have different voltage values during the standby mode. Rotem does disclose a system and method for controlling standby power, wherein the plurality of second voltages (reduced voltages delivered from voltage regulator 22, FIG. 1) provided by any two of the plurality of switch sets (multiplexing logic 40 for controlling voltage sent to computing system components 28a-28n, par. 20-22, FIG. 2) have different voltage values during the standby mode (during idle (standby) mode, each component of system having a different low power voltage, par. 20). It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Moriwaki with the standby power control configuration of Rotem to allow each circuit component of the device to have different standby voltages for better power savings and reduced leakage current. Regarding claims 2-3, and 12: Moriwaki discloses an electronic device (semiconductor device, FIG. 1), wherein each of the plurality of switch sets (control circuits with transistors e.g., TP0 and TP1 of 710-71m, FIGs. 9 and 17) comprises: a first switch (transistor TP0, FIGs. 9 and 17) having a first terminal for receiving the first voltage (VDD, FIG. 17), wherein a second terminal of the first switch is coupled to each of the plurality of corresponding circuit (plurality of word line driver blocks, par. 82, FIGs. 1 and 9), the first switch is controlled by a first control signal (complementary SLPX by inverter I0) and a second switch (transistor TP1, FIGs. 9 and 17) having a first terminal for receiving the second voltage (voltage Vst from VDD affected by R, FIG. 17), wherein a second terminal of the second switch is coupled to each of the plurality of corresponding circuit blocks (plurality of word line driver blocks, par. 82, FIGs. 1 and 9) and the second switch is controlled by a second control signal (SLPX). Regarding claim 4: Moriwaki discloses an electronic device (semiconductor device, FIG. 1), wherein a conduction state of the first transistor (NMOS transistor TN0, FIG. 15) is complementary to a conduction state of the second transistor (PMOS transistor TP1, FIG. 15), and the first control signal is the same (both TN0 and TP1 controlled by control signal SLPX, FIG. 15) as the second control signal. Regarding claim 5: Fig. 9 of Moriwaki discloses wherein a conduction state of the first transistor (TP0) is the same as a conduction state of the second transistor (TP1), and the first control signal (complementary of SLPX by inverter I0) is complementary to the second control signal (SLPX). Regarding claim 11: Moriwaki discloses a memory device (semiconductor device, FIG. 1), comprising: a plurality of circuit blocks (plurality of word line driver blocks, par. 82, FIGs. 1 and 9); and a plurality of switch sets (control circuits with transistors e.g., TP0 and TP1 of 710-71m, FIGs. 9 and 17) respectively coupled to the plurality of circuit blocks, wherein the plurality of switch sets provide a first voltage (voltage VDD, FIGs. 18 and 20) to the plurality of corresponding circuit blocks (word line driver blocks 10-1m, FIGs. 17 and 19) in a normal mode (WL<0> increased to voltage VDD during normal operation, FIGs. 18 and 20), the plurality of switch sets respectively provide a plurality of second voltages (plurality of voltages Vst, par. 95, FIGs. 18 and 20) to the plurality of corresponding circuit blocks (word line driver blocks 10-1m, FIGs. 17 and 19) in a standby mode (WLVD and VLVS at plurality of voltages Vst during standby operation, FIGs. 18 and 20), wherein a voltage value of the first voltage (voltage VDD, FIGs. 18 and 20) is greater than a voltage value of each of the plurality of second voltages (Voltage VDD greater than plurality of voltages Vst, FIGs 18 and 20), wherein each of the plurality of circuit blocks is a memory cell array circuit, a read/write control circuit, an address decoding circuit (1, Fig. 1 or Fig. 9), a page buffer circuit or a sensor amplifier circuit. Moriwaki does not disclose an electronic device, comprising: wherein the plurality of second voltages provided by any two of the plurality of switch sets have different voltage values during the standby mode. Rotem does disclose a system and method for controlling standby power, wherein the plurality of second voltages (voltages delivered from voltage regulator 22, FIG. 1) provided by any two of the plurality of switch sets (multiplexing logic 40 for controlling voltage sent to computing system components 28a-28n, par. 20-22, FIG. 2) have different voltage values during the standby mode (during idle (standby) mode, each having a different low power voltage, par. 20). It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Moriwaki with the standby power control configuration of Rotem to allow each circuit component of the device to have different standby voltages for better power savings and reduced leakage current . 07-21-aia AIA Claim (s) 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Moriwaki (US 20150279449 A1) in view of Rotem et al. (US 20050283625 A1), in further view of Park et al. (US 20080211466 A1) . Regarding claim 7: Moriwaki and Rotem do not disclose an electronic device, further comprising: a plurality of voltage generators respectively generating the plurality of second voltages according to a third control signal. Park does disclose voltage generators further comprising: a plurality of voltage generators (plurality of voltage generators 100, par. 5, FIG. 1) respectively generating the plurality of second voltages (voltages e.g., AVDD, VGH, par. 25, FIG. 2) according to a third control signal (control signal from control circuit 110, par. 25). It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Moriwaki and Rotem with the configuration of Park to allow the system to have the described voltage generator configuration. Regarding claim 14: Moriwaki and Rotem do not disclose a memory device, further comprising: a plurality of voltage generators respectively generating the plurality of second voltages according to a third control signal. Park does disclose voltage generators further comprising: a plurality of voltage generators (plurality of voltage generators 100, par. 5, FIG. 1) respectively generating the plurality of second voltages (voltages e.g., AVDD, VGH, par. 25, FIG. 2) according to a third control signal (control signal from control circuit 110, par. 25). It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Moriwaki and Rotem with the configuration of Park to allow the system to have the described voltage generator configuration . 07-21-aia AIA Claim (s) 8-10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Moriwaki (US 20150279449 A1) in view of Rotem et al. (US 20050283625 A1), in further view of Park et al. (US 2008/0211466 A1), in further view of Son (US 20100164550 A1) . Regarding claim 8: Moriwaki, Rotem, and Park do not disclose an electronic device wherein each of the plurality of voltage generators comprises: a switch determining whether to provide an enable signal based on the third control signal; and a voltage regulator generating each of the plurality of second voltages according to the enable signal and a reference voltage based on a power supply voltage. Son does disclose a comparing device with voltage regulators wherein each of the plurality of voltage generators comprises: a switch (switching box 50, FIG. 1) determining whether to provide an enable signal (feedback FB1, FIG. 1) based on the third control signal (signal from switching controller 60, FIG. 1); and a voltage regulator (voltage generator 10, FIG. 1) generating each of the plurality of second voltages (VOUT, FIG. 1) according to the enable signal (feedback FB1, FIG. 1) . It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Moriwaki, Rotem, and Park with the configuration of Son to allow the system to have the voltage generators with regulators as described. Regarding claim 9: Moriwaki, Rotem, and Park do not disclose an electronic device wherein a voltage value of the power supply voltage is greater than a voltage value of each of the plurality of second voltages. Son does disclose a comparing device with voltage regulators wherein a voltage value of the power supply voltage (supply voltage VIN1, FIG. 1) is greater (voltage regulator adapted to generate desired output voltage VOUT after reducing excessive input voltage VIN1, making power supply greater, par. 6) than a voltage value of each of the plurality of second voltages (VOUT, FIG. 1). It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Moriwaki, Rotem, and Park with the configuration of Son to allow the regulator to ensure the input supply voltage to correctly be filtered to lower output voltages as described. Regarding claim 10: Moriwaki, Rotem, and Park do not disclose wherein the voltage regulator is a low dropout voltage regulator. Son does disclose a comparing device with voltage regulators wherein the voltage regulator is a low dropout voltage regulator (regulator may be linear, low dropout (LDO) regulator, par. 6). It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Moriwaki, Rotem, and Park with the configuration of Son to allow the voltage regulator to be the described low dropout type for the operation. Regarding claim 15: Moriwaki, Rotem, and Park do not disclose a memory device, wherein each of the plurality of voltage generators comprises: a switch determining whether to provide an enable signal based on the third control signal; and a voltage regulator generating each of the plurality of second voltages according to the enable signal and a reference voltage based on an operating voltage. Son does disclose a comparing device with voltage regulators wherein each of the plurality of voltage generators comprises: a switch (switching box 50, FIG. 1) determining whether to provide an enable signal (feedback FB1, FIG. 1) based on the third control signal (signal from switching controller 60, FIG. 1); and a voltage regulator (voltage generator 10, FIG. 1) generating each of the plurality of second voltages (VOUT, FIG. 1) according to the enable signal (feedback FB1, FIG. 1). It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Moriwaki, Rotem, and Park with the configuration of Son to allow the system to have the voltage generators with regulators as described. Response to Arguments Applicant’s arguments with respect to claim(s) 1-5, 7-12, and 14-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANTHONY THINH TANG/Examiner, Art Unit 2827 /AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827 Application/Control Number: 18/793,963 Page 2 Art Unit: 2827 Application/Control Number: 18/793,963 Page 3 Art Unit: 2827 Application/Control Number: 18/793,963 Page 4 Art Unit: 2827 Application/Control Number: 18/793,963 Page 5 Art Unit: 2827 Application/Control Number: 18/793,963 Page 6 Art Unit: 2827 Application/Control Number: 18/793,963 Page 7 Art Unit: 2827 Application/Control Number: 18/793,963 Page 8 Art Unit: 2827 Application/Control Number: 18/793,963 Page 9 Art Unit: 2827 Application/Control Number: 18/793,963 Page 10 Art Unit: 2827
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