DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because the unlabeled rectangular box(es) shown in the drawing should be provided with descriptive text labels. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding the claim 1 recitation “drawing a plurality of wafer-level test measurements and associated final test yields”, the examiner presumes that the drawing is performed from among the previously-recited training data set, but this is not clear from the claim language. Clarification is required so that the scope of the claim is clear.
In the “predicting final test yields” step, it is unclear which wafer “the wafer” refers. In the “drawing” step, it appears that wafer-level measurements and associated final test yield are drawn for a plurality of the wafers of the training data set, and that the “predicting” and “aggregating” is performed for those wafers as a part of the teaching/training process. Clarification is required so that the scope of the claim is clear.
Claims 2-9 are rejected under 35 U.S.C. 112(b) by virtue of their dependence from claim 1.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-2, 4-5 and 7-9 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract without significantly more. In particular, analyzing these claims under 2019 Revised Patent Subject Matter Eligibility Guidance:
Claim 1 recites a method for teaching a machine learning system to predict failure probabilities of chips on a wafer, comprising:
providing a training data set comprising a plurality of wafers, each with wafer-level test measurements and an associated final test yield;
repeating several times:
drawing a plurality of wafer-level test measurements and associated final test yields,
predicting final test yields depending on the plurality of wafer-level test measurements by the machine learning system, wherein the machine learning system determines the failure probabilities of the chips on the wafer depending on the plurality of wafer-level test measurements,
aggregating the determined failure probabilities to the predicted final test yields, and
teaching the machine learning system, such that a mathematical difference between the predicted final test yield and the assigned final test yield is minimized.
Step 1:
Claim 1 is directed to a method for teaching a machine learning system to predict failure probabilities of chips on a wafer and therefore falls within the four statutory categories of subject matter (process).
Step 2A, prong 1:
At least the highlighted recitations of claim 1 set forth above relate to abstract ideas in the form of mental processes practically performed in the human mind (including an observation, evaluation, judgment, opinion) or with pen/paper. In particular the language “repeating several times: … predicting final test yields depending on the plurality of wafer-level test measurements by the machine learning, wherein the machine learning determines the failure probabilities of the chips on the wafer depending on the plurality of wafer-level test measurements, aggregating the determined failure probabilities to the predicted final test yields, and teaching the machine learning, such that a mathematical difference between the predicted final test yield and the assigned final test yield is minimized” has a scope that includes mental processes practically performed in the human mind (including an observation, evaluation, judgment, opinion) or with pen/paper when given its broadest reasonable interpretation in light of the specification. Specifically, the examiner notes that the term “machine learning” is broad and encompasses the application of statistical techniques such as Bayesian prediction, for example, to perform predictive modeling. The claim does not specify a particular number of chips (two or more) on the wafer being considered, a particular number of wafers comprising the training data (two or more), or the amount or nature of wafer-level test measurements of the training wafer data. There is nothing in the claim that appears to foreclose applying algorithms such as Bayesian prediction by a human, mentally or with pen and paper, to determine the failure probabilities of the chips on a wafer given a set of prior wafer-level test measurements. Similarly, there is nothing in the claim that appears to foreclose aggregating the determined failure probabilities to the predicted final test yields, and iteratively repeating/refining the application of Bayesian prediction with additional data until a satisfactory level of prediction accuracy is obtained.
Step 2A, prong 2:
Claim 1 recites as additional elements “providing a training data set comprising a plurality of wafers, each with wafer-level test measurements and an associated final test yield” and “drawing a plurality of wafer-level test measurements and associated final test yields”. These additional elements would appear to represent no more than insignificant extra-solution activity in the form of mere data gathering in conjunction with an abstract idea. Considered alone or in combination with the abstract idea and the additional element discussed below, these steps do not represent integration of the abstract idea into a practical application.
Claim 1 further recites as an additional element a “machine learning system”. The term “machine learning system”, considered in light of the disclosure, has a scope that includes a computer for implementing a machine learning algorithm (see, e.g., specification, paragraph 18). Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general-purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more. See, e.g., MPEP 2106.05(f). This additional element, considered alone or in combination with the abstract idea and the additional elements discussed above, does not integrate the abstract idea into a practical application under Step 2A, prong 2 or provide significantly more than the abstract idea itself under Step 2B.
Step 2B
The additional elements discussed above at Step 2A relate to insignificant extra-solution activity in the form of mere data gathering and the addition of a general-purpose computer or computer components after the fact to an abstract idea. Considered alone or in combination with the abstract idea, these additional elements do not provide significantly more than the abstract idea itself under Step 2B.
Each of dependent claims 2 and 4-5 appear to further elaborate on the abstract ideas identified above in connection with claim 1 and/or recite additional abstract ideas in the form of mental processes practically performed in the human mind. None of dependent claims 2 and 4-5 appear to recite any additional element(s) that would serve to integrate the abstract ideas into a practical application under Step 2A, prong 2 or provide significantly more than the abstract ideas under Step 2B. Dependent claims 2 and 4-5 are therefore not patent eligible under 35 U.S.C. 101. Dependent claim 7 recites a computer program implementation of the method of claim 1 and does qualify as patent-eligible subject matter for the reasons discussed above in connection with claim 1 (addition of a general-purpose computer or computer components after the fact to an abstract idea insufficient to integrate the abstract idea into a practical application under Step 2A, prong 2 or provide significantly more than the abstract ideas under Step 2B). Claim 8 is directed to a data processing device for implementing the method of claim 1, and claim 9 is directed to a non-transitory computer-readable medium having computer-executable instructions for causing a computer to implement the method of claim 1. Claims 8-9 do not qualify as patent-eligible subject matter for reasons analogous to those discussed above in connection with claim 1 (addition of a general-purpose computer or computer components after the fact to an abstract idea insufficient to integrate the abstract idea into a practical application under Step 2A, prong 2 or provide significantly more than the abstract ideas under Step 2B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3 and 5-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2001/0023083 to Simmons (Simmons) in view of P. Lenhard, A. Kovalenko and R. Lenhard, "Integrated Circuit Die Level Yield Prediction Using Deep Learning," 2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), Saratoga Springs, NY, USA, 2022, pp. 1-6 (Lenhard).
Regarding claim 1, Simmons discloses a method to predict failure probabilities of chips on a wafer, comprising:
drawing a plurality of wafer-level test measurements
predicting depending on the plurality of wafer-level test measurements by wherein determines the failure probabilities of the chips on the wafer depending on the plurality of wafer-level test measurements (Simmons, e.g., Fig. 2A and paragraphs 29-50, in Step 26, each defect 14 detected by the surface inspection tool is then assigned a defect weight value WV which reflects its projected effect on wafer yield; the defect weight value WV is based on defect size and part type specific geometry parameters, as known from historical records and/or projected therefrom; the algorithm of the invention may be set up to associate a particular defect weight value WV based on (a) defect size and (b) location of the defect 14 on an IC die 16; the greater the value of the defect weight, the greater the projected impact on yield; for each inspected IC die 16 of the wafer 12; in Step 28, the defect weight values of the applicable defect(s) 14 are used to produce a die yield loss metric DYL; this DYL has values between X and Y, where X and Y may be 0.0 and 1.0, for example; a DYL value of 0.0 represents a prediction of no yield loss, and a value of 1.0 represents a prediction of a fatal yield loss from the defect(s), i.e. no yield; thus, the higher the DYL value, the greater the predicted effect of the defect(s) on the IC die; the cumulative effect of all weighted defects on an individual die i is calculated to produce a die yield loss value DYLi for that die; a DYL value for each IC die on the wafer 12 is calculated),
aggregating the determined failure probabilities to t
Simmons discloses in connection with the determination of die yield loss at steps 26-28 of Fig. 2A that each defect 14 detected by the surface inspection tool is assigned a defect weight value WV which reflects its projected effect on wafer yield, with the defect weight value WV being based on defect size and part type specific geometry parameters, as known from historical records and/or projected therefrom (Simmons, e.g., paragraph 46). Simmons discloses that the algorithm may associate a particular defect weight value WV based on (a) defect size and (b) location of the defect 14 on an IC die 16, and that the greater the value of the defect weight, the greater the projected impact on yield (Simmons, e.g., paragraph 46). Simmons therefore discloses the use of historical records to obtain the association between defect weight value WV and the defect size and location parameters. Simmons is not relied upon as explicitly disclosing that the association based on historical records is obtained by using a trained machine learning system to determine the association.
Lenhard relates to, inter alia, deep learning techniques for IC yield prediction at the die-level (Lenhard, e.g., Abstract). Lenhard discloses that deep neural networks are suitable for predicting fail probability of a die (Lenhard, e.g., page 2, section B., for the die level prediction we used the same FNN architecture as for the regression task, with only change in the output layer, where a neuron with a sigmoid activation function was used to predict fail probability of the die). One of ordinary skill in the art would understand that neural networks, including neural networks of the type disclosed by Lenhard, may be trained using the iterative application of training data (e.g., previously collected or historical data) until the difference between an output predicted by the neural network and an actual target is suitably minimized.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Simmons such that the association between defect weight value WV and the defect size and location parameters is obtained using a machine learning algorithm, such as a neural network, with the machine learning algorithm being trained by repeating Simmons’s drawing, predicting and aggregating steps using a previously-collected/historical training data set comprising a plurality of wafers, with each wafer having wafer-level test measurements (e.g., wafer detect size/location) and an associated final test yield (e.g., overall wafer yield loss), until the learned association between defect weight value WV and the defect size is such that the difference between final test yields predicted by the machine learning algorithm and the associated final test yields of the training data is suitably minimized. In this way, in the manner disclosed by Lenhard, deep learning algorithms may be used perform die level prediction and wafer yields forecasts.
Regarding claim 2, Simmons in view of Lenhard discloses wherein the machine learning system has a topography set up to record the plurality of wafer-level test measurements as an input variable and to output a failure probability as an output variable for each chip on the wafer (see Simmons in view of Lenhard as applied to claim 1, noting that in modified Simmons the machine learning algorithm receives/records the plurality of wafer-level test measurements as an input variable and outputs a failure probability (die yield loss metric DYL) for each die on the wafer).
Regarding claim 3, Simmons in view of Lenhard discloses wherein the machine learning system is a neural network and an activation function of an output layer of the neural network is a sigmoid activation function (see Simmons in view of Lenhard as applied to claim 1, e.g., Lenhard, page 2, section B., for the die level prediction we used the same FNN architecture as for the regression task, with only change in the output layer, where a neuron with a sigmoid activation function was used to predict fail probability of the die).
Regarding claim 5, Simmons in view of Lenhard discloses using the trained machine learning system according to claim 1 to predict a failure probability in a final test for each chip on the wafer depending on wafer-level test measurements of a currently processed wafer (see Simmons in view of Lenhard as applied to claim 1, with the trained machine learning algorithm of modified Simmons being used to predict a failure probability in a final test for each chip on the wafer, e.g., at Step 28 of Fig. 2A subsequent to training, with this prediction depending on wafer-level test measurements of a currently processed wafer, e.g., a wafer that has been previously processed and used for training the machine learning algorithm).
Regarding claim 6, Simmons in view of Lenhard discloses wherein the chips for which the predicted failure probability is greater than a predetermined first threshold value are sorted out (see Simmons in view of Lenhard as applied to claim 1, Simmons, e.g., paragraph 37, Simmons discloses that a course of action includes identifying dice predicted to fail, and avoiding expenditure of resources on such dice, to the extent possible, which the examiner notes is tantamount to sorting out die for which the predicted failure probability is greater than predetermined threshold amount) and/or those chips for which the predicted failure probability is less than a predetermined second threshold value are installed with other chips less than the predetermined second threshold value in a final product.
Claim 7 recites wherein a computer program comprises instructions which, when the computer program is executed by a computer, cause the computer to execute the method, claim 8 recites a device for data processing configured to carry out the method according to claim 1, and claim 9 recites a non-transitory computer-readable storage medium comprising instructions which, when executed by a computer, cause the computer to execute the method according to claim 1. Simmons discloses that its method is advantageously digitally performed on a computer for ease and speed (Simmons, e.g., paragraph 78), and one of ordinary skill in the art would understand that the deep learning techniques discloses by Lenhard are necessarily performed using computers/processors. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Simmons in view of Lenhard to implement the processes of Simmons in view of Lenhard as applied to claim 1 using programmed processors at least in view of the advantages recognized by Simmons (e.g., ease and speed) and in view of the necessity of computers/processors for implementing the deep learning techniques discloses by Lenhard.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Simmons in view of Lenhard, and further in view of CN114397985A to Yang et al. (Yang).
Regarding claim 4, Simmons in view of Lenhard is not relied upon as explicitly disclosing performing an aggregation of the predicted failure probabilities to the predicted final test yield using an average calculation of the predicted failure probabilities. Yang relates to a processing method and device of wafer yield data and discloses that average yield values across multiple wafers is a useful statistic for showing which regions in a wafer have high or low failure rates (Yang, e.g., machine translation, page 6, utilize a wafer topological graph shows the yield statistic value (such as average yield) of each die position in a plurality of wafers, so as to facilitate the user to know which regions in the wafer has low failure rate or higher). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Simmons in view of Lenhard to include performing an aggregation of the predicted failure probabilities to the predicted final test yield using an average calculation of the predicted failure probabilities (e.g., an average calculation of the predicted failure probabilities across multiple wafers) at least in view of Yang’s disclosure that such statistics are useful for showing which regions in a wafer have high or low failure rates.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Laura Peters, Improving Yield With Machine Learning, 7/12/2022, available at https://semiengineering.com/improving-yield-with-machine-learning/ relates to the use of neural networks in semiconductor manufacturing.
Jang et al., "A Wafer Map Yield Prediction Based on Machine Learning for Productivity Enhancement," in IEEE Transactions on Semiconductor Manufacturing, vol. 32, no. 4, pp. 400-407, Nov. 2019 relates to a yield prediction model based on deep learning algorithms.
H. Selg, M. Jenihhin and P. Ellervee, "Wafer-Level Die Re-Test Success Prediction Using Machine Learning," 2020 IEEE Latin-American Test Symposium (LATS), Maceio, Brazil, 2020, pp. 1-5, relates to a method for applying Machine Learning to efficiently predict whether it is favorable to invest extra time into re-test of a particular failed die.
US 5,777,901 to Berezin relates to a method and system for performing in-line spacial map analysis of semiconductor wafer defects to predict die yield.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL R MILLER whose telephone number is (571) 270-1964. The examiner can normally be reached 10AM-6PM EST M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak, can be reached on (571) 270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL R MILLER/Primary Examiner, Art Unit 2858