Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/ Restrictions
Applicant's election of group II without traverse: claims 1-7, in the “Response to Election / Restriction Filed - 07/28/2026”, withdrawal of non-elected claim(s) 8-12 is/are acknowledged. This office action considers claims 1-12, in “Claims - 08/05/2024”, pending for prosecution, of which claim(s) 8-12 is/are withdrawn.
Priority
Acknowledgment is made of applicant's claim for foreign benefit based on DE10 2023 126 006.5 filed on 09/26/2023.
Claim Rejections - 35 USC § 112
The following is a quotation of the second paragraph of 35 U.S.C. 112:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites:
“an encapsulant embedding the semiconductor die, wherein the first leads and the
second leads are disposed outside the encapsulant”. There is insufficient antecedent basis for this limitation in the claim. The applicant may recite the following to overcome this rejection:
“an encapsulant embedding the semiconductor die, wherein the one or more first leads and the one or more second leads are disposed outside the encapsulant”.
Claim 1 further recites:
“the first die pad of the first leadframe is completely exposed at the top surface of the device”. There is insufficient antecedent basis for this limitation in the claim. The applicant may recite the following to overcome this rejection:
“the first die pad of the first leadframe is completely exposed at the top surface of the semiconductor device”.
Claim 2 recites:
“the first leads extend outside the encapsulant from the first level to a third level, and the second leads extend outside the encapsulant from the second level to the third level”. There is insufficient antecedent basis for this limitation in the claim. The applicant may recite the following to overcome this rejection:
“the one or more first leads extend outside the encapsulant from the first level to a third level, and the one or more second leads extend outside the encapsulant from the second level to the third level”.
Claim 7 recites:
“wherein the device is a leaded package”. There is insufficient antecedent basis for this limitation in the claim. The applicant may recite the following to overcome this rejection:
“wherein the semiconductor device is a leaded package”.
Claims 2-7 depend from claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(2):
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1, 3, 7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Saklang et al. (US 20240178111 A1 – hereinafter Saklang).
Regarding Claim 1, Saklang teaches a semiconductor device (see the entire document; Fig. 6 in view of Figs. 2-5; specifically, [0010]-[0012], and as cited below), comprising:
a first leadframe comprising a first die pad (108 – Fig. 6 – [0011]) and one or more first leads (112 – [0012] – see also Fig. 4) formed integral with the first die pad (108) and extending outward from the first die pad in a first direction (-y direction);
a second leadframe comprising a second die pad (106 – [0011]) and one or more second leads (110 – [0012] – see also Fig. 4) formed integral with the second die pad (106) and extending outward from the second die pad (106) in a second direction different than the first direction (y direction);
a semiconductor die (102 – [0012]) disposed between the first die pad (108) and the second die pad (106); and
an encapsulant (118 – [0016]) embedding the semiconductor die (102), wherein the first leads (112) and the second leads (110) are disposed outside the encapsulant (118);
characterized in that the first die pad (108) of the first leadframe is completely exposed at the top surface of the device (Fig. 6 shows top surface of 108 is completely exposed).
Regarding Claim 3, Saklang teaches the semiconductor device according to claim 1, wherein the semiconductor die is a vertical semiconductor transistor die, in particular a semiconductor power transistor die, an IGBT die, a MOSFET die, a CoolMOS die, a wide band gap semiconductor transistor die, in particular a SiC transistor die (SoC – [0010]).
Regarding Claim 7, Saklang teaches the semiconductor device according to claim 1, wherein the device is a leaded package (leadframe package – [0015].
Allowable Subject Matter
Claims 2, 4-6 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner’s Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 2: The semiconductor device according to claim 1, wherein the first die pad is disposed on a first level, and the second die pad is disposed on a second level, and the first leads extend outside the encapsulant from the first level to a third level, and the second leads extend outside the encapsulant from the second level to the third level.
Regarding claim 4: The semiconductor device according to claim 3, wherein the semiconductor transistor die comprises a first main face and a second main face opposite to the first main face, and a source pad disposed on the first main face and a drain pad disposed on the second main face.
Claims 5-6 depend from claim 4.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898
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