DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Applicant is advised that this Double Patenting rejection will not be held in abeyance. See MPEP § 804(I)(B)(1); 37 CFR § 1.111(b).
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6, 9, 13, and 16 of U.S. Patent No. 12,056,073 in view of Mukherjee et al. (U.S. Patent Application Publication Number 2015/0089184) and Campbell (U.S. Patent Number 6,385,712). The conflicting patent claims (e.g., Claim 1) do not expressly require a memory configured to store an address map and wherein the interface is configured to determine the address space of the second address based on the first address and the address map. However, Mukherjee discloses a memory configured to store an address map (paragraph 0125; i.e., upon receiving a GVA, it is determined whether the GVA is mapped to a guest physical address [GPA], or specifies an unmapped address space, which would indicate that a memory storing an address map is present) and wherein the interface is configured to determine the address space of the second address based on the first address and the address map (paragraphs 0124-0125; i.e., it is determined whether the GVA is mapped to a guest physical address [GPA], or specifies an unmapped address space; therefore, the determination of the address space of the second address is based on the GVA as well as the address map [it may be a mapped or unmapped address space]). It would have been obvious to one of ordinary skill in the art to have combined Mukherjee with the conflicting patent, for the purpose of providing a simple and efficient mechanism to determine whether the address needs to be translated or not.
The conflicting patent claims (e.g., Claim 11) also do not expressly require the processor is associated with an address space; the output is configured to provide an indication of whether the second address is associated with the address space of the processor. However, Campbell teaches the processor is associated with an address space (Figure 3, item 303, Column 2, lines 25-29; i.e., an address space of a native processor); the output is configured to provide an indication of whether the second address is associated with the address space of the processor (Figure 4, item 401, Column 5, lines 3-15; i.e., an address space tag 401 is included with the second virtual address 402; this address space tag 401 provides an “indication” of whether the second virtual address 402 is associated with the native processor address space because it differentiates between the address spaces of the various types of processors). It would have been obvious to one of ordinary skill in the art to have combined Campbell with the conflicting patent, for the purpose of providing memory protection, isolation, and efficiency in multitasking systems, as it uniquely identifies which process a virtual memory entry belongs to, preventing one process from accessing another's memory and reducing TLB flushing overhead when switching contexts. Without an address space indicator, the processor wouldn't know if a cached physical address corresponds to the current running process or a different one, leading to security vulnerabilities and significant performance degradation.
Finally, the conflicting patent claims (e.g., Claim 17) do not expressly require providing, by the interface, the second address and an indication of an address space of the second address to at least one of: a processor, a memory controller, or a direct memory access circuit. However, Mukherjee discloses providing, by the interface, the second address to at least one of: a processor (paragraphs 0003-0004 and 0007; i.e., the processor would receive the output result from merged TLB 110, which is presumably what is shown in Figure 13 considering the inputs and outputs, of whether there is a matching translation entry in the second storage unit), a memory controller, or a direct memory access circuit. Further, Campbell teaches providing an indication of an address space of the second address (Figure 4, item 401, Column 5, lines 3-15; i.e., an address space tag 401 [the claimed “indication of an address space”] is included with the second virtual address 402). It would have been obvious to one of ordinary skill in the art to have combined Mukherjee and Campbell with the conflicting patent, for the reasons provided in the preceding paragraphs.
Instant Claims
Conflicting Patent Claims
1. A device comprising:
an interface that includes:
an input configured to receive a first address;
a memory configured to store an address map; and
an output configured to provide a second address based on the first address and an indication of an address space of the second address, wherein the interface is configured to determine the address space of the second address based on the first address and the address map.
1. A circuit device comprising: a bus master circuit that includes an output configured to provide an address associated with a transaction; a demultiplexer that includes an input coupled to the output of the bus master circuit, a control input coupled to receive an address space value associated with the transaction, and a set of outputs; a multiplexer that includes a set of inputs coupled to the set of outputs of the demultiplexer; an address translation circuit coupled between a first output of the set of outputs of the demultiplexer and a first input of the set of inputs of the multiplexer; a bypass switch coupled between the first output of the set of outputs of the demultiplexer and the first input of the set of inputs of the multiplexer in parallel with the address translation circuit; and a configuration register, wherein the bypass switch is configured to bypass the address translation circuit to provide the address untranslated to the first input of the multiplexer based on a value stored in the configuration register.+ Mukherjee, paragraphs 0124-0125
2. The device of claim 1 wherein:
the interface further includes an address space translator coupled to the input and the output; and
the interface is configured to determine whether to cause the address space translator to translate the first address to produce the second address or whether to cause the first address to be provided as the second address based on the first address and the address map.
1. A circuit device comprising: a bus master circuit that includes an output configured to provide an address associated with a transaction; a demultiplexer that includes an input coupled to the output of the bus master circuit, a control input coupled to receive an address space value associated with the transaction, and a set of outputs; a multiplexer that includes a set of inputs coupled to the set of outputs of the demultiplexer; an address translation circuit coupled between a first output of the set of outputs of the demultiplexer and a first input of the set of inputs of the multiplexer; a bypass switch coupled between the first output of the set of outputs of the demultiplexer and the first input of the set of inputs of the multiplexer in parallel with the address translation circuit; and a configuration register, wherein the bypass switch is configured to bypass the address translation circuit to provide the address untranslated to the first input of the multiplexer based on a value stored in the configuration register.+ Mukherjee, paragraphs 0123 and 0125
3. The device of claim 2, wherein the interface is configured to cause the indication of the address space to have a first value when the address space translator translates the first address to produce the second address and to have a second value when the first address is provided as the second address.
1. A circuit device comprising: a bus master circuit that includes an output configured to provide an address associated with a transaction; a demultiplexer that includes an input coupled to the output of the bus master circuit, a control input coupled to receive an address space value associated with the transaction, and a set of outputs; a multiplexer that includes a set of inputs coupled to the set of outputs of the demultiplexer; an address translation circuit coupled between a first output of the set of outputs of the demultiplexer and a first input of the set of inputs of the multiplexer; a bypass switch coupled between the first output of the set of outputs of the demultiplexer and the first input of the set of inputs of the multiplexer in parallel with the address translation circuit; and a configuration register, wherein the bypass switch is configured to bypass the address translation circuit to provide the address untranslated to the first input of the multiplexer based on a value stored in the configuration register.
4. The device of claim 2, wherein the interface includes a demultiplexer that includes an input coupled to the input of the interface, a first output coupled to the address space translator, and a second output coupled to the output of the interface such that the address space translator is bypassed.
1. A circuit device comprising: a bus master circuit that includes an output configured to provide an address associated with a transaction; a demultiplexer that includes an input coupled to the output of the bus master circuit, a control input coupled to receive an address space value associated with the transaction, and a set of outputs; a multiplexer that includes a set of inputs coupled to the set of outputs of the demultiplexer; an address translation circuit coupled between a first output of the set of outputs of the demultiplexer and a first input of the set of inputs of the multiplexer; a bypass switch coupled between the first output of the set of outputs of the demultiplexer and the first input of the set of inputs of the multiplexer in parallel with the address translation circuit; and a configuration register, wherein the bypass switch is configured to bypass the address translation circuit to provide the address untranslated to the first input of the multiplexer based on a value stored in the configuration register.
5. The device of claim 4, wherein the interface includes a multiplexer that includes a first input coupled to the address space translator, a second input coupled to the second output of the demultiplexer and an output coupled to the output of the interface.
1. A circuit device comprising: a bus master circuit that includes an output configured to provide an address associated with a transaction; a demultiplexer that includes an input coupled to the output of the bus master circuit, a control input coupled to receive an address space value associated with the transaction, and a set of outputs; a multiplexer that includes a set of inputs coupled to the set of outputs of the demultiplexer; an address translation circuit coupled between a first output of the set of outputs of the demultiplexer and a first input of the set of inputs of the multiplexer; a bypass switch coupled between the first output of the set of outputs of the demultiplexer and the first input of the set of inputs of the multiplexer in parallel with the address translation circuit; and a configuration register, wherein the bypass switch is configured to bypass the address translation circuit to provide the address untranslated to the first input of the multiplexer based on a value stored in the configuration register.
6. The device of claim 1, wherein the interface is a Peripheral Component Interconnect Express (PCIe) interface.
6. The circuit device of claim 1, wherein: the multiplexer further includes an output; and the circuit device further comprises a Peripheral Component Interconnect express (PCIe) circuit coupled to the output of the multiplexer.
7. The device of claim 1 further comprising:
a switch array coupled to the output of the interface; and
a destination device coupled to the switch array and configured to receive the second address and the indication of the address space of the second address.
4. The circuit device of claim 1, wherein: the bus master circuit includes an input; and the circuit device further comprises a crossbar [the “switch array”] coupled to the input of the bus master circuit.
8. The device of claim 7, wherein the destination device is from a group consisting of: a direct memory access circuit, a processor, and a memory controller.
5. The circuit device of claim 4 further comprising at least one of: a direct memory access circuit, a processor, or a memory controller coupled to the crossbar.
9. The device of claim 1, wherein:
the input of the interface is configured to receive a first set of data;
the interface is configured to perform a function on the first set of data to produce a second set of data;
the function is based on the address space of the second address; and
the output of the interface is configured to provide the second set of data with the second address and the indication of an address space of the second address.
2. The circuit device of claim 1, wherein: the output of the bus master circuit is a first output; the bus master circuit further includes a second output configured to provide a set of data associated with the transaction; the demultiplexer is a first demultiplexer; the multiplexer is a first multiplexer; and the circuit device further includes: a second demultiplexer that includes an input coupled to the second output of the bus master circuit, a control input coupled to receive the address space value, and a set of outputs; a second multiplexer that includes a set of inputs coupled to the set of outputs of the second demultiplexer; and a data manipulation circuit coupled between a first output of the set of outputs of the second demultiplexer and a first input of the set of inputs of the second multiplexer.
10. The device of claim 9, wherein the function includes at least one of: compression, conversion from big endian mode to little endian mode, or conversion from little endian mode to big endian mode.
3. The circuit device of claim 2, wherein the data manipulation circuit is configured to perform at least one operation on the set of data from a group consisting of: endian reversal and compression.
11. A device comprising:
a processor associated with an address space; and
an interface that includes:
an input configured to receive a first address; and
an output coupled to the processor and configured to provide a second address based on the first address and an indication of whether the second address is associated with the address space of the processor.
9. A device comprising: a Peripheral Component Interconnect express (PCIe) circuit that includes an output configured to provide an address associated with a transaction; a demultiplexer that includes an input coupled to the output of the PCIe circuit, a control input coupled to receive an address space value associated with the transaction, and a set of outputs; a multiplexer that includes a set of inputs coupled to the set of outputs of the demultiplexer; an address translation circuit coupled between a first output of the set of outputs of the demultiplexer and a first input of the set of inputs of the multiplexer; a bypass switch coupled between the first output of the set of outputs of the demultiplexer and the first input of the set of inputs of the multiplexer in parallel with the address translation circuit; and a configuration register, wherein the bypass switch is configured to bypass the address translation circuit to provide the address untranslated to the first input of the multiplexer based on a value stored in the configuration register. + Campbell, Column 5, lines 3-15
12. The device of claim 11, wherein the interface includes an address space translator and is configured to determine whether to:
utilize the address space translator to translate the first address to produce the second address and cause the indication to specify that the second address is associated with the address space of the processor; or
provide the first address as the second address and cause the indication to specify that the second address is not associated with the address space of the processor.
9. A device comprising: a Peripheral Component Interconnect express (PCIe) circuit that includes an output configured to provide an address associated with a transaction; a demultiplexer that includes an input coupled to the output of the PCIe circuit, a control input coupled to receive an address space value associated with the transaction, and a set of outputs; a multiplexer that includes a set of inputs coupled to the set of outputs of the demultiplexer; an address translation circuit coupled between a first output of the set of outputs of the demultiplexer and a first input of the set of inputs of the multiplexer; a bypass switch coupled between the first output of the set of outputs of the demultiplexer and the first input of the set of inputs of the multiplexer in parallel with the address translation circuit; and a configuration register, wherein the bypass switch is configured to bypass the address translation circuit to provide the address untranslated to the first input of the multiplexer based on a value stored in the configuration register. + Campbell, Column 5, lines 3-15
13. The device of claim 12, wherein the interface includes a demultiplexer that includes an input coupled to the input of the interface, a first output coupled to the address space translator, and a second output coupled to the output of the interface such that the address space translator is bypassed.
9. A device comprising: a Peripheral Component Interconnect express (PCIe) circuit that includes an output configured to provide an address associated with a transaction; a demultiplexer that includes an input coupled to the output of the PCIe circuit, a control input coupled to receive an address space value associated with the transaction, and a set of outputs; a multiplexer that includes a set of inputs coupled to the set of outputs of the demultiplexer; an address translation circuit coupled between a first output of the set of outputs of the demultiplexer and a first input of the set of inputs of the multiplexer; a bypass switch coupled between the first output of the set of outputs of the demultiplexer and the first input of the set of inputs of the multiplexer in parallel with the address translation circuit; and a configuration register, wherein the bypass switch is configured to bypass the address translation circuit to provide the address untranslated to the first input of the multiplexer based on a value stored in the configuration register.
14. The device of claim 13, wherein the interface includes a multiplexer that includes a first input coupled to the address space translator, a second input coupled to the second output of the demultiplexer and an output coupled to the output of the interface.
9. A device comprising: a Peripheral Component Interconnect express (PCIe) circuit that includes an output configured to provide an address associated with a transaction; a demultiplexer that includes an input coupled to the output of the PCIe circuit, a control input coupled to receive an address space value associated with the transaction, and a set of outputs; a multiplexer that includes a set of inputs coupled to the set of outputs of the demultiplexer; an address translation circuit coupled between a first output of the set of outputs of the demultiplexer and a first input of the set of inputs of the multiplexer; a bypass switch coupled between the first output of the set of outputs of the demultiplexer and the first input of the set of inputs of the multiplexer in parallel with the address translation circuit; and a configuration register, wherein the bypass switch is configured to bypass the address translation circuit to provide the address untranslated to the first input of the multiplexer based on a value stored in the configuration register.
15. The device of claim 11, wherein the interface is a Peripheral Component Interconnect Express (PCIe) interface.
9. A device comprising: a Peripheral Component Interconnect express (PCIe) circuit that includes an output configured to provide an address associated with a transaction; a demultiplexer that includes an input coupled to the output of the PCIe circuit, a control input coupled to receive an address space value associated with the transaction, and a set of outputs; a multiplexer that includes a set of inputs coupled to the set of outputs of the demultiplexer; an address translation circuit coupled between a first output of the set of outputs of the demultiplexer and a first input of the set of inputs of the multiplexer; a bypass switch coupled between the first output of the set of outputs of the demultiplexer and the first input of the set of inputs of the multiplexer in parallel with the address translation circuit; and a configuration register, wherein the bypass switch is configured to bypass the address translation circuit to provide the address untranslated to the first input of the multiplexer based on a value stored in the configuration register.
16. The device of claim 11 further comprising a memory controller coupled to the output of the interface, wherein the memory controller is associated with the address space.
5. The circuit device of claim 4 further comprising at least one of: a direct memory access circuit, a processor, or a memory controller coupled to the crossbar. + Mukherjee, paragraph 0122
17. A method comprising:
receiving, by an interface, a first address;
determining, by the interface, based on the first address, whether to translate the first address to produce a second address or to provide the first address as the second address; and
providing, by the interface, the second address and an indication of an address space of the second address to at least one of: a processor, a memory controller, or a direct memory access circuit.
13. A method comprising: storing a value in a configuration register; receiving an address associated with a transaction at an input of a demultiplexer; receiving an address space value associated with the transaction at a control input of the demultiplexer; providing the address at a first output of a set of outputs of the demultiplexer based on the address space value; performing an address translation on the address using an address translation circuit coupled to the first output of the demultiplexer to produce a translated address; and determining whether to provide the translated address or to bypass the address translation to provide the address untranslated based on the value stored in the configuration register. + Mukherjee, paragraphs 0003-0004 and 0007 and Campbell, Column 5, lines 3-15
18. The method of claim 17, wherein:
the processor and the memory controller are associated with a first address space; and
the method further comprises:
translating the first address to produce the second address based on the first address space; and
based on the translating, causing the indication to specify that the address space of the second address is the first address space of the processor and the memory controller.
13. A method comprising: storing a value in a configuration register; receiving an address associated with a transaction at an input of a demultiplexer; receiving an address space value associated with the transaction at a control input of the demultiplexer; providing the address at a first output of a set of outputs of the demultiplexer based on the address space value; performing an address translation on the address using an address translation circuit coupled to the first output of the demultiplexer to produce a translated address; and determining whether to provide the translated address or to bypass the address translation to provide the address untranslated based on the value stored in the configuration register. + Campbell, Column 2, lines 25-29, Column 3, lines 1-6, and Column 5, lines 3-15
19. The method of claim 17 further comprising:
translating the first address;
receiving the translated first address at a first input of a multiplexer;
receiving the first address at a second input of the multiplexer; and
providing, via the multiplexer, either the translated first address or the first address as the second address.
13. A method comprising: storing a value in a configuration register; receiving an address associated with a transaction at an input of a demultiplexer; receiving an address space value associated with the transaction at a control input of the demultiplexer; providing the address at a first output of a set of outputs of the demultiplexer based on the address space value; performing an address translation on the address using an address translation circuit coupled to the first output of the demultiplexer to produce a translated address; and determining whether to provide the translated address or to bypass the address translation to provide the address untranslated based on the value stored in the configuration register.
20. The method of claim 17, wherein the interface is a Peripheral Component Interconnect Express (PCIe) interface.
16. The method of claim 14, wherein the transaction is a Peripheral Component Interconnect express (PCIe) transaction.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-16 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1, it is stated in lines 5-6, “an output configured to provide a second address based on the first address and an indication of an address space of the second address”. It is unclear whether this means:
(a) the output is configured to provide (1) a second address based on the first address, and (2) an indication of an address space of the second address; or
(b) the output is configured to provide a second address based on (1) the first address and (2) an indication of an address space of the second address.
The examiner will presume for examination purposes that option (a) is the correct interpretation of the claim.
Regarding Claim 11, it is stated in lines 5-7, “an output coupled to the processor and configured to provide a second address based on the first address and an indication of whether the second address is associated with the address space of the processor”. It is unclear whether this means:
(a) the output is configured to provide (1) a second address based on the first address, and (2) an indication of whether the second address is associated with the address space of the processor; or
(b) the output is configured to provide a second address based on (1) the first address and (2) an indication of whether the second address is associated with the address space of the processor.
The examiner will presume for examination purposes that option (a) is the correct interpretation of the claim.
Claim 18 recites the limitation "wherein the processor and the memory controller are associated with a first address space" in line 2. There is insufficient antecedent basis for this limitation in the claim. More specifically, the claim from which this claim depends (i.e., Claim 17) states “providing, by the interface, the second address and an indication of an address space of the second address to at least one of: a processor, a memory controller, or a direct memory access circuit” (lines 5-7). Accordingly, assuming only a processor is present in Claim 17, the “memory controller” would lack antecedent basis (or vice versa).
Appropriate corrections/clarification is therefore required.
All claims that are not specifically addressed are rejected due to a dependency.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, 11, 12, 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Mukherjee et al. (U.S. Patent Application Publication Number 2015/0089184) and Campbell (U.S. Patent Number 6,385,712).
Regarding Claim 1, Mukherjee discloses a device (Figure 1, item 110) comprising:
an interface (Figure 13, paragraph 0122; i.e., the components shown in Figure 13 are a part of the merged TLB 110 [Figure 1] based on the shown inputs and outputs and interface with the memory controller 108) that includes:
an input configured to receive a first address (Figure 13, “GVA & attributes”, paragraph 0125; i.e., the first address being a guest virtual address [GVA]);
a memory configured to store an address map (paragraph 0125; i.e., upon receiving a GVA, it is determined whether the GVA is mapped to a guest physical address [GPA], or specifies an unmapped address space, which would indicate that a memory storing an address map is present); and
an output configured to provide a second address based on the first address (Figure 13, “GPA”, paragraph 0125; i.e., the guest physical address [GPA] [the “second address”] is output based on the GVA address [translated 1320 or translation-bypassed 1365]), wherein the interface is configured to determine the address space of the second address based on the first address and the address map (paragraphs 0124-0125; i.e., it is determined whether the GVA is mapped to a guest physical address [GPA], or specifies an unmapped address space; therefore, the determination of the address space of the second address is based on the GVA as well as the address map [it may be a mapped or unmapped address space]).
Mukherjee does not expressly disclose the output configured to provide an indication of an address space of the second address.
In the same field of endeavor (e.g., address translation techniques), Campbell teaches the output (Column 3, lines 1-6; i.e., second virtual address is generated based on the first virtual address and is output) configured to provide an indication of an address space of the second address (Figure 4, item 401, Column 5, lines 3-15; i.e., an address space tag 401 [the claimed “indication of an address space”] is included with the second virtual address 402).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Campbell’s teachings of address translation techniques with the teachings of Mukherjee, for the purpose of providing memory protection, isolation, and efficiency in multitasking systems, as it uniquely identifies which process a virtual memory entry belongs to, preventing one process from accessing another's memory and reducing TLB flushing overhead when switching contexts. Without an address space indicator, the processor wouldn't know if a cached physical address corresponds to the current running process or a different one, leading to security vulnerabilities and significant performance degradation.
Regarding Claim 2, Mukherjee discloses wherein the interface further includes an address space translator (Figure 13, item 1320) coupled to the input and the output; and
the interface is configured to determine whether to cause the address space translator to translate the first address to produce the second address or whether to cause the first address to be provided as the second address based on the first address and the address map (paragraph 0123; i.e., the GVA may be translated to generate the GPA, or alternatively the translator 1320 may be bypassed and the GPA could be the same as the GVA [the address mask does not need to be used]; the second address can be determined to bypass the translation based on both the first address [GVA] as well as the address map [see paragraph 0125 - the GVA may be unmapped]).
Regarding Claim 3, Campbell teaches wherein the interface is configured to cause the indication of the address space to have a first value when the address space translator translates the first address to produce the second address (Column 4, lines 42-49; i.e., an emulated address space) and to have a second value when the first address is provided as the second address (Column 4, lines 50-53; i.e., addresses in the address space 301 are not translated; further, the address space tag 401 is used to differentiate between a native address space and emulated address space [Column 5, lines 5-9]).
Regarding Claim 6, Mukherjee does not expressly disclose wherein the interface is a Peripheral Component Interconnect Express (PCIe) interface. The examiner takes Official Notice that the PCI Express standard was well known in the art at the time of the invention and it would have been obvious to one of ordinary skill in the art to have used it for the purpose of providing faster communication mechanism than other interfaces that were known at the time (e.g., 8 GT/s for PCIe Gen 3).
Regarding Claim 11, Mukherjee discloses a device (Figure 1, item 100) comprising:
a processor (paragraph 0003); and
an interface (Figure 13, paragraph 0122; i.e., the components shown in Figure 13 are a part of the merged TLB 110 [Figure 1] based on the shown inputs and outputs and interface with the memory controller 108) that includes:
an input configured to receive a first address (Figure 13, “GVA & attributes”, paragraph 0125; i.e., the first address being a guest virtual address [GVA]); and
an output coupled to the processor (paragraphs 0003-0004 and 0007; i.e., the processor would receive the output result from merged TLB 110, which is presumably what is shown in Figure 13 considering the inputs and outputs, of whether there is a matching translation entry in the second storage unit) and configured to provide a second address based on the first address (Figure 13, “GPA”, paragraph 0125; i.e., the guest physical address [GPA] [the “second address”] is output based on the GVA address [translated 1320 or translation-bypassed 1365]).
Mukherjee does not expressly disclose the processor is associated with an address space;
the output is configured to provide an indication of whether the second address is associated with the address space of the processor.
In the same field of endeavor, Campbell teaches the processor is associated with an address space (Figure 3, item 303, Column 2, lines 25-29; i.e., an address space of a native processor);
the output is configured to provide an indication of whether the second address is associated with the address space of the processor (Figure 4, item 401, Column 5, lines 3-15; i.e., an address space tag 401 is included with the second virtual address 402; this address space tag 401 provides an “indication” of whether the second virtual address 402 is associated with the native processor address space because it differentiates between the address spaces of the various types of processors).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 11.
Regarding Claim 12, Mukherjee discloses wherein the interface includes an address space translator (Figure 13, item 1320) and is configured to determine whether to:
utilize the address space translator to translate the first address to produce the second address or provide the first address as the second address (paragraph 0123; i.e., the GVA may be translated to generate the GPA, or alternatively the translator 1320 may be bypassed and the GPA could be the same as the GVA [the address mask does not need to be used]; the second address can be determined to bypass the translation based on both the first address [GVA] as well as the address map [see paragraph 0125 - the GVA may be unmapped])
Mukherjee does not expressly disclose cause the indication to specify that the second address is associated with the address space of the processor; or
cause the indication to specify that the second address is not associated with the address space of the processor.
In the same field of endeavor, Campbell teaches causing the indication to specify that the second address is associated with the address space of the processor; or causing the indication to specify that the second address is not associated with the address space of the processor (Figure 4, item 401, Column 5, lines 3-15; i.e., an address space tag 401 is included with the second virtual address 402; this address space tag 401 provides an “indication” of whether the second virtual address 402 is associated with the native processor address space because it differentiates between the address spaces of the various types of processors).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 11.
Regarding Claim 15, Mukherjee does not expressly disclose wherein the interface is a Peripheral Component Interconnect Express (PCIe) interface. The examiner takes Official Notice that the PCI Express standard was well known in the art at the time of the invention and it would have been obvious to one of ordinary skill in the art to have used it for the purpose of providing faster communication mechanism than other interfaces that were known at the time (e.g., 8 GT/s for PCIe Gen 3).
Regarding Claim 16, Mukherjee discloses a memory controller (Figure 1, item 108) coupled to the output of the interface, wherein the memory controller is associated with the address space (paragraph 0122; i.e., the memory controller 108 determines whether an address corresponding to particular address space is to be translated or translation-bypassed and is therefore “associated” with the address space).
Regarding Claim 17, Mukherjee discloses a method comprising:
receiving, by an interface (Figure 13, paragraph 0122; i.e., all of the components, which are a part of the merged TLB 110 [Figure 1] based on the shown inputs and outputs, to the right of the unnumbered multiplexer that is located between items 1320 and 1330 are considered to be equivalent to the claimed "interface" because they interface with the memory controller 108), a first address (Figure 13, “GPA”, paragraph 0125; i.e., the first address being a guest physical address [GPA]);
determining, by the interface, based on the first address, whether to translate the first address to produce a second address (Figure 13, item 1330, paragraph 0123; i.e., the root physical address [RPA] being the second address) or to provide the first address as the second address (Figure 13, paragraphs 0123 and 0125; i.e., the root physical address [RPA] [the “second address”] is output based on the GPA address; if the translation 1330 is bypassed, then the RPA can be provided identical to the GPA without any change [even the address masking step can be bypassed]); and
providing, by the interface, the second address to at least one of: a processor (paragraphs 0003-0004 and 0007; i.e., the processor would receive the output result from merged TLB 110, which is presumably what is shown in Figure 13 considering the inputs and outputs, of whether there is a matching translation entry in the second storage unit), a memory controller, or a direct memory access circuit.
Mukherjee does not expressly disclose providing an indication of an address space of the second address.
In the same field of endeavor, Campbell teaches providing an indication of an address space of the second address (Figure 4, item 401, Column 5, lines 3-15; i.e., an address space tag 401 [the claimed “indication of an address space”] is included with the second virtual address 402).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 17.
Regarding Claim 18, Campbell teaches wherein the processor and the memory controller are associated with a first address space (Figure 3, item 303, Column 2, lines 25-29; i.e., an address space of a native processor; note that the examiner had interpreted the claim from which this claim depends to only have the address space of the processor [see also § 112 rejection discussed above with regards to this limitation]); and
the method further comprises:
translating the first address to produce the second address based on the first address space (Column 3, lines 1-6); and
based on the translating, causing the indication to specify that the address space of the second address is the first address space of the processor (Figure 4, item 401, Column 5, lines 3-15; i.e., an address space tag 401 is included with the second virtual address 402; this address space tag 401 provides an “indication” of whether the second virtual address 402 is associated with the native processor address space because it differentiates between the address spaces of the various types of processors) and the memory controller.
Regarding Claim 19, Mukherjee discloses translating the first address (Figure 13, item 1330);
receiving the translated first address at a first input of a multiplexer (Figure 13, see unnumbered multiplexer at output of translator 1330);
receiving the first address at a second input of the multiplexer (Figure 13, item 1366; i.e., the second address can be identical to the first address if the translation 1330 is bypassed); and
providing, via the multiplexer, either the translated first address or the first address as the second address (Figure 13, paragraphs 0123 and 0125; i.e., the root physical address [RPA] [the “second address”] is output based on the GPA address; if the translation 1330 is bypassed, then the RPA can be provided identical to the GPA without any change [even the address masking step can be bypassed]).
Regarding Claim 20, Mukherjee does not expressly disclose wherein the interface is a Peripheral Component Interconnect Express (PCIe) interface. The examiner takes Official Notice that the PCI Express standard was well known in the art at the time of the invention and it would have been obvious to one of ordinary skill in the art to have used it for the purpose of providing faster communication mechanism than other interfaces that were known at the time (e.g., 8 GT/s for PCIe Gen 3).
Claims 4, 5, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Mukherjee and Campbell as applied to claims 2 and 12 above, and further in view of Hammond et al. (U.S. Patent Number 6,219,774).
Regarding Claim 4, Mukherjee and Campbell do not expressly disclose wherein the interface includes a demultiplexer that includes an input coupled to the input of the interface, a first output coupled to the address space translator, and a second output coupled to the output of the interface such that the address space translator is bypassed.
In the same field of endeavor (e.g., address translation techniques), Hammond teaches wherein the interface includes a demultiplexer (Figure 9, item 910) that includes an input (Figure 9, item 737) coupled to the input of the interface (Figure 9, item 203), a first output coupled to the address space translator (Figure 9, item 236), and a second output coupled to the output of the interface such that the address space translator is bypassed (Figure 9, item 246, Column 16, lines 29-58; i.e., the demultiplexer 910 will choose between transmitting the address to the paging unit 236 [equivalent to the claimed “address space translator” because it translates between virtual and physical addresses] and the paging unit 246; if it chooses to transmit the address to the paging unit 246, then it necessarily bypasses the paging unit 236).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Hammond’s teachings of address translation techniques with the teachings of Mukherjee and Campbell, for the purpose of providing a simple mechanism to perform the address bypass mechanism (i.e., as opposed to the more complex bypass determination system used in Mukherjee).
Regarding Claim 5, Hammond teaches wherein the interface includes a multiplexer (Figure 9, item 920) that includes a first input coupled to the address space translator (Figure 9, item 236), a second input coupled to the second output of the demultiplexer (Figure 9, item 246) and an output (Figure 9, item 736) coupled to the output of the interface (Figure 9, item 732).
Regarding Claim 13, Hammond teaches wherein the interface includes a demultiplexer (Figure 9, item 910) that includes an input (Figure 9, item 737) coupled to the input of the interface (Figure 9, item 203), a first output coupled to the address space translator (Figure 9, item 236), and a second output coupled to the output of the interface such that the address space translator is bypassed (Figure 9, item 246, Column 16, lines 29-58; i.e., the demultiplexer 910 will choose between transmitting the address to the paging unit 236 [equivalent to the claimed “address space translator” because it translates between virtual and physical addresses] and the paging unit 246; if it chooses to transmit the address to the paging unit 246, then it necessarily bypasses the paging unit 236).
Regarding Claim 14, Hammond teaches wherein the interface includes a multiplexer (Figure 9, item 920) that includes a first input coupled to the address space translator (Figure 9, item 236), a second input coupled to the second output of the demultiplexer (Figure 9, item 246) and an output (Figure 9, item 736) coupled to the output of the interface (Figure 9, item 732).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Mukherjee and Campbell as applied to claim 1 above, and further in view of Ansari et al. (U.S. Patent Number 8,185,720).
Regarding Claim 7, Campbell discloses a destination device configured to receive the second address and the indication of the address space of the second address (Figure 6, item 603, Column 1, lines 32-37 and Column 5, lines 3-15).
Mukherjee and Campbell do not expressly disclose a switch array coupled to the output of the interface; and
a destination device coupled to the switch array.
In the same field of endeavor (e.g., address translation techniques), Ansari teaches a switch array (Figure 3, item 299) coupled to the output of the interface (Figure 3, items 202-204); and
a destination device coupled to the switch array (Figure 3, item 301, Column 9, lines 36-45).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Ansari’s teachings of address translation techniques with the teachings of Mukherjee and Campbell, for the purpose of allowing plurality devices to receive the second address, thereby increasing the processing capabilities of the system.
Regarding Claim 8, Ansari teaches wherein the destination device is from a group consisting of: a direct memory access circuit, a processor, and a memory controller (Figure 3, item 301).
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Mukherjee and Campbell as applied to claim 1 above, and further in view of Lai (U.S. Patent Application Publication Number 2011/0082999).
Regarding Claim 9, Campbell discloses wherein the input of the interface is configured to receive a first set of data (Column 2, lines 34-37; i.e., a store instruction would include associated data to store in the memory);
the output of the interface is configured to provide the second set of data with the second address and the indication of an address space of the second address (Column 3, lines 44-60; i.e., although the described embodiment is for a load instruction [by which data is read from the memory], in the event a store instruction is transmitted, data associated with the store instruction together with the second address and indication of the second address space [see Column 5, lines 3-15] would be transmitted from the output of the interface).
Mukherjee and Campbell do not expressly disclose the interface is configured to perform a function on the first set of data to produce a second set of data;
the function is based on the address space of the second address.
In the same field of endeavor (e.g., memory access techniques), Lai teaches the interface is configured to perform a function on the first set of data to produce a second set of data (paragraph 0006; i.e., endian conversion [the claimed “function”] may be necessary for the data);
the function is based on the address space of the second address (paragraph 0006).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Lai’s teachings of memory access techniques with the teachings of Mukherjee and Campbell, for the purpose of supporting different types of hardware implementations.
Regarding Claim 10, Lai teaches wherein the function includes at least one of: compression, conversion from big endian mode to little endian mode, or conversion from little endian mode to big endian mode (paragraph 0006).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses a device for determining whether to bypass an address translation.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175