DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Preliminary Amendment
Acknowledgment is made of applicant's Preliminary Amendment, filed 22 November 2024. The changes and remarks disclosed therein were considered.
Claim 1 has been canceled and claim 2-21 are newly added bye preliminary amendment. Therefore, claims 2-21 are pending in the application.
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed on08/05/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
The drawings submitted on 08/05/2024. These drawings are review and accepted by the examiner.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because it uses the phrase “disclosed” in page 1, line 1, which is implied. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 2-21 are reject on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-20 of U.S Patent No. 12,080360 B2 (‘360). Although the conflicting claims are not identical, they are not patentably distinct from each other because the instant application claims are obvious variants of the ‘360 claims.
US Patent No.
US Patent Application No. 2025/0078940 A1
1. A method, comprising: programming a memory cell in a block of NAND memory cell strings, the block including multiple sub-blocks of memory cell strings, wherein the memory cell strings respectively comprise multiple NAND memory cells extending between a source select gate and a drain select gate and sharing a common channel material; wherein the programming of a selected NAND memory cell in a selected NAND memory cell string in a selected sub-block, comprises: during a first interval of a programming operation, precharging channel material of memory cell strings in both the selected sub-block and in at least one unselected sub-block to a precharge voltage, wherein the at least one unselected sub-block does not contain a selected memory cell; and during a second interval of the programming operation, after the first interval, applying a programming voltage to a first access line coupled to the selected memory cell in the selected sub-block, wherein an unselected memory cell in the at least one unselected sub-block is also coupled to the first access line; wherein during the second interval of the programming operation, the channel materials of a group of memory cell strings in the unselected sub-block are charged to a first voltage higher than the precharge voltage by a voltage induced on the channel materials of the group of memory cell strings in the unselected sub-block as a result of the programming voltage on the first access line.
2. The method of claim 1, wherein the multiple memory cell strings within a block collectively form multiple vertically offset levels of memory cells, wherein each level of memory cells in multiple sub-blocks are coupled to a respective common access line.
3. The method of claim 2, wherein multiple memory cells at a respective level within a block of memory cell strings are coupled to a common access line.
4. The method of claim 1, wherein the precharging further comprises enabling respective select gates of multiple memory cell strings in the unselected sub-block to couple the precharge voltage to the channel material of the multiple strings of memory cells in the unselected sub-block.
5. The method of claim 4, wherein the enabled select gates in the unselected sub-block during precharging are the drain select gates of the NAND memory cell strings.
6. The method of claim 4, wherein the enabled select gates in the unselected sub-block during precharging are the source select gates of the NAND memory cell strings.
7. The method of claim 1, further comprising allowing the channel material of the strings of memory cells in the unselected sub-block to float during the second interval of the programming operation.
8. The method of claim 7, wherein allowing the channel material of the string of memory cells in the unselected sub-block to float comprises grounding a select line coupled to a select gate of the string of memory cells in the unselected sub-block.
9. The method of claim 7, further comprising applying a program enable voltage to a data line during the programming operation, wherein the data line is coupled to strings of memory cells in the unselected sub-block and in the selected sub-block.
10. The method of claim 9, wherein applying a program enable voltage to a data line of a selected string comprises coupling the data line to a ground potential.
11. The method of claim 10, further comprising enabling a select gate in the selected string of memory cells to couple the program enable voltage to channel material of the selected memory cell string during the programming operation.
12. A memory structure, comprising: at least one block of NAND memory including multiple sub-blocks of NAND memory cell strings, wherein the NAND memory cell strings respectively comprise multiple NAND memory cells extending between a source select gate and a drain select gate and sharing a common channel material; a memory device controller, comprising control circuitry configured to perform operations on the memory structure, wherein the operations include programming of a first NAND memory cell in a first NAND memory cell string within a first sub-block, including: during a first interval of a programming operation, precharging channel material of memory cell strings in both the first sub-block and at least a second sub-block to a precharge voltage, wherein the second sub-block does not contain a selected memory cell; and during a second interval of the programming operation, after the first interval, applying a programming voltage to a first access line coupled to the first memory cell in the first sub-block, wherein the first access line is further coupled to at least one additional memory cell in the second sub-block; wherein during the second interval of the programming operation, the channel materials of a group of memory cell strings in the second sub-block are charged to a first voltage higher than the precharge voltage in response to a voltage induced on the channel materials as a result of the programming voltage on the first access line.
13. The memory structure of claim 12, wherein the first access line is coupled to multiple memory cells in both the first sub-block and the second sub-block.
14. The memory structure of claim 12, wherein the channel materials of the strings of memory cells in both the first sub-block and the second sub-block are precharged to the precharge voltage during the first interval of the programming operation.
15. The memory structure of claim 14, wherein the channel material of each NAND memory string includes a semiconductor pillar, and wherein the operations further comprise allowing the pillars of NAND memory cell strings in the second sub-block to float during the second interval of the programming operation.
16. The memory structure of claim 15, wherein allowing the pillars of the NAND memory cell strings in the second sub-block to float during the second interval of the programming operation comprises placing respective drain select gates of NAND memory cell strings in the second sub-block in a non-conducting state.
17. The memory structure of claim 16, wherein the operations further comprise, during the second interval of the programing operation, placing the drain select gate of the first memory cell string in a conducting state.
18. A memory device, comprising: a NAND memory array comprising, a block of NAND memory cell strings, comprising, multiple sub-blocks of NAND memory cell strings, each sub-block including multiple strings of NAND memory cells, wherein strings of NAND memory cells extend between an associated source and an associated data line of multiple data lines, wherein the multiple NAND memory cells in a string are arranged at vertically offset levels along a semiconductor pillar; a source select gate between the multiple NAND memory cells of the respective string and the source; a drain select gate between the NAND memory cells and the associated data line; and multiple access lines coupled to multiple memory cells in a respective vertically offset level, wherein a first access line is coupled to multiple memory cells in at least first and second sub-blocks of the block; a memory controller, comprising control circuitry configured to perform operations comprising, performing a programming operation on a selected first memory cell in a first memory cell string in the first sub-block, the programming operation comprising a first portion and a second portion; during the first portion of the programming operation, precharging the semiconductor pillars of multiple strings of memory cells in both the first and second sub-blocks with a precharge voltage, the precharging comprising placing the drain select gates of the memory cell strings of the first and second sub-blocks in a conducting state, and applying a precharge voltage to data lines in both the first and second sub-blocks; wherein the second portion of the programming operation comprises, after precharging the respective semiconductor pillars of the strings of memory cells in the first and second sub-blocks, placing the drain select gates in the second sub-block in a non-conducting state; maintaining an elevated voltage on data lines not coupled to the memory cell string containing the first memory cell; applying a programming voltage to a first access line coupled to the selected memory cell in the first sub-block and also coupled to multiple memory cells in the second sub-block; and while applying the programming voltage to the first access line, placing the drain select gate of the first memory cell string containing the first memory cell in a conductive state.
19. The memory device of claim 18, wherein the first portion of the programming operation further comprises applying a third voltage to the first access line and to multiple additional access lines to establish a conducting condition in the pillars of the memory cells coupled to the first access line and the multiple additional access lines.
20. The memory device of claim 18, wherein the NAND memory cells are charge trap memory cells.
2. A method, comprising: programming a memory cell in a block of NAND memory cell strings, the block including multiple sub-blocks of NAND memory cell strings, wherein the NAND memory cell strings respectively comprise multiple NAND memory cells extending between a source select gate and a drain select gate and sharing a common channel material; wherein the programming comprises: during a first interval: applying a first precharging voltage to the respective channel materials of multiple NAND memory cell strings in a first sub-block containing a memory cell for programming and in at least one additional sub-block which does not contain a memory cell selected for programming; and applying a second voltage to multiple access lines extending across the first sub-block and the at least one additional sub-block, the multiple access lines respectively coupled to multiple respective NAND memory cells in the first sub-block and the additional sub-block, the second voltage causing the NAND memory cells coupled to the access lines to enter a conducting state; and during a second interval, subsequent to applying the first precharge voltage: allowing the channel materials of multiple NAND memory cell strings in the at least one additional sub-block to float, and applying a third programming voltage to multiple NAND memory cells coupled to a first access line, wherein multiple memory cells in the first sub-block and the at least one additional sub-block are also coupled to the first access line; wherein applying of the third programming voltage to the first access line induces a coupled voltage on the floating channel materials of multiple NAND memory cell strings in the at least one additional sub-block, raising the voltage on the channel materials and inhibiting programming of memory cells in the at least one additional sub-block.
3. The method of claim 2, wherein the multiple NAND memory cell strings within a block collectively form multiple vertically offset tiers of NAND memory cells, and wherein access lines within the block of NAND memory strings are coupled to multiple memory cells in a respective tier of NAND memory cells extending across multiple sub-blocks.
4. The method of claim 2, wherein allowing the channel material of the multiple NAND memory cell strings in the at least one additional sub-block to float during the second interval comprises grounding a select line coupled to a select gate of the string of memory cells in the at least one additional sub-block.
5. The method of claim 2, wherein multiple NAND memory cells in the first sub-block are selected for programming.
6. The method of claim 5, further comprising during the second interval, applying a program enable voltage to data lines coupled to strings of NAND memory cells in the first sub-block containing a respective NAND memory cell selected for programming.
7. The method of claim 5, wherein applying a program enable voltage to a data line of a NAND memory cell string comprises coupling the data line to a ground potential.
8. The method of claim 4, further comprising during the second interval, coupling a program enable voltage to channel material of the NAND memory cell string including the NAND memory cell selected for programming by enabling a select gate of that NAND memory cell string.
9. A memory structure, comprising: at least one block of NAND memory including multiple sub-blocks of NAND memory cell strings, wherein the NAND memory cell strings respectively comprise multiple NAND memory cells extending between a source select gate and a drain select gate and sharing a common channel material; a controller configured to cause operations to be performed on the memory structure, wherein the operations include a programming operation, comprising: during a first interval of the programming operation: applying a first precharging voltage to respective channel materials of multiple NAND memory cell strings in a first sub-block containing a NAND memory cell selected for programming and in an additional sub-block, which does not contain a memory cell selected for programming; and applying a second voltage to multiple access lines extending across the first sub-block and the additional sub-block, the multiple access lines respectively coupled to multiple respective NAND memory cells in the first sub-block and the additional sub-block, the second voltage causing channels of the NAND memory cells coupled to the access lines to enter a conducting state; and during a second interval of the programming operation, subsequent to applying the first precharge voltage: allowing the channel materials of NAND memory cell strings in the additional sub-block to float, and applying a third programming voltage to multiple NAND memory cells coupled to a first access line, wherein multiple memory cells in the first sub-block and the at least one additional sub-block are also coupled to the first access line; wherein applying of the third programming voltage to the first access line induces a coupled voltage on the floating channel materials of the multiple NAND memory cell strings in the additional sub-block, raising the voltage on the channel materials and inhibiting programming of memory cells in the additional sub-block.
10. The memory structure of claim 9, wherein the multiple NAND memory cell strings within a block collectively form multiple vertically offset levels of NAND memory cells, and wherein access lines within the block of NAND memory strings are coupled to multiple memory cells in a respective level of NAND memory cells extending across multiple sub-blocks.
11. The memory structure of claim 9, wherein allowing the channel material of the multiple NAND memory cell strings in the additional sub-block to float during the second interval comprises grounding a select line coupled to a select gate of the string of NAND memory cells in the additional sub-block.
12. The memory structure of claim 9, further comprising, during the second interval of the programming operation, reducing voltage on the channel material of the NAND memory cell string containing the selected memory cell to a program enable voltage lower than the precharge voltage.
13. The memory structure of claim 9, further comprising during the second interval of the programming operation, applying a program enable voltage to data lines coupled to strings of NAND memory cells in the first sub-block containing a respective NAND memory cell selected for programming.
14. The memory structure of claim 13, wherein applying a program enable voltage to a data line of a NAND memory cell string comprises coupling the data line to a ground potential.
15. The memory structure of claim 9, further comprising during the second interval of the programming operation, coupling a program enable voltage to channel material of the NAND memory cell string including the NAND memory cell selected for programming by enabling a select gate of that NAND memory cell string.
16. A memory structure, comprising: a block of NAND memory including multiple sub-blocks of NAND memory cell strings, each NAND memory cell string respectively including multiple NAND memory cells sharing a common channel material, and further including a source select gate and a drain select gate at opposite sides of the multiple NAND memory cells of the string; wherein the memory cells of each memory cell string are coupled to respective access lines; wherein each access line is coupled to memory cells in at least two sub-blocks of the block of NAND memory; and wherein each drain select gate is coupled to a first select line, and wherein each source select gate is coupled to a second select line; and a controller configured to cause operations to be performed on the memory structure, wherein the operations include a programming operation, comprising: selecting at least one memory cell in a NAND memory cell string in a first sub-block of the multiple sub-blocks for programming; during an initial part of a programming operation, precharging the channel materials of the NAND memory cell strings of both the first sub-block and an additional sub-block coupled to common access lines with an inlet of the selected sub-block by applying a precharge voltage to the channel material of each NAND memory cell string; and during a subsequent portion of the programming operation, after precharging of the channel material of the NAND memory cell strings of the first sub-block and the additional sub-block: isolating the channel materials of NAND memory cell strings in the additional sub-block, allowing the isolated channel materials of such NAND memory cell strings to float; applying a programming voltage greater than the precharge voltage to a first access line coupled to the selected memory cell in the first sub-block; wherein during the subsequent portion of the programing operation, the channel materials of the NAND memory cell strings in the additional sub-block are charged to a third voltage higher than the precharge voltage by a coupled voltage induced on the channel materials by the programming voltage on the first access line.
17. The memory structure of claim 16, wherein multiple NAND memory cells in the first sub-block are selected for programming.
18. The memory structure of claim 16, further comprising, during the subsequent portion of the programming operation causing voltage on the channel material of the NAND memory cell string containing the selected memory cell to drop to a program enable voltage.
19. The memory structure of claim 18, wherein the program enable voltage is approximately 0 volts.
20. The memory structure of claim 16, wherein the multiple NAND memory cell strings within a block collectively form multiple vertically offset levels of NAND memory cells, and wherein access lines within the block of NAND memory strings are coupled to multiple memory cells in a respective level of NAND memory cells extending across multiple sub-blocks.
21. The memory structure of claim 17, further comprising: during the initial portion of the programming operation, applying a pass voltage to multiple access lines in the first sub-block and the additional sub-block, including the first access line coupled to the selected NAND memory cell; and during the subsequent portion of the programming operation, maintaining the pass voltage on multiple access lines in the first sub-block and the additional sub-block while the programming voltage is applied to the first access line.
Allowable Subject Matter
Claims 2-21 are presently rejected under obviousness double patenting, but would be allowable provided that a terminal disclaimer is filed.
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 02/09/2026