DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the operations of “wherein the plurality of transistors are configured to provide respective signals, and a first signal from an N-th transistor exceeds a threshold voltage of the N-th transistor, and remains at a supply voltage until a second signal from an N+1-th transistor begins to rise” as recited in claim 1; “ wherein the second signal remains at a supply voltage until the first signal rising to the threshold voltage” as recited in claim 11; and “wherein until a first one of the plurality of signals rises to the threshold voltage, a second signal remains at a supply voltage” as recited in claim 19 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
With respect to the drawings it can be seen that the drawings do not provide support for the limitation of wherein the plurality of transistors are configured to provide respective signals, and a first signal from an N-th transistor exceeds a threshold voltage of the N-th transistor, and remains at a supply voltage until a second signal from an N+1-th transistor begins to rise”. This is because it can be seen that Fig. 6 discloses V1 falling below Vdd before V2 rises at T2, V2 falling below Vdd before V3 rises at T1, V3 falling below Vdd before V5 rises at T2 and V5 falling below Vdd before V1 rises at T5. Thus, the drawings fail to disclose the above recited limitation. See Examiner’s Markup below.
Furthermore, the drawings fail to provide support for the limitations of “wherein the second signal remains at a supply voltage until the first signal rising to the threshold voltage” as recited in claim 11 and “wherein until a first one of the plurality of signals rises to the threshold voltage, a second signal remains at a supply voltage” as recited in claim 19. This is because it is shown that V2 falls below Vdd before V1 reaches Vthn at T1. No other waveform of Fig. 6 discloses the above recited limitations of claims 11 and 19.
Examiner’s Markup of Fig. 6 of the instant Application
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Specification
The amendment filed 4/29/2026 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows:
The recitation of “wherein the plurality of transistors are configured to provide respective signals, and a first signal from an N-th transistor exceeds a threshold voltage of the N-th transistor, and remains at a supply voltage until a second signal from an N+1-th transistor begins to rise” of claim 1 is not supported by the original disclosure.
Applicant is required to cancel the new matter in the reply to this Office Action.
For further clarification it is noted that, while not shown in the drawings, support for the limitations of “wherein the second signal remains at a supply voltage until the first signal rising to the threshold voltage” as recited in claim 11 and “wherein until a first one of the plurality of signals rises to the threshold voltage, a second signal remains at a supply voltage” as recited in claim 19 is provided in paragraph 0041 of the originally filed specification.
Claim Rejections - 35 USC § 112
Claims 1-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
With respect to claim 1, the recitation of “wherein the plurality of transistors are configured to provide respective signals, and a first signal from an N-th transistor exceeds a threshold voltage of the N-th transistor, and remains at a supply voltage until a second signal from an N+1-th transistor begins to rise” of claim 1 is not supported by the original disclosure.
Claims 2-10 are rejected for the same reasons as claim 1.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 1, the recitation of “wherein the plurality of transistors are configured to provide respective signals, and a first signal from an N-th transistor exceeds a threshold voltage of the N-th transistor, and remains at a supply voltage until a second signal from an N+1-th transistor begins to rise” cannot be understood, since it is not supported by the original disclosure.
Claims 2-10 are rejected for the same reasons as claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7, 9-16 and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawagoe et al. (USPN 4,015,219).
With respect to claim 1, Kawagoe et al. discloses, as far as can be understood, a circuit (Fig. 6 operational details disclosed in Fig. 7), comprising:
a plurality of current sources (at least any two or more of 12, 14 and 16 in combination with 23) each configured to provide a reference current (each respective current output from 12, 14 and 16 to nodes a, b and c respectively); and
a plurality of transistors each corresponding to a respective one of the plurality of current sources (at least any two or more of sequentially connected 11, 13 and 15) and configured to receive the reference current from the respective current source (at the drains of 11, 13 and 15),
wherein each of the plurality of transistors has a same conductive type (the transistors are the same conductivity types) and includes:
a first source/drain terminal connected to a gate terminal of a first neighboring one of the plurality of transistors (drain of 11 connected to gate of 13 at a, gate of 15 connected to drain of 13 at node b and drain of 15 connected to gate 11 at node c);
a second source/drain terminal connected to ground (sources of 11, 13 and 15 are grounded); and
a gate terminal connected to a source/drain terminal of a second neighboring one of the plurality of transistors (gate terminal of 11 connected to drain of 15, gate terminal of 13 connected to drain of 11 and gate terminal of 15 connected to drain of 13), and
wherein the plurality of transistors are configured to provide respective signals (signal on a, signal on b and signal on c), and a first signal from an N-th transistor exceeds a threshold voltage of the N-th transistor, and remains at a supply voltage until a second signal from an N+1-th transistor begins to rise (as far as can be understood the circuit operates in the same fashion as shown in Applicant’s Fig. 6. For instance, when the signal from 15 on c reaches the threshold of 15/11, e.g., the 15 and 11 have equal thresholds, the output of 15 remains at the high/VGG level until approximately when 11/signal on node a begins to rise at t3/t4. This the similar to V1 of Fig. 6 of Applicant’s invention maintaining Vdd until approximately just before V2 rises at T1, or to when V5 stays at approximately Vdd to when V1 approximately starts to rise at T0. Thus, as far as can be understood the circuits operate in the same fashion. Furthermore, the circuit is connected as claimed and therefore must operate as claimed).
With respect to claim 2, the circuit of claim 1, wherein the plurality of transistors form a loop (oscillating loop of Fig. 6).
With respect to claim 3, the circuit of claim 1, further comprising a plurality of capacitors, wherein each of the plurality of capacitors is connected to the first source/drain terminal of each of the plurality of transistors (17 and 18 when the current sources are selected as 12 and 14 and the plurality of transistors are selected as 11 and 13).
With respect to claim 4, the circuit of claim 3, wherein each of the plurality of signals is a delayed version of each other, wherein a delay constant is associated with a capacitance of a corresponding one of the plurality of capacitors (delay provided by each stage and the capacitance associated with each stage of 12 with 11 and 17 and 14 with 13 and 18).
With respect to claim 5, the circuit of claim 1, wherein each of the plurality of current sources is configured to provide the reference current proportional to a threshold voltage of a corresponding transistor (threshold associated with at least one of 19 and 20).
With respect to claim 6, the circuit of claim 5, wherein each of the plurality of transistors has a same threshold voltage (see Col. 5 lines 26-30).
With respect to claim 7, the circuit of claim 1, wherein a number of the plurality of transistors is a prime number that prevents the signals from the plurality of transistors from being harmonized with each other (when the plurality of transistors is interrupted as all of 11, 13 and 15 the number is prime and the signals are prevented from being harmonized for the purpose of operating as a ring oscillator).
With respect to claim 9, the circuit of claim 1, wherein at least one of the plurality of current sources includes a diode-connected transistor (20 of 23) and reference transistors that have a conductive type the same as the conductive type of a corresponding one of the plurality of transistors (19), wherein the at least one current source is configured to output the reference current based on a threshold voltage of the diode-connected transistor (current through the branch consisting of 21, 19 and 20, or at least one of the currents generated by 12, 14 and 16 which are dependent upon the current/voltage of 23).
With respect to claim 10, the circuit of claim 1, wherein the plurality of transistors are configured to provide oscillating signals without connecting to an inverter (the transistors do not connect to a CMOS inverter that requires both a PMOS and NMOS transistor).
With respect to claim 11, Kawagoe et al. discloses, in Figs. 6 and 7, a circuit, comprising:
a plurality of current sources each configured to provide a reference current (23 with at least two of 12, 14 and 16); and
a plurality of transistors (at least two of 11, 13 and 15) each corresponding to a respective one of the plurality of current sources (11 connected to 12, 13 connected to 14 and 15 connected to 16) and configured to receive the reference current from the respective current source (current from 12, 14 and 16, respectively), wherein each of the plurality of transistors has a same conductive type (the transistors are the same conductivity type), and the reference current is proportional to a threshold voltage of a corresponding one of the plurality of transistors (due to the control of 23 having 19 and 20 which have threshold voltages that control the biasing of 12, 14 and 16. Thus, the outputs of 12, 14 and 16 are proportional to the threshold of at least one of 19 and 20), the plurality of transistors including:
a first transistor (13) configured to provide a first signal (signal on b); and
a second transistor (15) configured to provide a second signal being a delayed version of the first signal (15 providing the output of 15 at node c which is a delayed version of b), wherein the second signal remains at a supply voltage until the first signal rising to the threshold voltage (the circuit on C stays at VGG until the signal on node b reaches the threshold of 15, i.e., the threshold set by 23, to activate 15 to pull node c low causing the signal on node c to fall, see t3 when the voltage on b reach the threshold of 15 and the voltage on node c begins to fall).
With respect to claim 12, the circuit of claim 11, wherein the plurality of transistors form a loop (ring oscillator loop).
With respect toc alim 13, the circuit of claim 11, further comprising a plurality of capacitors connected between the plurality of transistors (17 between 11 and 13, 18 between 13 and 15).
With respect to claim 14, the circuit of claim 13, wherein the second signal is delayed from the first signal by a delay constant associated with a capacitance of the plurality of capacitors (delay provided by the capacitances of 17 and 18 causing the delay/ramping of the signals).
With respect to claim 15, the, circuit of claim 11, wherein each of the plurality of transistors has a same threshold voltage (see Col. 5 lines 26-30).
With respect to claim 16, the circuit of claim 11, wherein a number of the plurality of transistors is a prime number (three when the plurality of transistors is interpreted as 11, 13 and 15).
With respect to claim 18, the circuit of claim 11, wherein at least one of the plurality of current sources includes a diode-connected transistor (20 of 23) and reference transistors that have a conductive type the same as the conductive type of a corresponding one of the plurality of transistors (19), wherein the at least one current source is configured to output the reference current based on a threshold voltage of the diode-connected transistor (current through the branch consisting of 21, 19 and 20, or at least one of the currents generated by 12, 14 and 16 which are dependent upon the current/voltage of 23).
With respect to claim 19, a method, comprising:
providing, by each of a plurality of current sources ( 23 with current output by at least two of 12, 14 and 16), a reference current to a corresponding one of a plurality of transistors having a same conductive type (current to at least two of 11, 13 and 15), wherein the reference current is proportional to a threshold voltage of the corresponding one of the plurality of transistors (according to the threshold of 19 and 20 which has the same threshold as that of 11, 13 and 15. Thus, the currents are proportional to the threshold of the transistors); and
in response to receiving the reference current, providing, by the plurality of transistors, a plurality of signals (at least two of a, b and c), each of which is a delayed version of each other (delay caused by 17, 18 and the threshold voltage of each transistor 11, 13 and 15), wherein until a first one of the plurality of signals rises to the threshold voltage, a second signal remains at a supply voltage (until the signal on node b reaches the threshold of FET 11 the signal on node C remains at the VGG voltage level, see b and c at t3/t4 of Fig. 7)
With respect to claim 20, the method of claim 19, wherein each of the plurality of signals is delayed from each other by a delay constant associated with a capacitor connected to the plurality of transistors (cumulative delay associated with at least one of 17 and 18).
Claim(s) 1, 3-4, 8, 11, 13-14 and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ohta et al. (USPN 7,560,998).
With respect to claim 1, Ohta et al. discloses, as far as can be understood, a circuit (Fig. 1), comprising:
a plurality of current sources (27, 28 and 1a-3a) each configured to provide a reference current (each respective current output from 1a to 3a); and
a plurality of transistors each corresponding to a respective one of the plurality of current sources (1b-3b),
wherein each of the plurality of transistors has a same conductive type (NMOS) and includes:
a first source/drain terminal connected to a gate terminal of a first neighboring one of the plurality of transistors (drain of 1b connected to gate of 2b, drain of 1b connected to gate of 2b and drain of 2b connected to gate 3b);
a second source/drain terminal connected to ground (sources of 1b-3b are grounded); and
a gate terminal connected to a source/drain terminal of a second neighboring one of the plurality of transistors (gate terminal of 1b connected to drain of 3b, gate terminal of 2b connected to drain of 2b and gate terminal of 3b connected to drain of 2b), and
wherein the plurality of transistors are configured to provide respective signals (signal on 1d, signal on 2d and signal on 3d/e), and a first signal from an N-th transistor exceeds a threshold voltage of the N-th transistor, and remains at a supply voltage until a second signal from an N+1-th transistor begins to rise (as far as can be understood the circuit operates in the same fashion as shown in Applicant’s Fig. 6. For instance, when a signal from 3d is above the threshold of 3b. The signal will remain high at the voltage level of 12 provided at node 6 until the signal at 2d starts to substantially starts to rise similar to that of Fig. 6 of Applicant’s invention. Thus, as far as can be understood the circuits operate in the same fashion. Furthermore, the circuit is connected as claimed and therefore must operate as claimed).
With respect to claim 3, the circuit of claim 1, further comprising a plurality of capacitors, wherein each of the plurality of capacitors is connected to the first source/drain terminal of each of the plurality of transistors (1c-3c).
With respect to claim 4, the circuit of claim 3, wherein each of the plurality of signals is a delayed version of each other, wherein a delay constant is associated with a capacitance of a corresponding one of the plurality of capacitors (delay provided by each stage and the capacitance associated with each stage of 1c with 1b, 2c with 2b and 3c with 3c, see equation 4 of Col. 4)
With respect to claim 8, the circuit of claim 1, wherein at least one of the plurality of current sources includes an operational amplifier (24) and a diode-connected transistor (5b), wherein the operational amplifier is configured to output the reference current based on a threshold voltage of the diode-connected transistor (due to the output voltage of 5b provided to 24a and 24a controlling the biasing of 1a-3a, see Col. 10 lines 18-58).
With respect to claim 11, Kawagoe et al. discloses, in Figs. 6 and 7, a circuit, comprising:
a plurality of current sources each configured to provide a reference current (27 and 28 with 1a-3a); and
a plurality of transistors (1b-3b) each corresponding to a respective one of the plurality of current sources (output at the drains of 1a-3a) and configured to receive the reference current from the respective current source (drain currents from each of 1a-3a), wherein each of the plurality of transistors has a same conductive type (the transistors are the same conductivity type, i.e., NMOS), and the reference current is proportional to a threshold voltage of a corresponding one of the plurality of transistors (threshold of 5b which corresponds to the thresholds of 1a-b, see Col. 10 lines 18-58), the plurality of transistors including:
a first transistor (e.g., 2b) configured to provide a first signal (signal on 2d); and
a second transistor (e.g. 3b) configured to provide a second signal being a delayed version of the first signal (signal on 3d which is a delayed version of the signal on 2d), wherein the second signal remains at a supply voltage until the first signal rising to the threshold voltage (the circuit operates as recited since when the signal on 2d is lower than the threshold of 3b, 3b is off such that 3a charges node 3d to the voltage provided by 12 at node 6. Then once the voltage on 2d becomes higher than the threshold of 3b 3b becomes active to discharge node 3d and pulls down 3d away from the power supply voltage of 12 at node 6).
With respect to claim 13, the circuit of claim 11, further comprising a plurality of capacitors connected between the plurality of transistors (1c-3c).
With respect to claim 14, the circuit of claim 13, wherein the second signal is delayed from the first signal by a delay constant associated with a capacitance of the plurality of capacitors (delay provided by the capacitances of 1c-3c causing the delay/ramping of the signals).
With respect to claim 17, the circuit of claim 11, wherein at least one of the plurality of current sources includes an operational amplifier (24) and a diode-connected transistor (5b), wherein the operational amplifier is configured to output the reference current based on a threshold voltage of the diode-connected transistor (via the controls of 1a-5a under the biasing provided by 24. The current is based on the threshold of 5b, see Col. 10 lines 18-58).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
It is further noted that the removal of the previous rejections of claims 1-20 under Tripoli et al. (USPN 10,630,267) and Higuchi et al. (USPAPN 2005/0258911) of the Office Action mailed 3/5/2026 is not intended to indicate that the above references fail to teach the limitations of claims 1-20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Monk et al. (USPN 5,525,938) discloses an oscillator (Fig. 3) that has stages that generate an output signal that stays at the power supply level (0.8v) until the next stage output rises (see NODE 1 to NODE 3 of Fig. 5).
Ogawa et al. (USPN 5,457,429) discloses an oscillator (Fig. 4 within Fig. 6) that has stages (each inverter of Fig. 6 constructed as shown in Fig. 4) that generate an output signal that stays at the power supply level (high level of Va Vb and Vout of Fig. 5) until the next stage output rises (see Vin to Vout of Fig. 5).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2836
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