DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8, 10-17 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tripoli et al. (USPN 10,630,267).
With respect to claim 1, Tripoli et al. discloses, in 4-6 and 8, a circuit (Fig. 5 details of the current generator that generates Iosca-Ioscc disclosed in one of Figs. 4 and 8, details of the reference voltage generator 100 of Fig. 4 disclosed in Fig. 6), comprising:
a plurality of current sources (102, 104/108 and R of Fig. 4 with 110a-110c of Fig. 4; or 112, R, 116, 114, 124/104, 108 and 118 of Fig. 8 with 110a-110c of Fig. 8) each configured to provide a reference current (i.e., the respective drain current of each transistor of 110a-110c, see each respective Iosca to Ioscc. Note the transistors of 106 provided the Iosca-Ioscc currents to transistors 204a-204c of Fig. 5, see Col. 7 line 53 to Col. 8 line 3);
a plurality of transistors (each one of 204a-204c of Fig. 5) each corresponding to a respective on of the plurality of current sources configured to receive the reference current from the respective current source (Iosca provided to 204a; Ioscb provided to 204b; Ioscc provided to 204c),
wherein each of the plurality of transistors has a same conductive type (NMOS) and includes:
a first source/drain terminal (drain terminals of each of 204a-204c) connected to a gate terminal of a first neighboring one of the plurality of transistors (gate terminal connected to each of the subsequent one of 204a-204c, e.g., drain of 204a connected to gate of 204b, drain of 204b connected to gate of 204c, drain of 204c connected to gate of 204a);
a second source/drain terminal connected to ground (ground); and
a gate terminal connected to a source/drain terminal of a second neighboring one of the plurality of transistors (gate terminal of each transistor connected to second neighboring transistor e.g., gate of 204a connected to drain of 204c, gate of 204b connected to drain of 204a, gate of 204c connected to drain of 204b).
With respect to claim 2, the circuit of claim 1, wherein the plurality of transistors form a loop (via the loop from drain of 204c to gate of 204a).
With respect to claim 3, the circuit of claim 1, further comprising a plurality of capacitors, wherein each of the plurality of capacitors is connected to the first source/drain terminal of each of the plurality of transistors (Ca-Cc).
With respect to claim 4, the circuit of claim 3, wherein the plurality of transistors are configured to provide a plurality of signals (output on the drains of each transistor), each of which is a delayed version of each other, wherein a delay constant is associated with a capacitance of a corresponding one of the plurality of capacitors (see Col. 8 lines 61-67).
With respect to claim 5, the circuit of claim 1, wherein each of the plurality of current sources is configured to provide the reference current proportional to a threshold of a corresponding transistor (e.g., each current source provides a current, i.e., each respective drain current, that is proportional to the threshold of the transistor 112 of Fig. 4, i.e., Vth2 which is proportional to the threshold voltage of the transistors of each inverter of 204a-204c, i.e., Vth1, since the thresholds are matched, see Col. 9 lines 33-61, see equation 7 which discloses the devices having the same threshold voltage).
With respect to claim 6, the circuit of claim 5, wherein each of the plurality of transistors has a same threshold (each of the plurality of transistors of each 204, i.e., 204a-204c have the same threshold, see Col. 8 line 61 to Col. 9 line 14. It can be seen that each stage of 204 has the threshold of Vth1. Furthermore, the frequency is equal to 1/(N*D), see equation 4, wherein D is dependent upon the threshold of the stage 204, see equation 3, and N is equal to the number of stages of 204. Thus, according to equation 4 each transistor of each stage of 204a-204c must have the same threshold voltage to provide for the frequency being equal to 1/(N*D)).
With respect to claim 7, the circuit of claim 1, wherein a number of the plurality of transistors is a prime number (3) that prevents signal form the plurality of transistors from being harmonized with each other (the number is prime so it will provide for such functional limitations. Furthermore, the frequency is dependent upon the prime number of stages which will provide for a frequency that is a prime number and thus avoid harmonic interference).
With respect to claim 8, the circuit of claim 1, wherein the at least one of the plurality of current sources includes an operational amplifier (102 of Fig. 4) and a diode-connected transistor (112 of Fig. 6), wherein the operational amplifier is configured to output the reference current (Iref) based on a threshold voltage of the diode-connected transistor (Iref is generated based on Vref, e.g., the gate to source voltage of 112. Furthermore, Vref is generated based on the threshold of 112, see Col. 9 lines 33-45 and Col. 10 line 66 to Col. 11 line 4).
With respect to claim 10, the circuit of claim 1, wherein the plurality of transistors are configured to provide oscillating signals without connecting to an inverter (the oscillator of 2’ of Fig. 5 generates oscillating signals with connected to an inverter, note Fig. 5 is connected in essentially the same fashion as Figs. 2 and 3 of Applicant’s instant invention. Thus, Fig. 5 is not connected to an inverter).
With respect to claim 11, a circuit (Fig. 5 details of the current generator that generates Iosca-Ioscc disclosed in one of Figs. 4 and 8, details of the reference voltage generator 100 of Fig. 4 disclosed in Fig. 6), comprising:
a plurality of current sources (102, 104/108 and R of Fig. 4 with each respective current source of 110a to 110c each generating a respective drain current source of Iosca to Ioscc; or Fig. 8 lest 106 with each respective current source of 110a to 110c each generating a respective drain current source of Iosca to Ioscc) each configured to provide a reference current (each respective drain current of 110a to 110c, see Iosca to Ioscc. Note the transistors of 106 provided the Iosca-Ioscc currents to transistors 204a-204c of Fig. 5, see Col. 7 line 53 to Col. 8 line 3); and
a plurality of transistors (204a-204c of Fig. 5) corresponding to a respective one of the plurality of current sources and each configured to receive the reference current from the respective current source (each respect transistor 110a to 110c supplies a respective current to each 204a to 204c, see Iosca to Ioscc), wherein each of the plurality of transistors has a same conductive type (NMOS), and the reference current is proportional to a threshold voltage of a corresponding one of the plurality of transistors (Iref is equal to Vref/R and Vref is proportional to threshold Vth2, see equation 5 of Col. 9, and Vth2 is equal to the threshold of the transistors of 204a-204c, i.e., Vth1, see Col. 9 lines 55-61. Thus, Iref and/or Iosca-Ioscc is proportional to the threshold of the transistors of 204a-204c), the plurality of transistors including:
a first transistor (204a) configured to provide a first signal (signal on the drain of 204a); and
a second transistor (204b) configured to provide a second signal (signal on the drain of 204b) being a delayed version of the first signal (via the delay associated with each stage, see equation 3 of Col. 8 and equation 9 of Col. 9), wherein the second signal falls in response to the first signal rising to the threshold voltage (the circuit will operate as claimed due to the cascading of the output of 204a to the input of a 204b, also see Col. 8 lines 37-60).
Claims 12-17 are rejected for essentially the same reasons claims 2-5 and 7-8.
With respect to claim 19, a method, (method of operating Fig. 5 and 8) comprising:
providing, by each of a plurality of current sources, a reference current (each respective drain current of 110a to 110c, see Iosca-Ioscc of Figs. 4 and 8) to a corresponding one of a plurality of transistors having a same conductive type (each respective transistor 240a to 204c of Fig. 5 receives a respective drain current of 110a to 110c, see Iosca to Ioscc; each transistor of 204a to 204c being NMOS), wherein the reference current is proportional to a threshold voltage of the corresponding one of the plurality of transistors (Iref is equal to Vref/R and Vref is proportional to threshold Vth2, see equation 5 of Col. 9, and Vth2 is equal to the threshold of the transistors of 204a-204c, i.e., Vth1, see Col. 9 lines 55-61. Thus, Iref and/or Iosca-Ioscc is proportional to the threshold of the transistors of 204a-204c); and
in response to receiving the reference current, providing, by the plurality of transistors, a plurality of signals (each output at the drains of 204a-204c), each of which is a delayed version of each other (via the delay provided by each stage, e.g., see equation 8 of Col. 9), wherein when a first one of the plurality of signals rises to the threshold voltage, a second signal falls (the circuit will operate as claimed due to the cascading of the output of 204a-204c to the input of a subsequent one of 204a-204c, also see Col. 8 lines 37-60).
With respect to claim 20, the method of claim 19, wherein each of the plurality of signals is delayed from each other by a delay constant associated with a capacitor connected to the plurality of transistors (see equation 3 of Col. 8 and equation 8 of Col. 9).
Claim(s) 1, 9, 11 and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Higuchi et al. (USPAPN 2005/0258911).
With respect to claim 1, Higuchi et al. discloses, in Fig. 1, a circuit (10 with 20 of Fig. 1), comprising:
a plurality of current sources (10 with P1 to P2n+1) each configured to provide a reference current (drain current of each P1 to P2n+1); and
a plurality of transistors (N1-N2n+1) each corresponding to a respective one of the plurality of current sources (respective drain current of each P1 to P2n+1) and configured to receive the reference current from the respective current source (via drain current output provided by P1 to P2n+1), wherein each of the plurality of transistors has a same conductive type (NMOS) and includes:
a first source/drain terminal (drain terminals of each of P1 to P2n+1) connected to a gate terminal of a first neighboring one of the plurality of transistors (gate terminal connected to each of the subsequent one of P1 to P2n+1, e.g., drain of N1 connected to gate of N2 and so on);
a second source/drain terminal connected to ground (ground); and
a gate terminal connected to a source/drain terminal of a second neighboring one of the plurality of transistors (gate terminal of each transistor connected to second neighboring transistor e.g., gate of N1 connected to drain of N2n+1, gate of N2 connected to drain of N1 and so on).
With respect to claim 9, the circuit of claim 1, wherein at least one of the plurality of current sources includes a diode-connected transistor (N12) and reference transistors (N10 with N11) that have a conductive type the same as the conductive type of a corresponding one of the plurality of transistors (NMOS), wherein the at least one current source is configured to output the reference current based on a threshold voltage of the diode-connected transistor (10 generates a current that is based on the threshold voltage of N12, see paragraph 0042 and thus each P1 through P2n+1 generates a current based on the threshold of N12).
With respect to claim 11, Higuchi et al. discloses, in Fig. 1, a circuit (10 with 20 of Fig. 1), comprising:
a plurality of current sources (10 with P1 to P2n+1) each configured to provide a reference current (each respective drain current of P1 to P2n+1); and
a plurality of transistors (N1 to N2n+1) each corresponding to a respective one of the plurality of current sources and configured to receive the reference current from the respective current source (via the drain current provided by P1 to P2n+1), wherein each of the plurality of transistors has a same conductive type (NMOS), and the reference current is proportional to a threshold voltage of a corresponding one of the plurality of transistors (N12 is sized to have the same threshold as N1-N2n+1 and generate a current that is proportional to the threshold of the plurality of transistors to provide proper compensation, see paragraphs 0034 and 0042), the plurality of transistors including:
a first transistor (N1) configured to provide a first signal (output of N1); and
a second transistor (N2) configured to provide a second signal being a delayed version of the first signal (output of N2 due to the delay provided by N1/N2), wherein the second signal falls in response to the first signal rising to the threshold voltage (the circuit operates as claimed due to the cascaded connections of the drain of N1 and the gate of N2. It is noted that 10 and 20 of Fig. 1 of Higuchi et al. are connected in essentially the same fashion as 510 and 520 of Applicant’s Fig. 5).
Claim 18 is rejected for the same reasons as claim 9.
Response to Arguments
Applicant's arguments filed 12/08/2025 have been fully considered but they are not persuasive.
The argument that “Tripoli does not disclose or teach “a plurality of current sources each configured to provide a reference current’” is not persuasive. It is clear that both Figs. 4 and 8 include a plurality of current sources (110a to 110c) that each provide a reference current (i.e., each distinct current Iosca to Ioscc). Thus, Tripoli is, in fact, connected as claimed. If one cannot read the drain current/output of a distinct PMOS transistor as “a reference current” and multiple PMOS transistors as “a plurality of current sources”. Then Applicant’s invention would fail to disclose such a limitation. This is because Applicant’s “plurality of current sources” are constructed from multiple PMOS transistors (see 315A to 315N o Fig. 3 of Applicants drawings, as well as the PMOS current sources of 420 and 520 of Figs. 4 and 5 of Applicant’s drawings), wherein the “reference current” provided by each PMOS current source is the drain current of each respective PMOS transistor. Therefore it can be seen that it is reasonable to read a “plurality of current sources” as a plurality of PMOS transistors (such as that of 110a-110c of Tripoli) and the respective reference being drain current of each PMOS transistor (such as Iosca to Ioscc of Tripoli). Thus, Tripoli is connected as claimed.
The argument that “Tripoli discusses, at best, a single current source without showing any ‘plurality of current sources each configured to provide a reference current’” is not persuasive for the reasons discussed above. Tripoli does not merely disclose a single current source as Applicant alleges but rather a plurality of current sources (each 110a-110c) that generate a respect reference current (each respective Iosca to Ioscc). This is similar to Applicant’s PMOS current sources of Figs. 3-5 as discussed above.
The following arguments are not persuasive “Tripoli” “only a single current source (the current source 1) is provided to generate the reference current, and the current mirror 106 mirrors this current for the inverter stage IS of the ring oscillator. Tripoli's current source is simply not “a plurality of current sources each configured to provide a reference current’”.
This is because Applicant ignores the fact the Tripoli clearly shows generating three distinct current (Iosca to Ioscc) output from three distinct current sources (110a-110c), while Iosca to Ioscc may have the same magnitude (i.e., mirror the reference current) that is not to say that each current is the same. Rather, each current, Iosca to Ioscc, is generated by a separate and distinct PMOS transistor (110a to 110c) and thus each current is different current that is generated by a different device. They are not “the same current” as Applicant alleges. At best they are distinct current sources each generating a distinct reference current (Iosca to Ioscc) that have the same magnitude of current level. They are not “the same current”.
Applicant further alleges that Higuchi fails to disclose “a plurality of current source each configured to provide a reference current”, since 11 and 12 “are connected to the ring oscillator 20 to collectively provide a single current that is distributed to all of the inverter stages”. The above alleges are not persuasive, since they are incorrect. As can be seen each distinct PMOS transistor P1 to P2n+1 generates a distinct drain current to each respective transistor of N1 to N2n+1. Thus, each of P1 to P2n+1 are considered the “plurality of currents” and each drain current each P1 to P2n+1 is the provided “reference current” each stage. In no way does P1 to P2n+1 generate a “single current” as Applicant alleges. Rather it is clear that each P1 to P2n+1 generates its own distinctive current in essentially the same fashion as Applicant’s “current sources” of the PMOS transistors of Figs. 3-5 of Applicant’s drawings. Thus, Applicant’s arguments are not persuasive.
Cited Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chiang et al. (USPN 12,323,149) further evidences, in Fig. 3, that a current mirror (211) comprising a plurality of current source transistors (Mp1 to Mp3) that each generate a distinct reference current (Ip1; Ip2; and Ip3).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2849