Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/10/2024,10/04/2024,04/11/2025,09/08/2025,07/01/2026 and 09/04/2026 is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims13-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation "the vertical interconnect" in its body. There is insufficient antecedent basis for this limitation in the claim.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1,3,6,8,10 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1,3,6,8,10 of U.S. Patent No. US 12057373 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the claims in US 12057373 B2 teaches the scope of the claim limitations of application 18/794,693 being examined.
Attached below is a table of the claims rejected under double patenting by the claims of the parent case.
Claim numbering that are anticipated
Instant Application Claims
Conflicting Application/Patent Claims by Olsen et al, (US 12,057,373 B2)
1
1. A method of making a package, comprising: providing a first temporary carrier comprising embedded component mount sites and a plurality of conductive interconnects disposed around the embedded component mount sites; disposing an embedded component over the first temporary carrier, wherein the embedded component comprises through silicon vias (TSVs) extending from a first surface to a second surface opposite the first surface, wherein the embedded component comprises one or more of a package, an active device, a semiconductor die comprising an active surface formed at the first surface, an integrated passive device (IPD), a passive device, and a MEMs device; disposing an encapsulant over the first temporary carrier, around at least five sides of the embedded component, and contacting side surfaces of the embedded component and the conductive interconnects; forming a first interconnect structure over the encapsulant and coupled to first ends of the TSVs at the first surface of the embedded component; providing a second temporary carrier opposite the first temporary carrier and over the first interconnect structure; removing the first temporary carrier; forming a second interconnect structure over and coupled to a second end of the TSVs at the second surface of the embedded component; removing the second temporary carrier; and disposing a component over, and coupling the component to, the first interconnect structure, wherein the component comprises one or more of: a package, a chip, a sensor, an optical device, an antenna, a semiconductor die, system on chip (SOC), memory device, microprocessor, graphics processor, analog device, clock, MEMs, or other semiconductor device.
1. A method of making a package, comprising: providing a first temporary carrier comprising embedded component mount sites and a plurality of conductive interconnects disposed around the embedded component mount sites; disposing an embedded component over the first temporary carrier, wherein the embedded component comprises through silicon vias (TSVs), wherein the embedded component comprises one or more of an active device, a semiconductor die comprising an active surface, an integrated passive device (IPD), a passive device, and a MEMs device; disposing an encapsulant over the first temporary carrier, around at least five sides of the embedded component, and contacting four side surfaces of the embedded component; forming a first build-up interconnect structure over the encapsulant and coupled to first ends of the TSVs; providing a second temporary carrier opposite the first temporary carrier and over the first build-up interconnect structure; removing the first temporary carrier; forming a second build-up interconnect structure over and coupled to a second end of the TSVs; removing the second temporary carrier; and disposing a component, over and coupling the component to, the first build-up interconnect structure, wherein the component comprises a semiconductor die, system on chip (SoC), memory device, microprocessor, graphics processor, analog device, clock, MEMs, or other semiconductor device.
2
3. The method of claim 1, wherein the first interconnect structure is coupled to the first ends of the TSVs with a portion of a conductive RDL layer filling a via hole and without conductive bumps, or coupling the first ends of the TSVs to a portion of a conductive RDL layer with a solder bump.
3. The method of claim 1, wherein the first build-up interconnect structure is coupled to the first ends of the TSVs with a portion of a conductive RDL layer filling a via and without conductive bumps.
3
6. A method of making a package, comprising: providing an embedded component comprising embedded vertical interconnects (EVIs) extending through a base substrate material from a first surface to a second surface opposite the first surface; disposing an encapsulant around at least five sides of the embedded component, the encapsulant contacting four side surfaces of the embedded component; forming a first interconnect structure coupled to a first end of the EVI at the first surface of the embedded component; coupling a second interconnect structure to a second end of the EVI at the second surface of the embedded component; and disposing a component over, and coupling the component to, the first interconnect structure and the EVI, wherein the component comprises one or more of: a package, a chip, a sensor, an optical device, an antenna, a semiconductor die, system on chip (SOC), memory device, microprocessor, graphics processor, analog device, clock, MEMs device, or other semiconductor device.
6. A method of making a semiconductor device comprising: providing an embedded device comprising through silicon vias (TSVs) extending from a first surface to a second surface opposite the first surface, wherein the embedded device comprises an active device, a semiconductor die comprising an active surface formed at the first surface, an integrated passive device (IPD), or a passive device; disposing an encapsulant over at least five sides of the embedded device, the encapsulant contacting four side surfaces of the embedded device; coupling a first electrical interconnect structure to a first end of the TSV at the first surface of the embedded device; coupling a second electrical interconnect structure to a second end of the TSV at the second surface of the embedded device; and disposing a semiconductor die over, and coupling the semiconductor die to, the first electrical interconnect of the TSV, wherein the semiconductor die comprises a system on chip (SoC), memory device, microprocessor, graphics processor, analog device, clock, or other semiconductor device.
4
8. The method of claim 6, further comprising: forming a conductive stud formed at, and directly contacting, the first end of the EVI and a first electrical interconnect structure; and forming a second electrical interconnect structure as an interconnect structure that comprises a portion of a conductive RDL layer filling a via hole through a dielectric to directly contact the second end of the EVI
8. The method of claim 6, further comprising: forming a conductive bump formed at, and directly contacting, the first end of the TSV and the first electrical interconnect structure; and forming the second electrical interconnect structure as a build-up interconnect structure that comprises a portion of a conductive RDL layer filling a via through a dielectric via to directly contact, the second end of the TSV.
5
10. The method of claim 6, further comprising: forming an RDL coupled to the first interconnect structure of the EVI and coupled to the embedded component, wherein the RDL is formed over and directly contacts the encapsulant, and the encapsulant contacts at least five sides of the embedded component.
10. The method of claim 6, further comprising: forming an RDL coupled to the first electrical interconnect of the TSV and coupled to the embedded die, wherein the RDL is formed over and directly contacts the encapsulant, and the encapsulant contacts at least five sides of the embedded device.
Allowable Subject Matter
Claims 2,4-5,7,9 and 11-12 objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
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/MAMADOU L DIALLO/Primary Examiner, Art Unit 2897
Prosecution Insights