DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0295717) and Otremba (US 2015/0092375) in view of Niu (US 2019/0101586).
Regarding claim 1, Yu discloses an inspection apparatus for a warpage of a semiconductor die (paragraph [51], Yu discloses inspecting semiconductor die for determining a level of warpage), comprising:
a carrier (paragraph [53], Yu discloses a carrier 101);
a thermal isolation material (paragraph [41], Yu discloses implementation of molding material 203 for surrounding the semiconductor die, wherein the molding material 203 can be an epoxy, organic polymer with or without silica-based or glass filler, or liquid molding material that is gel-like substance in that molding material 203 can comprise insulating and/or encapsulating materials for isolating heat within the semiconductor die 201, thus thermally insulating and isolating the temperature as needed on the semiconductor die; paragraph [16], Yu discloses the carrier can comprise of thermal isolation material that can comprise of metal, glass, ceramic, silicon or some combination of the aforementioned materials, and that the carrier can have a coefficient of thermal expansion that is tuned to a certain temperature for producing a thermal isolation material; paragraph [18], Yu discloses implementing an adhesive layer 103 to be applied to the carrier 101 in that adhesive layer 103 can be a light to heat conversion film for functioning as a thermal isolation material), disposed over the carrier (paragraph [16], Yu discloses the carrier can comprise of thermal isolation material that can comprise of metal, glass, ceramic, silicon or some combination of the aforementioned materials, and that the carrier can have a coefficient of thermal expansion that is tuned to a certain temperature for producing a thermal isolation material; paragraph [18], Yu discloses implementing an adhesive layer 103 to be applied to the carrier 101 in that adhesive layer 103 can be a light to heat conversion film for functioning as a thermal isolation material).
Yu does not disclose a holding unit, standing on and in contact with the thermal isolation material; a heater, disposed inside the holding unit and being configured to heat the semiconductor die. However, Otremba teaches a holding unit (paragraph [85], Otremba discloses a bonding clip that functions as a metal holder that comprises a heater or heat capacity producer for producing heat to be utilized as a metal holder with a heater inside to heat the semiconductor die, wherein paragraph [82], Otremba discloses dots of solder paste or thermal isolation material is dispensed onto a substrate 102, and then paragraph [84], Otremba discloses dots of solder paste is applied onto substrate 102 and first semiconductor chip 106; paragraph [23], Otremba discloses clip-bonding technology that applies solder paste to the semiconductor chip (ie. die) that permits a proper package resistance and efficient thermal transfer for thermally isolating the heat when bonding semiconductor chips), standing on and in contact with the thermal isolation material (paragraph [85], Otremba discloses a bonding clip that functions as a metal holder that comprises a heater or heat capacity producer for producing heat to be utilized as a metal holder with a heater inside to heat the semiconductor die, wherein paragraph [82], Otremba discloses dots of solder paste or thermal isolation material is dispensed onto a substrate 102, and then paragraph [84], Otremba discloses dots of solder paste is applied onto substrate 102 and first semiconductor chip 106; paragraph [23], Otremba discloses clip-bonding technology that applies solder paste to the semiconductor chip (ie. die) that permits a proper package resistance and efficient thermal transfer for thermally isolating the heat when bonding semiconductor chips); a heater (paragraph [85], Otremba discloses a bonding clip that functions as a metal holder that comprises a heater or heat capacity producer for producing heat to be utilized as a metal holder with a heater inside to heat the semiconductor die, wherein paragraph [82], Otremba discloses dots of solder paste or thermal isolation material is dispensed onto a substrate 102, and then paragraph [84], Otremba discloses dots of solder paste is applied onto substrate 102 and first semiconductor chip 106; paragraph [23], Otremba discloses clip-bonding technology that applies solder paste to the semiconductor chip (ie. die) that permits a proper package resistance and efficient thermal transfer for thermally isolating the heat when bonding semiconductor chips), disposed inside the holding unit and being configured to heat the semiconductor die (paragraph [85], Otremba discloses a bonding clip that functions as a metal holder that comprises a heater or heat capacity producer for producing heat to be utilized as a metal holder with a heater inside to heat the semiconductor die, wherein paragraph [82], Otremba discloses dots of solder paste or thermal isolation material is dispensed onto a substrate 102, and then paragraph [84], Otremba discloses dots of solder paste is applied onto substrate 102 and first semiconductor chip 106; paragraph [23], Otremba discloses clip-bonding technology that applies solder paste to the semiconductor chip (ie. die) that permits a proper package resistance and efficient thermal transfer for thermally isolating the heat when bonding semiconductor chips). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu and Otremba together as a whole for heating the semiconductor die so as to bond semiconductor chips efficiently and effectively during the manufacturing process of electronic components.
Yu and Otremba do not disclose a cover, standing on and in contact with the holding unit, wherein the semiconductor die is disposed between the cover and the heater and distant from the cover.
However, Niu teaches implementing a cover to be placed over the semiconductor die (paragraph [45], fig.1F, Niu discloses carrier substrate 114 functions as a transparent cover that is placed over the semiconductor die 100, wherein paragraph [14], Niu discloses element 100 is a semiconductor die).
Since Otremba discloses a holding unit, standing on and in contact with the thermal isolation material and a heater, disposed inside the holding unit and being configured to heat the semiconductor die, and Niu discloses a cover to be placed over the semiconductor die, therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba and Niu together as a whole for ascertaining the limitation “…a cover, standing on and in contact with the holding unit, wherein the semiconductor die is disposed between the cover and the heater and distant from the cover”, by simple substation of Niu’s cover with the combination of Yu and Otremba, so as to permit a smooth bonding of semiconductor chips to manufacture high quality electronic components in an efficient manner for mass production.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0295717), Otremba (US 2015/0092375) and Niu (US 2019/0101586) in view of Eto (US 2021/0287926).
Regarding claim 2, Otremba discloses the holding unit disposed on the thermal isolation material and extending along with an edge of the thermal isolation material (paragraph [85], Otremba discloses a bonding clip that functions as a metal holder that comprises a heater or heat capacity producer for producing heat to be utilized as a metal holder with a heater inside to heat the semiconductor die, wherein wherein paragraph [82], Otremba discloses dots of solder paste or thermal isolation material is dispensed onto a substrate 102, and then paragraph [84], Otremba discloses dots of solder paste is applied onto substrate 102 and first semiconductor chip 106).
Yu, Otremba and Niu do not disclose wherein the holding unit is in form of a ring disposed on the thermal isolation material and extending along with an edge of the thermal isolation material. However, Eto teaches wherein the holding unit is in form of a ring (paragraph [45], Eto discloses that first heater is provided in the first ring stage in that the first ring stage is a holding unit for holding a heater).
Since Otremba discloses “…the holding unit disposed on the thermal isolation material and extending along with an edge of the thermal isolation material”, and Eto discloses “…the holding unit is in form of a ring”, therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba and Niu together as a whole for ascertaining the limitation “…wherein the holding unit is in form of a ring disposed on the thermal isolation material and extending along with an edge of the thermal isolation material” for permitting the heat to evenly distribute to the thermal isolation material for properly bonding the semiconductor die in order to inspect and manufacture quickly.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0295717), Otremba (US 2015/0092375), Niu (US 2019/0101586) and Eto (US 2021/0287926) in view of Yoshida (US 2017/0190002).
Regarding claim 3, Otremba discloses the holding unit disposed on the thermal isolation material and extending along with an edge of the thermal isolation material (paragraph [85], Otremba discloses a bonding clip that functions as a metal holder that comprises a heater or heat capacity producer for producing heat to be utilized as a metal holder with a heater inside to heat the semiconductor die, wherein wherein paragraph [82], Otremba discloses dots of solder paste or thermal isolation material is dispensed onto a substrate 102, and then paragraph [84], Otremba discloses dots of solder paste is applied onto substrate 102 and first semiconductor chip 106).
Yu, Otremba and Niu does not disclose wherein the holding unit comprises: a ring portion, disposed on the thermal isolation material and extending along with an edge of the thermal isolation material; and a plate portion, disposed on the thermal isolation material and extending along with a main surface of the thermal isolation material, wherein the plate portion is connected to the ring portion.
However, Eto teaches wherein the holding unit comprises a ring portion (paragraph [45], Eto discloses that first heater is provided in the first ring stage in that the first ring stage is a holding unit for holding a heater). Since Otremba discloses “the holding unit disposed on the thermal isolation material and extending along with an edge of the thermal isolation material”, Eto discloses “a ring portion”, therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba, Niu and Eto together as a whole for ascertaining the limitation “…wherein the holding unit comprises: a ring portion, disposed on the thermal isolation material and extending along with an edge of the thermal isolation material” for permitting the heat to evenly distribute to the thermal isolation material for properly bonding the semiconductor die in order to inspect and manufacture quickly.
Yu, Otremba, Niu and Eto do not disclose a plate portion, disposed on the thermal isolation material and extending along with a main surface of the thermal isolation material, wherein the plate portion is connected to the ring portion. However, Yoshida teaches a plate portion (paragraph [63], Yoshida discloses heater plate of heater portion 61). Since Otremba discloses “the holding unit disposed on the thermal isolation material and extending along with an edge of the thermal isolation material”, Eto discloses “a ring portion”, and Yoshida discloses “a plate portion”, therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba, Niu and Eto together as a whole for ascertaining the limitation “…a plate portion, disposed on the thermal isolation material and extending along with a main surface of the thermal isolation material, wherein the plate portion is connected to the ring portion”, by simple substitution, in order to permit quick efficient heating of the semiconductor die so as to bond semiconductor chips for manufacturing electrical parts for constructing electronic appliances.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0295717), Otremba (US 2015/0092375), Niu (US 2019/0101586), Eto (US 2021/0287926) and Yoshida (US 2017/0190002) in view of Thirunavukarasu (US 2018/0144969).
Regarding claim 4, Yu, Otremba, Niu, Eto and Yoshida do not disclose wherein a thickness of the plate portion is less than a thickness of the ring portion. However, Thirunavukarasu teaches wherein a thickness of the plate portion is less than a thickness of the ring portion (paragraph [7], Thirunavukarasu discloses the thickness of carrier plate is less than thickness of carrier ring). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba, Niu, Eto, Yoshida and Thirunavukarasu together as a whole for allowing the flexibility of increasing the capacity of wafer production so as to produce electronic components efficiently (Thirunavukarasu’s paragraph [19]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0295717), Otremba (US 2015/0092375) and Niu (US 2019/0101586) in view of Huang (US 2020/0105548).
Regarding claim 6, Yu, Otremba and Niu do not disclose further comprising: a controller, electrically coupled to the heater and being configured to adjust a heating temperature of the semiconductor die. However, Huang teaches further comprising: a controller (paragraph [20], Huang discloses implementation of a thermal controller for controlling the temperature of the semiconductor wafer (ie. die) for either increasing or decreasing the temperature of the wafer), electrically coupled to the heater and being configured to adjust a heating temperature of the semiconductor die (paragraph [20], Huang discloses implementation of a thermal controller for controlling the temperature of the semiconductor wafer (ie. die) for either increasing or decreasing the temperature of the wafer). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba, Niu, and Huang together as a whole for controlling the temperature of the semiconductor die so as to ensure proper bonding of components for manufacturing electrical appliances.
Claims 7-8, 10 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0295717), Otremba (US 2015/0092375), Niu (US 2019/0101586) and Amanullah (US 2010/0188486) in view of Tosiya (US 2004/0227474).
Regarding claim 7, Yu discloses inspecting the warpage of the semiconductor die (paragraph [51], Yu discloses inspecting semiconductor die for determining a level of warpage).
Yu does not disclose a heater for heating. However, Otremba discloses a heater for heating (paragraph [85], Otremba discloses a bonding clip that functions as a metal holder that comprises a heater or heat capacity producer for producing heat to be utilized as a metal holder with a heater inside to heat the semiconductor die). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu and Otremba together as a whole for heating the semiconductor die so as to bond semiconductor chips efficiently and effectively during the manufacturing process of electronic components.
Yu and Otremba do not disclose a cover. However, Niu discloses a cover (paragraph [45], fig.1F, Niu discloses carrier substrate 114 functions as a transparent cover that is placed over the semiconductor die 100, wherein paragraph [14], Niu discloses element 100 is a semiconductor die). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba and Niu together as a whole for permitting a smooth bonding of semiconductor chips to manufacture high quality electronic components in an efficient manner for mass production.
Yu, Otremba and Niu do not disclose a light source, disposed over the cover and being configured to project a light to the semiconductor die; a capture device, disposed over the cover and being configured to capture an image of the semiconductor die for inspecting the warpage of the semiconductor die after heating; and a controller, electrically coupled to the capture device and being configured to analysis the image of the semiconductor die.
However, Amanullah discloses a light source (paragraph [130], Amanullah discloses utilizing brightfield illumination to obtain illumination pattern of semiconductor wafer); a capture device being configured to capture an image of the semiconductor die for inspecting the warpage of the semiconductor die (paragraph [269], Amanullah discloses capturing images of semiconductor wafer (ie. die); paragraph [220], Amanullah discloses capture images of semiconductor wafer (ie. die) with 3D profile camera, wherein paragraph [224], Amanullah discloses the inspection of a semiconductor wafer (ie. die) to determine a warpage of individual die); and a controller (paragraph [128], Amanullah discloses a CPU or central processing unit for controlling the capture and inspection of image data, and paragraph [92], Amanullah discloses a CPU for processing image information to detect defects present in semiconductor die), electrically coupled to the capture device and being configured to analysis the image of the semiconductor die (paragraph [270], Amanullah discloses performing analysis of 3D images of semiconductor wafer (ie. die), wherein paragraph [128], Amanullah discloses a CPU or central processing unit for controlling the capture and inspection of image data, and paragraph [92], Amanullah discloses a CPU for processing image information to detect defects present in semiconductor die).
Since Otremba discloses a heater for heating, and Amanullah discloses “a capture device being configured to capture an image of the semiconductor die for inspecting the warpage of the semiconductor die”, therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba, Niu and Amanullah together as a whole for ascertaining the limitation “…a capture device, disposed over the cover and being configured to capture an image of the semiconductor die for inspecting the warpage of the semiconductor die after heating” for obtaining images of the semiconductor die to accurately inspect and determine the defects present on the die when manufacturing electronic components.
Yu, Otremba, Niu and Amanullah do not disclose a light source, disposed over the cover and being configured to project a light to the semiconductor die. However, Tosiya teaches a light source being configured to project a light to the semiconductor die (paragraph [68], Tosiya discloses a pattern of light is projected onto a semiconductor wafer (ie. die)). Since Niu discloses the cover, and Tosiya discloses “…a light source being configured to project a light to the semiconductor die”, therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba, Niu, Amanullah and Tosiya together as a whole for ascertaining the limitation “…a light source, disposed over the cover and being configured to project a light to the semiconductor die” in order to permit the semiconductor die to be properly inspected by checking for abnormalities on patterns relative to non-defective semiconductor chips.
Regarding claim 8, Yu discloses an inspection apparatus for a warpage of a semiconductor die (paragraph [51], Yu discloses inspecting semiconductor die for determining a level of warpage), comprising:
a carrier (paragraph [53], Yu discloses a carrier 101);
an insulating material vertically disposed over the carrier (paragraph [41], Yu discloses implementation of molding material 203 for surrounding the semiconductor die, wherein the molding material 203 can be an epoxy, organic polymer with or without silica-based or glass filler, or liquid molding material that is gel-like substance in that molding material 203 can comprise insulating and/or encapsulating materials for isolating and insulating heat within the semiconductor die 201, thus thermally insulating the temperature as needed on the semiconductor die; paragraph [16], Yu discloses the carrier can comprise of thermal isolation material that can comprise of metal, glass, ceramic, silicon or some combination of the aforementioned materials, and that the carrier can have a coefficient of thermal expansion that is tuned to a certain temperature for producing a thermal isolation material; paragraph [18], Yu discloses implementing an adhesive layer 103 to be applied to the carrier 101 in that adhesive layer 103 can be a light to heat conversion film for functioning as a thermal isolation material).
Yu does not disclose a metallic holder, disposed over the carrier; an insulating material, vertically disposed between the carrier and the metallic holder, the insulating material thermally isolating the metallic holder and the carrier; a heater, disposed inside the metallic holder and being configured to heat the semiconductor die. However, Otremba discloses a metallic holder (paragraph [85], Otremba discloses a bonding clip that functions as a metal holder that comprises a heater or heat capacity producer for producing heat to be utilized as a metal holder with a heater inside to heat the semiconductor die, wherein paragraph [82], Otremba discloses dots of solder paste or thermal isolation material is dispensed onto a substrate 102, and then paragraph [84], Otremba discloses dots of solder paste is applied onto substrate 102 and first semiconductor chip 106; paragraph [23], Otremba discloses clip-bonding technology that applies solder paste to the semiconductor chip (ie. die) that permits a proper package resistance and efficient thermal transfer for thermally isolating and insulating the heat when bonding semiconductor chips, and thus providing insulating material for thermally insulating heat as needed); an insulating material vertically disposed with the metallic holder (paragraph [85], Otremba discloses a bonding clip that functions as a metal holder that comprises a heater or heat capacity producer for producing heat to be utilized as a metal holder with a heater inside to heat the semiconductor die, wherein paragraph [82], Otremba discloses dots of solder paste or thermal isolation material is dispensed onto a substrate 102, and then paragraph [84], Otremba discloses dots of solder paste is applied onto substrate 102 and first semiconductor chip 106; paragraph [23], Otremba discloses clip-bonding technology that applies solder paste to the semiconductor chip (ie. die) that permits a proper package resistance and efficient thermal transfer for thermally isolating and insulating the heat when bonding semiconductor chips, and thus providing insulating material for thermally insulating heat as needed), the insulating material thermally isolating the metallic holder (paragraph [85], Otremba discloses a bonding clip that functions as a metal holder that comprises a heater or heat capacity producer for producing heat to be utilized as a metal holder with a heater inside to heat the semiconductor die, wherein paragraph [82], Otremba discloses dots of solder paste or thermal isolation material is dispensed onto a substrate 102, and then paragraph [84], Otremba discloses dots of solder paste is applied onto substrate 102 and first semiconductor chip 106; paragraph [23], Otremba discloses clip-bonding technology that applies solder paste to the semiconductor chip (ie. die) that permits a proper package resistance and efficient thermal transfer for thermally isolating and insulating the heat when bonding semiconductor chips, and thus providing insulating material for thermally insulating heat as needed); a heater (paragraph [85], Otremba discloses a bonding clip that functions as a metal holder that comprises a heater or heat capacity producer for producing heat to be utilized as a metal holder with a heater inside to heat the semiconductor die, wherein paragraph [82], Otremba discloses dots of solder paste or thermal isolation material is dispensed onto a substrate 102, and then paragraph [84], Otremba discloses dots of solder paste is applied onto substrate 102 and first semiconductor chip 106; paragraph [23], Otremba discloses clip-bonding technology that applies solder paste to the semiconductor chip (ie. die) that permits a proper package resistance and efficient thermal transfer for thermally isolating and insulating the heat when bonding semiconductor chips, and thus providing insulating material for thermally insulating heat as needed), disposed inside the metallic holder and being configured to heat the semiconductor die (paragraph [85], Otremba discloses a bonding clip that functions as a metal holder that comprises a heater or heat capacity producer for producing heat to be utilized as a metal holder with a heater inside to heat the semiconductor die, wherein paragraph [82], Otremba discloses dots of solder paste or thermal isolation material is dispensed onto a substrate 102, and then paragraph [84], Otremba discloses dots of solder paste is applied onto substrate 102 and first semiconductor chip 106; paragraph [23], Otremba discloses clip-bonding technology that applies solder paste to the semiconductor chip (ie. die) that permits a proper package resistance and efficient thermal transfer for thermally isolating and insulating the heat when bonding semiconductor chips, and thus providing insulating material for thermally insulating heat as needed).
Since Yu discloses a carrier and an insulating material vertically disposed over the carrier, and Otremba discloses “a metallic holder”, “an insulating material vertically disposed with the metallic holder, the insulating material thermally isolating the metallic holder”, therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu and Otremba together as a whole for ascertaining the limitation “…a metallic holder, disposed over the carrier; an insulating material, vertically disposed between the carrier and the metallic holder, the insulating material thermally isolating the metallic holder and the carrier” for heating the semiconductor die so as to bond semiconductor chips efficiently and effectively during the manufacturing process of electronic components.
Yu and Otremba do not disclose a transparent cover, standing on the metallic holder. However, Niu discloses a transparent cover (paragraph [45], fig.1F, Niu discloses carrier substrate 114 functions as a transparent cover that is placed over the semiconductor die 100, wherein paragraph [14], Niu discloses element 100 is a semiconductor die). Since Otremba discloses the metallic holder, and Niu discloses a transparent cover, therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba and Niu together as a whole for ascertaining the limitation “…a transparent cover, standing on the metallic holder”, by simple insertion of Niu’s cover with the combination of Yu and Otremba, so as to permit a smooth bonding of semiconductor chips to manufacture high quality electronic components in an efficient manner for mass production.
Yu, Otremba and Niu do not disclose an optical capture device, disposed over the transparent cover and being configured to capture an image of the semiconductor die for inspecting the warpage of the semiconductor die.
However, Amanullah teaches an optical capture device being configured to capture an image of the semiconductor die for inspecting the warpage of the semiconductor die (paragraph [269], Amanullah discloses capturing images of semiconductor wafer (ie. die); paragraph [220], Amanullah discloses capture images of semiconductor wafer (ie. die) with 3D profile camera, wherein paragraph [224], Amanullah discloses the inspection of a semiconductor wafer (ie. die) to determine a warpage of individual die). Since Niu discloses a transparent cover, and Amanullah discloses “…an optical capture device being configured to capture an image of the semiconductor die for inspecting the warpage of the semiconductor die”, therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba, Niu and Amanullah together as a whole for ascertaining the limitation “…an optical capture device, disposed over the transparent cover and being configured to capture an image of the semiconductor die for inspecting the warpage of the semiconductor die” in order to obtain images of the semiconductor die to accurately inspect and determine the defects present on the die when manufacturing electronic components.
Yu, Otremba, Niu and Amanullah do not disclose a projector, disposed over the transparent cover and being configured to project a pre-determined pattern of a light on the semiconductor die. However, Tosiya discloses a projector being configured to project a pre-determined pattern of a light on the semiconductor die (paragraph [68], Tosiya discloses a pattern of light is projected onto a semiconductor wafer (ie. die)). Since Niu discloses a transparent cover, and Tosiya discloses “a projector being configured to project a pre-determined pattern of a light on the semiconductor die”, therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba, Niu, Amanullah and Tosiya together as a whole for ascertaining the limitation “…a projector, disposed over the transparent cover and being configured to project a pre-determined pattern of a light on the semiconductor die” in order to permit the semiconductor die to be properly inspected by checking for abnormalities on patterns relative to non-defective semiconductor chips.
Regarding claim 10, Yu does not disclose wherein a material of the metallic holder comprises a metal or a metal alloy. However, Otremba teaches wherein a material of the metallic holder comprises a metal or a metal alloy (paragraph [85], Otremba discloses a bonding clip that functions as a metal holder that comprises a heater or heat capacity producer for producing heat to be utilized as a metal holder with a heater inside to heat the semiconductor die). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu and Otremba together as a whole for heating the semiconductor die so as to bond semiconductor chips efficiently and effectively during the manufacturing process of electronic components.
Regarding claim 13, Yu and Otremba do not disclose wherein the transparent cover comprises a glass cover being configured to be passed through by a visible light. However, Niu teaches wherein the transparent cover comprises a glass cover being configured to be passed through by a visible light (paragraph [45], fig.1F, Niu discloses carrier substrate 114 functions as a transparent cover that is placed over the semiconductor die 100, wherein paragraph [37], Niu discloses carrier substrate 114 is a transparent glass substrate (ie. glass cover) for permitting high visible light transmittance to permit visible light to transmit through element 114). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba and Niu together as a whole for permitting a smooth bonding of semiconductor chips to manufacture high quality electronic components in an efficient manner for mass production.
Regarding claim 14, Yu discloses the pre-determined pattern is a strip pattern or a moire pattern (paragraph [51], Yu discloses the pre-determined pattern is a moire pattern).
Yu, Otremba, Niu and Amanullah do not disclose wherein the projector comprises a light source illustrating a visible light. However, Tosiya teaches wherein the projector comprises a light source illustrating a visible light (paragraph [68], Tosiya discloses the projector’s light source comprises visible light). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba, Niu, Amanullah and Tosiya together as a whole for permitting the semiconductor die to be properly inspected by checking for abnormalities on patterns relative to non-defective semiconductor chips.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0295717), Otremba (US 2015/0092375), Niu (US 2019/0101586), Amanullah (US 2010/0188486) and Tosiya (US 2004/0227474) in view of Rupp (US 2018/0068975).
Regarding claim 9, Yu, Otremba, Niu, Amanullah and Tosiya do not disclose wherein the carrier comprises a carbon carrier. However, Rupp teaches disclose wherein the carrier comprises a carbon carrier (paragraph [131], Rupp discloses implementing carbon carrier for wafer bonding). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba, Niu, Amanullah, Tosiya and Rupp together as a whole for permitting the effective bonding of semiconductor wafers for manufacturing tasks.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0295717), Otremba (US 2015/0092375), Niu (US 2019/0101586), Amanullah (US 2010/0188486) and Tosiya (US 2004/0227474) in view of Kim (US 2013/0037967).
Regarding claim 11, Yu, Otremba, Niu, Amanullah and Tosiya do not disclose wherein a material of the insulating material comprises a heat-resist resin or a heat-isolated ceramic. However, Kim teaches wherein a material of the insulating material comprises a heat-resist resin or a heat-isolated ceramic (paragraph [16], Kim discloses the insulating material is a heat resistant resin). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba, Niu, Amanullah, Tosiya and Kim together as a whole for utilizing heat-resist resin for effectively bonding semiconductor chips at appropriate temperatures in order to prevent loosening of components at high temperatures so as to maintain structural integrity of electronic components.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0295717), Otremba (US 2015/0092375), Niu (US 2019/0101586), Amanullah (US 2010/0188486) and Tosiya (US 2004/0227474) in view of Ma (US 2019/0279887).
Regarding claim 12, Yu, Otremba, Niu, Amanullah and Tosiya do not disclose wherein the heater comprises a ceramic coil heater. However, Ma teaches wherein the heater comprises a ceramic coil heater (paragraph [21], Ma discloses implementing plural heating plates 22, wherein heating plates are ceramic plates with heating coils, thus, Ma discloses a ceramic coil heater). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba, Niu, Amanullah, Tosiya and Ma together as a whole for heating semiconductor chips as needed for inspection and manufacturing tasks.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0295717), Otremba (US 2015/0092375), Niu (US 2019/0101586), Amanullah (US 2010/0188486) and Tosiya (US 2004/0227474) in view of Iida (US 2009/0179317).
Regarding claim 15, Yu discloses an insulating material vertically disposed over the carrier (paragraph [16], Yu discloses the carrier can comprise of thermal isolation material that can comprise of metal, glass, ceramic, silicon or some combination of the aforementioned materials, and that the carrier can have a coefficient of thermal expansion that is tuned to a certain temperature for producing a thermal isolation material; paragraph [18], Yu discloses implementing an adhesive layer 103 to be applied to the carrier 101 in that adhesive layer 103 can be a light to heat conversion film for functioning as a thermal isolation material).
Yu does not disclose a heater. However, Otremba discloses a heater (paragraph [85], Otremba discloses a bonding clip that functions as a metal holder that comprises a heater or heat capacity producer for producing heat to be utilized as a metal holder with a heater inside to heat the semiconductor die). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu and Otremba together as a whole for heating the semiconductor die so as to bond semiconductor chips efficiently and effectively during the manufacturing process of electronic components.
Yu and Otremba do not disclose wherein the semiconductor die is vertically between the heater and the transparent cover. However, Niu discloses the transparent cover (paragraph [45], fig.1F, Niu discloses carrier substrate 114 functions as a transparent cover that is placed over the semiconductor die 100, wherein paragraph [14], Niu discloses element 100 is a semiconductor die). Since Yu discloses “an insulating material vertically disposed over the carrier”, Otremba discloses a heater, and Niu discloses a transparent cover, therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba and Niu together as a whole for ascertaining the limitation “…wherein the semiconductor die is vertically between the heater and the transparent cover”, by simple insertion of Niu’s cover with the combination of Yu and Otremba, so as to permit a smooth bonding of semiconductor chips to manufacture high quality electronic components in an efficient manner for mass production.
Yu, Otremba, Niu, Amanullah and Tosiya do not disclose a distance between the transparent cover and the semiconductor die is greater than zero and is less than or substantially equal to 3 mm. However, Iida discloses a distance between the semiconductor dies is greater than zero and is less than or substantially equal to 3 mm (paragraph [55], Iida discloses setting the distance between the semiconductor dies to be 1 mm to 3 mm, thus disclosing providing a gap or space between the semiconductor dies to be less than or substantially equal to 3 mm). Since Niu discloses a transparent cover, and Iida discloses “a distance between the semiconductor dies is greater than zero and is less than or substantially equal to 3 mm”, therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba, Niu, Amanullah, Tosiya and Iida together as a whole for ascertaining the limitation “a distance between the transparent cover and the semiconductor die is greater than zero and is less than or substantially equal to 3 mm” so as to provide adequate spacing between the cover and the die in order to provide a clear visual image of the semiconductor die when utilizing an image capture process.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0295717), Otremba (US 2015/0092375), Niu (US 2019/0101586), Amanullah (US 2010/0188486), Tosiya (US 2004/0227474) and Yamamoto (US 2016/0378092) in view of Lai (US 2022/0349057).
Regarding claim 16, Yu, Otremba and Niu does not disclose a first controller, electrically coupled to the optical capture device and being configured to analysis the image of the semiconductor die. However Amanullah teaches a first controller (paragraph [128], Amanullah discloses a CPU or central processing unit for controlling the capture and inspection of image data, and paragraph [92], Amanullah discloses a CPU for processing image information to detect defects present in semiconductor die), electrically coupled to the optical capture device (paragraph [269], Amanullah discloses capturing images of semiconductor wafer (ie. die); paragraph [220], Amanullah discloses capture images of semiconductor wafer (ie. die) with 3D profile camera, wherein paragraph [224], Amanullah discloses the inspection of a semiconductor wafer (ie. die) to determine a warpage of individual die) and being configured to analysis the image of the semiconductor die (paragraph [270], Amanullah discloses performing analysis of 3D images of semiconductor wafer (ie. die)). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba, Niu and Amanullah together as a whole for obtaining images of the semiconductor die to accurately inspect and determine the defects present on the die when manufacturing electronic components.
Yu, Otremba, Niu, Amanullah and Tosiya do not disclose a power supply, electrically coupled to the heater and being configured to adjust a heating temperature of the semiconductor die. However, Yamamoto teaches a power supply (paragraph [56], Yamamoto discloses a control apparatus 200 for adjusting the temperature of the semiconductor wafer W that is located on top of electrostatic chuck 6 by controlling the heater power supply 30, the chiller unit 33 and heat transfer gas supply unit for heating or cooling the semiconductor wafer as needed or desired), electrically coupled to the heater and being configured to adjust a heating temperature of the semiconductor die (paragraph [56], Yamamoto discloses a control apparatus 200 for adjusting the temperature of the semiconductor wafer W that is located on top of electrostatic chuck 6 by controlling the heater power supply 30, the chiller unit 33 and heat transfer gas supply unit for heating or cooling the semiconductor wafer as needed or desired). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba, Niu, Amanullah, Tosiya and Yamamoto together as a whole for accurately heating semiconductor chips as needed during manufacturing of electrical components for constructing appliances.
Yu, Otremba, Niu, Amanullah, Tosiya and Yamamoto do not disclose a supporting structure, disposed underneath the carrier and being configured to support the carrier. However, Lai teaches a supporting structure (paragraph [47], fig.4A, Lai discloses support member 500 is located below carrier body 400 in that support member 500 functions as a support structure for supporting the carrier 400), disposed underneath the carrier and being configured to support the carrier (paragraph [47], fig.4A, Lai discloses support member 500 is located below carrier body 400 in that support member 500 functions as a support structure for supporting the carrier 400). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba, Niu, Amanullah, Tosiya, Yamamoto and Lai together as a whole for supporting the carrier to permit the observation, soldering and heating of semiconductor chips for manufacture and inspection tasks.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0295717), Otremba (US 2015/0092375), Niu (US 2019/0101586), Amanullah (US 2010/0188486), Tosiya (US 2004/0227474), Yamamoto (US 2016/0378092) and Lai (US 2022/0349057) in view of Ohkubo (US 2007/0252968).
Regarding claim 17, Yu, Otremba, Niu, Amanullah, Tosiya, Yamamoto and Lai do not disclose a second controller, electrically coupled to the projector and being configured to adjust the pre-determined pattern of the light. However, Ohkubo teaches a controller (paragraph [81], Ohkubo discloses a processor 172 generates information send to adjuster 178 for adjusting the light pattern), electrically coupled to the projector and being configured to adjust the pre-determined pattern of the light (paragraph [81], Ohkubo discloses a processor 172 generates information send to adjuster 178 for adjusting the light pattern). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yu, Otremba, Niu, Amanullah, Tosiya, Yamamoto, Lai and Ohkubo together as a whole for generating light patterns of die for properly evaluating defects of semiconductor die in order to determine appropriateness of components for use in manufacturing appliances.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Amanullah (US 2010/0188486) and Yu (US 2018/0295717) in view of Tosiya (US 2004/0227474).
Regarding claim 18, Amanullah discloses a method of inspecting a warpage of a semiconductor die (paragraph [224], Amanullah discloses the inspection of a semiconductor wafer (ie. die) to determine a warpage of individual die), comprising:
obtaining a light pattern of the semiconductor die (paragraph [131], Amanullah discloses obtaining an illumination pattern of the semiconductor wafer, wherein paragraph [130], Amanullah discloses utilizing brightfield illumination to obtain illumination pattern of semiconductor wafer);
capturing an image of the semiconductor die (paragraph [269], Amanullah discloses capturing images of semiconductor wafer (ie. die); paragraph [220], Amanullah discloses capture images of semiconductor wafer (ie. die) with 3D profile camera);
analyzing the image of the semiconductor die (paragraph [270], Amanullah discloses performing analysis of 3D images of semiconductor wafer (ie. die)); and
determining a warpage of the semiconductor die (paragraph [224], Amanullah discloses the inspection of a semiconductor wafer (ie. die) to determine a warpage of individual die).
Amanullah does not disclose heating the semiconductor die. However, Yu teaches heating the semiconductor die (paragraph [86], Yu discloses heating the semiconductor package, wherein the semiconductor package includes a semiconductor die). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Amanullah and Yu together as a whole for heating the semiconductor die in order to properly inspect the chip for defects.
Amanullah and Yu do not disclose projecting a light having a pattern to the semiconductor die. However, Tosiya teaches projecting a light having a pattern to the semiconductor die (paragraph [68], Tosiya discloses a pattern of light is projected onto a semiconductor wafer (ie. die)). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Amanullah, Yu and Tosiya together as a whole for permitting the semiconductor die to be properly inspected by checking for abnormalities on patterns relative to non-defective semiconductor chips.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Amanullah (US 2010/0188486), Yu (US 2018/0295717), Tosiya (US 2004/0227474) and Otremba (US 2015/0092375) in view of Niu (US 2019/0101586).
Regarding claim 19, Amanullah discloses prior to heating the semiconductor die (paragraph [66], Amanullah discloses the inspection apparatus for performing the inspection of the semiconductor wafer (ie. die), wherein paragraph [224], Amanullah discloses the inspection of a semiconductor wafer (ie. die) to determine a warpage of individual die), further comprising:
placing the semiconductor die into an inspection apparatus (paragraph [66], Amanullah discloses the inspection apparatus for performing the inspection of the semiconductor wafer (ie. die), wherein paragraph [224], Amanullah discloses the inspection of a semiconductor wafer (ie. die) to determine a warpage of individual die), the inspection apparatus comprising:
a light source (paragraph [68], Amanullah discloses brightfield illuminator 26 for performing brightfield illumination, paragraph [131], Amanullah discloses obtaining an illumination pattern of the semiconductor wafer, wherein paragraph [130], Amanullah discloses utilizing brightfield illumination to obtain illumination pattern of semiconductor wafer);
a capture device (paragraph [269], Amanullah discloses capturing images of semiconductor wafer (ie. die); paragraph [220], Amanullah discloses capture images of semiconductor wafer (ie. die) with 3D profile camera);
the image of the semiconductor die is captured by the capture device (paragraph [269], Amanullah discloses capturing images of semiconductor wafer (ie. die); paragraph [220], Amanullah discloses capture images of semiconductor wafer (ie. die) with 3D profile camera).
Amanullah does not disclose the inspection apparatus comprising a carrier, a thermal isolation material disposed over the carrier. However, Yu teaches the inspection apparatus comprising a carrier (paragraph [53], Yu discloses a carrier 101), a thermal isolation material disposed over the carrier (paragraph [16], Yu discloses the carrier can comprise of thermal isolation material that can comprise of metal, glass, ceramic, silicon or some combination of the aforementioned materials, and that the carrier can have a coefficient of thermal expansion that is tuned to a certain temperature for producing a thermal isolation material; paragraph [18], Yu discloses implementing an adhesive layer 103 to be applied to the carrier 101 in that adhesive layer 103 can be a light to heat conversion film for functioning as a thermal isolation material). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Amanullah and Yu together as a whole for heating the semiconductor die in order to properly inspect the chip for defects.
Amanullah and Yu do not disclose the light is projected by the light source. However, Tosiya teaches the light is projected by the light source (paragraph [68], Tosiya discloses a pattern of light is projected onto a semiconductor wafer (ie. die)). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Amanullah, Yu and Tosiya together as a whole for permitting the semiconductor die to be properly inspected by checking for abnormalities on patterns relative to non-defective semiconductor chips.
Amanullah, Yu and Tosiya do not disclose a holding unit standing on and in contact with the thermal isolation material, a heater disposed inside the holding unit. However, Otremba teaches a holding unit standing on and in contact with the thermal isolation material (paragraph [85], Otremba discloses a bonding clip that functions as a metal holder that comprises a heater or heat capacity producer for producing heat to be utilized as a metal holder with a heater inside to heat the semiconductor die, wherein paragraph [82], Otremba discloses dots of solder paste or thermal isolation material is dispensed onto a substrate 102, and then paragraph [84], Otremba discloses dots of solder paste is applied onto substrate 102 and first semiconductor chip 106), a heater disposed inside the holding unit (paragraph [85], Otremba discloses a bonding clip that functions as a metal holder that comprises a heater or heat capacity producer for producing heat to be utilized as a metal holder with a heater inside to heat the semiconductor die). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Amanullah, Yu, Tosiya and Otremba together as a whole for heating the semiconductor die so as to bond semiconductor chips efficiently and effectively during the manufacturing process of electronic components.
Amanullah, Yu, Tosiya and Otremba do not disclose a transparent cover standing on and in contact with the holding unit, a light source disposed over the transparent cover, and a capture device disposed over the transparent cover, wherein: the semiconductor die is placed onto and heated by the heater, and is disposed between the transparent cover and the heater.
However, Niu teaches implementing a transparent cover (paragraph [45], fig.1F, Niu discloses carrier substrate 114 functions as a transparent cover that is placed over the semiconductor die 100, wherein paragraph [14], Niu discloses element 100 is a semiconductor die).
Since Amanullah discloses a light source and a capture device, Yu discloses wherein: the semiconductor die is placed onto and heated by the heater, and Otremba discloses the holding unit, and Niu discloses a transparent cover, therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Amanullah, Yu, Tosiya, Otremba and Niu together as a whole for ascertaining the limitations “…a transparent cover standing on and in contact with the holding unit, a light source disposed over the transparent cover, and a capture device disposed over the transparent cover, wherein: the semiconductor die is placed onto and heated by the heater, and is disposed between the transparent cover and the heater”, by simple substitution of Niu’s transparent cover teaching with the combination of Amanullah, Yu, Tosiya and Otremba, so as to permit a smooth bonding of semiconductor chips to manufacture high quality electronic components in an efficient manner for mass production.
Allowable Subject Matter
Claims 5 and 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
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/ALLEN C WONG/Primary Examiner, Art Unit 2488