DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
“PACKAGE STRUCTURE COMPRISING WINDING AND MANUFACTURING METHOD THEREOF”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 6-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiu (U.S. PG Pub No US2022/0093538A1).
Regarding claim 1, Chiu teaches a package structure (2) fig. 2D [0033, 0042], comprising:
a substrate (20) fig. 2D [0036] (acting as a carrier-substrate) having a first surface (20a) fig. 2D [0039] and a second surface (20b) fig. 2D [0039];
a winding (23) fig. 2D [0040-0041] (23 is coiled/winds around 22 [0040]) disposed on (supported by) the first surface (20a) of the substrate (20), and electrically connected to the substrate (20) (electrically connected to substrate via 200 of substrate 20 [0039]);
a chip (right 21’) fig. 2D [0034, 0037-0039] disposed on (supported by) the first surface (20a) of the substrate (20), and electrically connected to the substrate (20) (electrically connected to substrate via 200 of substrate 20 [0039]);
a component (left 21’) fig. 2D [0037-0039] (chip [0034]) disposed on (supported by) the first surface (20a) of the substrate (20), and electrically connected to the substrate (20) (electrically connected to substrate via 200 of substrate 20 [0039]); and
a magnetic encapsulation layer (comprising 24 with 22) fig. 2D [0040, 0042] (acting to encapsulate [0042]; 24 with 22 encapsulates and includes an at least partially magnetic portion, ferrite material 22 [0040]) disposed (directly) on the first surface (20a) of the substrate (20), and (collectively) encapsulating [0042] the winding (23), the chip (right 21’), and the component (left 21’).
Regarding claim 2, Chiu teaches the package structure (2) fig. 2D [0033, 0042] according to claim 1. Chiu also teaches wherein the first surface (20a) fig. 2D [0039] of the substrate (20) fig. 2D [0036] has a first pad (right 200 surface) fig. 2D [0038-0039] (surface of conductive 200 for connections [0038-0039] acts as pad), a second pad (middle 200) [0038-0039], and a third pad (left 200), the winding (23) fig. 2D [0040-0041] is (electrically) connected [0035, 0039] to the first pad, the chip (right 21’) fig. 2D [0037-0039] is connected (electrically) [0039] to the second pad (middle 200), and the component (left 21’) fig. 2D [0037-0039] is connected (electrically) to the third pad (left 200).
Regarding claim 3, Chiu teaches the package structure (2) fig. 2D [0033, 0042] according to claim 2. Chiu also teaches wherein the winding (23) fig. 2D [0040-0041] and the magnetic encapsulation layer (comprising 22 of 24 with 22) fig. 2D [0040, 0042] form an inductor structure (2a) fig. 2D [0041].
Regarding claim 6, Chiu teaches the package structure (2) fig. 2D [0033, 0042] according to claim 1. Chiu also teaches wherein the winding (23) fig. 2D [0040] (refer also to fig. 2C’ [0040] for top-view of winding/coiling/spiral) has a spiral portion (comprising 23a constituting portion of ‘coil’/spiral shape [0040]) fig. 2D [0040] and a connecting portion (comprising connective/conductive 231 with 23b) fig. 2D [0040] connected [0040] to the spiral portion (23a), the connecting portion (231 with 23b) comprises a vertical portion (231 extending vertically in cross-sectional view) fig. 2D [0040] and a horizontal portion (23b) fig. 2D [0040] (appearing to extend ‘horizontally’ in fig. 2C’ perspective) connected (directly) to each other, and the connecting portion (231 with 23b) is electrically connected to the substrate (20) through the horizontal portion (23b) (conductive 231 and 23b are both electrically connected to respective 200 [0039] of substrate 20 [0039]).
Regarding claim 7, Chiu teaches the package structure (2) fig. 2D [0033, 0042] according to claim 6. Chiu also teaches wherein an outer diameter of the spiral portion (comprising 23a constituting portion of ‘coil’/spiral shape [0040]) fig. 2D [0040] is R, a length of the horizontal portion (23b) fig. 2D [0040] is L, and 1/4R≤L≤R (L is defined as approximately equal to R, based on fig. 2C’ of Chiu below).
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Annotated fig. 2C’ of Chiu
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu (U.S. PG Pub No US2022/0093538A1), as applied in claim 1 above, in view of Lu (U.S. Patent No 9,799,722).
Regarding claim 4, Chiu teaches the package structure (2) fig. 2D [0033, 0042] according to claim 1. Chiu also teaches wherein the winding (23) fig. 2D [0040] (refer also to fig. 2C’ [0040] for top-view of winding/coiling/spiral) has a spiral portion (comprising 23a constituting portion of ‘coil’/spiral shape [0040]) fig. 2D [0040] and a connecting portion (comprising connective/conductive 231 with 23b) fig. 2D [0040] connected [0040] to the spiral portion (23a), the connecting portion (231 with 23b) is electrically connected to the substrate (conductive 231 and 23b are both electrically connected to respective 200 [0039] of substrate 20 [0039]).
However, Chiu does not explicitly disclose and at least one of the chip (right 21’) fig. 2D [0037-0039] and the component (left 21) fig. 2D [0037-0039] is located in a space formed by the spiral portion (23a) (formed aside from 23 / 23a instead).
Lu teaches a package structure [see fig. 5, col 7, lines 64-67; col 8, lines 1-50] (see also fig. 2A top view [col 5, lines 36-67]) comprising at least one of the chip (144) fig. 5 [col 8, lines 1-17] and the component (142) fig. 5 [col 8, lines 1-17] is located in a space (240) [col 8, line 11] (see also fig. 2A [col 5, lines 36-67]) formed by the spiral portion (200 comprising 120 with 112) [col 5, lines 36-67] (‘more than one’ chip/die [col 7, lines 64-67; col 8, lines 1-50] can be disposed in the space 240 surrounded by parts of the inductive spiral 200; see also fig. 2).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the package structure of Chiu such that the spiral-inductor components [col 5, lines 36-67] are expanded across the package to at least partially surround a space hosting a plurality of electronic semiconductor components [col 7, lines 64-67; col 8, lines 1-50] in order to maximize the integration density of the magnetic field generating spiral components relative to the packaging area of chips integrated into the package [col 1, lines 10-32; col 12, lines 18-36], as taught by Lu.
Regarding claim 5, Chiu in view of Lu teaches the package structure (2) fig. 2D [0033, 0042] according to claim 4. Chiu in view of Lu (with reference to Lu) also teaches wherein the chip (144) fig. 5 [col 8, lines 1-17] and the component (142) fig. 5 [col 8, lines 1-17] are both located in the space (240) [col 8, line 11] (see also fig. 2A [col 5, lines 36-67]) formed by the spiral portion (200 comprising 120 with 112) [col 5, lines 36-67] (‘more than one’ chip/die [col 7, lines 64-67; col 8, lines 1-50] can be disposed in the space 240 surrounded by parts of the inductive spiral 200; see also fig. 2).
Claims 8 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu (U.S. PG Pub No US2022/0093538A1) in view of Elian (U.S. PG Pub No US2014/0097514A1).
Regarding claim 8, Chiu teaches a manufacturing method [see figs. 2A-2D, 0033] of a package structure (2) fig. 2D [0033, 0042], comprising:
step S1, providing a substrate (20) fig. 2B [0036] (acting as a carrier-substrate), wherein the substrate (20) has a first surface (20a) fig. 2D [0039] and a second surface (20b) fig. 2D [0039], and the first surface (20a) of the substrate (20) has (hosts) a first pad (right 200 surface) fig. 2D [0038-0039] (surface of conductive 200 for connections [0038-0039] acts as pad), a second pad (middle 200) [0038-0039], and a third pad (left 200);
step S2, providing a winding (23) fig. 2C [0040-0041] (23 is coiled/winds around 22 [0040]), a chip (right 21’) fig. 2B [0034, 0037-0039], and a component (left 21’) fig. 2B [0037-0039] (chip [0034]), connecting (electrically) [0035, 0039] the winding (23) to the first pad (right 200), connecting (electrically) [0039] the chip (right 21’) to the second pad (middle 200), and connecting (electrically) [0039] the component to the third pad (left 200); and
step S3, disposing an insulating material (24) fig. 2D [0042-0043] (acting to encapsulate [0042]) on (supported by) the first surface (20a) of the substrate (20), so that the insulating material (24) encapsulates [0042] the winding (23), the chip (right 21’), and the component (left 21’) to form a magnetic encapsulation layer (24 around 2a) (interpreted as meaning encapsulant of magnetic material(s)/component(s) [0040-0042]).
However, Chiu does not explicitly disclose the insulating material being an insulating magnetic material to form a magnetic encapsulation layer (insulating material [0043] being “magnetic” not specifically disclosed).
Elian teaches a manufacturing method [0038] of a package structure (100) fig. 1A [0038] comprising the insulating material (30) fig. 2B [0017, 0047] being an insulating magnetic material (may be formed of insulating material such as silicon oxide [0017] comprising magnetic particles such as iron [0017]) to form a magnetic encapsulation layer (30) [0017].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of forming the encapsulation layer of Chiu such that the insulating filler material [0017] of the encapsulant is embedded with magnetic particles [0017] so as to render it a magnetic, insulating encapsulation layer [0017, 0019, 0022] in order to improve control of thermal expansion [0017] and magnetic [0017, 0019, 0022] properties of the encapsulant of the inductor [0019-0022], as taught by Elian.
Regarding claim 9, Chiu in view of Elian teaches the manufacturing method [see figs. 2A-2D, 0033] of the package structure (2) fig. 2D [0033, 0042] of claim 8. However, Chiu does not explicitly disclose wherein the step S2 further comprises filling a glue material between the chip (right 21’) fig. 2D [0034, 0037-0039] and the substrate (20) fig. 2D [0036].
Elian teaches a manufacturing method [0038] of a package structure (100) fig. 1A [0038]
wherein step S2 (comprising disposing / fixing chip 10 to substrate carrier 50 [see fig. 2A, 0044]) further comprises filling a glue material [0044] between (in the space between) the chip (right 10) fig. 2A [0044] and the substrate (50) fig. 2A [0044] (glue material, not explicitly shown, may be provided on a surface of carrier substrate 50 [0043-0044] in the space between 50 and chip(s) 10 ‘to fix’ chip 10 to substrate 50 [0044]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of forming the chips of Chiu such that a glue material is provided between the chips and substrate [0043-0044] in order to securely [0044] mechanically fix the chips to the substrate [0044], as taught by Elian.
Regarding claim 11, Chiu in view of Elian teaches the manufacturing method [see figs. 2A-2D, 0033] of the package structure (2) fig. 2D [0033, 0042] of claim 8. Chiu also teaches wherein the winding (23) fig. 2D [0040] (refer also to fig. 2C’ [0040] for top-view of winding/coiling/spiral) has a spiral portion (comprising 23a constituting portion of ‘coil’/spiral shape [0040]) fig. 2D [0040] and a connecting portion (comprising connective/conductive 231 with 23b) fig. 2D [0040] connected [0040] to the spiral portion (23a), the connecting portion (231 with 23b) comprises a vertical portion (231 extending vertically in cross-sectional view) fig. 2D [0040] and a horizontal portion (23b) fig. 2D [0040] (appearing to extend ‘horizontally’ in fig. 2C’ perspective) connected (directly) to each other, and the connecting portion (231 with 23b) is electrically connected [0039-0040] to the first pad (right 200 of 20) through the horizontal portion (23b) (conductive 231 and 23b are both electrically connected to respective pad 200 [0039] of substrate 20 [0039]).
Regarding claim 12, Chiu in view of Elian teaches the manufacturing method [see figs. 2A-2D, 0033] of the package structure (2) fig. 2D [0033, 0042] of claim 11. Chiu also teaches wherein an outer diameter of the spiral portion (comprising 23a constituting portion of ‘coil’/spiral shape [0040]) fig. 2D [0040] is R, a length of the horizontal portion (23b) fig. 2D [0040] is L, and 1/4R≤L≤R (L is defined as approximately equal to R, based on fig. 2C’ of Chiu below).
[AltContent: textbox (L; approximate horizontal length of 23B in fig. 2C’ view, spans spiral shape )][AltContent: arrow][AltContent: textbox (R; diameter of spiral defined, in part, by 23A. Outer diameter spanning spiral approximated by this line )][AltContent: arrow][AltContent: connector][AltContent: connector]
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Annotated fig. 2C’ of Chiu
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chiu (U.S. PG Pub No US2022/0093538A1) modified by Elian (U.S. PG Pub No US2014/0097514A1), as applied in claim 8 above, and further in view of Lu (U.S. Patent No 9,799,722).
Regarding claim 10, Chiu in view of Elian teaches the manufacturing method [see figs. 2A-2D, 0033] of the package structure (2) fig. 2D [0033, 0042] of claim 8. Chiu also teaches wherein the winding (23) fig. 2D [0040] (refer also to fig. 2C’ [0040] for top-view of winding/coiling/spiral) has a spiral portion (comprising 23a constituting portion of ‘coil’/spiral shape [0040]) fig. 2D [0040] and a connecting portion (comprising connective/conductive 231 with 23b) fig. 2D [0040] connected [0040] to the spiral portion (23a), the connecting portion (231 with 23b) is electrically connected [0039-0040] to the first pad (right 200 of 20) (conductive 231 and 23b are both electrically connected to respective 200 [0039] of substrate 20 [0039]).
However, Chiu does not explicitly disclose and at least one of the chip (right 21’) fig. 2D [0037-0039] and the component (left 21) fig. 2D [0037-0039] is located in a space formed by the spiral portion (23a) (formed aside from 23 / 23a instead).
Lu teaches a method of forming a package structure [see fig. 5, col 7, lines 64-67; col 8, lines 1-50] (see also fig. 2A top view [col 5, lines 36-67]) comprising at least one of the chip (144) fig. 5 [col 8, lines 1-17] and the component (142) fig. 5 [col 8, lines 1-17] is located in a space (240) [col 8, line 11] (see also fig. 2A [col 5, lines 36-67]) formed by the spiral portion (200 comprising 120 with 112) [col 5, lines 36-67] (‘more than one’ chip/die [col 7, lines 64-67; col 8, lines 1-50] (be disposed in the space 240 surrounded by parts of the inductive spiral 200; see also fig. 2).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of forming the package structure of Chiu such that the spiral-inductor components [col 5, lines 36-67] are expanded across the package to at least partially surround a space hosting a plurality of electronic semiconductor components [col 7, lines 64-67; col 8, lines 1-50] in order to maximize the integration density of the magnetic field generating spiral components relative to the packaging area of chips integrated into the package [col 1, lines 10-32; col 12, lines 18-36], as taught by Lu.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are considered relevant because they all feature structures applicable to the encapsulation of inductor winding and electronic chip components on a substrate.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 08/07/2026
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