Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/04/2025, 01/28/2025, and 08/05/2024 were being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 3, 7 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thacker et al (US Pub. No. 2014/0321803 A1) in view of Raj et al. (US Pub. No. 2013/0230272 A1).
With regards to claims 1, Thacker teaches a package-level architecture including integrated circuit 110-1, optical integrated circuit 128-1, optionally I/O integrated circuit 134-1, interposer 118, and substrate 136, all arranged in one compact package. Thacker also teaches hat the optional I/O integrated circuit can serialize/deserialize data and include photonic driver/receiver circuits, that optical fiber 156 can be directly edge or vertically couple, and that ramp-stack memory package 910 can be include for package level memory expansion [0047]-[0054],[0059]-[0066], (Figures 1,6,9-10).
Thacker fails to expressly disclose that the transceiver direct drives a channel driver in the optical engine through the substrate through an embed interconnection in the substate.
Ray teaches a substrate 210 with opposite surfaces, connectors 214-1/214-2, interconnectors 216 through the substate and a short lateral region 204 of a most 1mm for high-speed communication. Ray also teaches a conversion mechanism 220a adjacent the opposite surface, where optically I/O ports include sources, detectors and associated receiver such as a transimpedance amplifiers and limiting amplifier with serial serializer/deserializer I/O blocks posited close to the integrated circuit side [0030]-[0034],[0037]-[0044], (Figures 2-6)
In view of the utility, to reduce the highest speed path length, lower parasitics and power and improve signal integrity above 10 Gbps, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Thacker to include the teachings such as that taught by Ray.
With regards to claim 2, Thacker discloses the optical engine is coupled to an external optical cable (i.e., optical fiber 156) configured to mate directly with the integrated circuit package (notice the optical fiber vertically coupled to the optical integrated circuit 128-1) [0054] – [0058] (Figures 1-4).
With regards to claim 3, Thacker discloses the transceiver, i.e., see optional I/O integrated circuit 134-1 is separate die between integrated circuit 110-1 and the optical integrated circuit 128-1 [0048] (Figure 1).
With regards to claim 7, Thacker discloses the claimed limitation according to claim 1, but fails to expressly disclose the transceiver and the channel of the optical engine is connected through an interconnection embedded in the substrate.
Ray teaches the interconnector 216 through substate 210, including short later region 204 embedded in / through the substrate structure [0030] - [0033], figures 2 and 6).
In view of the utility, to reduce the highest speed path length, lower parasitics and power and improve signal integrity above 10 Gbps, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Thacker to include the teachings such as that taught by Ray.
With regards to claim 9, Thacker discloses additional memory formed on a fifth die, wherein the additional memory is communicatively coupled to the processing circuitry and configured to store data accessible by the processing circuitry [0064] – [0066], (Figure 9 – 10). Thacker already discloses multiple memory chips in the same package and points to those die packages to duplicate but fails to teach or doesn’t expressly explicitly say “die”, nonetheless adding one more memory die, especially when it’s been stated that most of the rest of the parts were being duplicated, than duplicating dies are considered only routine skill and generally scaling. The court to has held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to duplicate dies the dies in addition to all the other elements that were pointed out, since it has been held that a mere duplication of working parts of a device involves only routine skill in the art. One would have been motivated to duplicate the dies for the purpose of adding more capabilities, improve yield, advance packaging at the least.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thacker et al (US Pub. No. 2014/0321803 A1) and Raj et al. (US Pub. No. 2013/0230272 A1) in view of Sefidvash et al. (US Pub. No. 2007/0258551).
With regards to claim 4, Thacker discloses the claimed invention according to claim 1, and further teaches about the packaging shell and the transceiver-side intermediary [0048], but fails to expressly disclose the transceiver comprising a transceiver physical-layer circuit that directly drives the channel.
Sefidvash teaches PHY blocking partitioning including serializer/deserializer and PMD circuity and basic package connection to optical side channel driver/receiver structures [0032]-[0035],[0037]-[0040].
In view of the utility, to expand modes and capabilities of the circuits, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Thacker to include the teachings such as that taught by Sefidvash.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thacker et al (US Pub. No. 2014/0321803 A1), Raj et al. (US Pub. No. 2013/0230272 A1) and Sefidvash et al. (US Pub. No. 2007/0258551) in view of Wu et al. (US Publication 2005/0105574 A1).
With regards to claim 5, Thacker discloses the claimed invention according to claim 1, and further teaches the package architecture with integrated circuit 110-1, optical I/O integrated circuit 134-1 and optical integrated circuit 128-1 on the same side of interpose 118, in addition to other elements but more importantly, Thacker fails to expressly disclose that the transceiver physical-layer circuit comprise a serializer that directly drives the channel driver of the optical engine; and a deserializer that directly receives signals from a transimpedance amplifier and limiting amplifier block in the optical engine.
Wu relates to optical communication (Abstract). Wu teaches, referring to FIG. 7, a network interface, according to one embodiment of the present invention, includes a media access control 70 coupled to an encoder/decoder 60 and a serializer/deserializer 50 in one embodiment. The serializer/deserializer 50 may be coupled, on the transmitter side, to the laser driver 10, which may be any of the embodiments illustrated herein. The driver 10 in turn is coupled to the transmitting laser diode 36 [0024].
Raj teaches optical chip assembly and the flexibility of how to configure or nr creative with packages [0037] – [0042].
On the receiver side, the receiving photo diode 37 is coupled to a limiting amplifier/transimpedance amplifier 40, which in turn may be coupled to the serializer/deserializer 50 [0025].
On the transmitter side, digital data may be provided from the media access control module 70 to the encoding/decoding module 60, where the digital data may be encoded into a format that is advantageous for conversion into optical signals. If the digital data is already in the proper form, processing by the encoder/decoder 60 may be unnecessary. Sometimes, the encoded digital data needs to be serialized or deserialized. In such case, the encoded digital data may be fed to the serializer/deserializer 50. The output from the serializer/deserializer 50 may be fed to the laser driver 10 that may drive the laser diode 36 as described previously. Optical energy may be created and optical signals may be provided from the interface to a fiber optic line (not shown) in one embodiment of the present invention [0026].
In view of the utility, to expand modes and capabilities of the circuits, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Thacker to include the teachings such as that taught by Raj and Wu
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thacker et al (US Pub. No. 2014/0321803 A1), Raj et al. (US Pub. No. 2013/0230272 A1) and Shubin et al. (US Pub. No. 2017/0199328 A1).
With regards to claim 6, Thacker fails to expressly disclose comprising an additional optical engine mounted on top of the transceiver.
Shubin teaches a multi-chip module (MCM) is described. This MCM includes a driver integrated circuit that includes electrical circuits, a photonic chip, an interposer, and an optical gain chip. The photonic chip may be implemented using a silicon-on-insulator technology, and may being aligned relative to a top surface of the elements (Abstract). The MCM described herein may integrate three types of chips into a single functional, hybrid-integrated photonic module or transceiver with internally generated laser light (and, more generally, an optical signal) [0040].
In view of the utility, to expand modes and capabilities of the packages, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Thacker to include the teachings such as that taught by Shubin.
Claim(s) 8 and 10 - 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thacker et al (US Pub. No. 2014/0321803 A1) and of Raj et al. (US Pub. No. 2013/0230272 A1) in view of Nagarjan (US Pub. No. 2016/0080090 A1).
With regards to claim 8, Thacker teaches photonic-modulator driver signaling, in addition to, implicitly directing in an analog optical front-end character by including silicon-photonics drive interface art used in the configuration and/or the system, for example, a silicon-photonics driver interface. Thacker teaches that alternatively, optical interconnects or links based on silicon photonics are attractive candidates for interconnect technology because they can be readily scaled on optical integrated circuits [0008] [0044].
Nafarajan relates to telecommunication techniques including integrated electrical optics multiple chip module and methods. Nafarajan makes explicit that which Nafarajan makes implicit by teaching an example, wherein a device with a driver interface provides on a substrate member coupled to the driver module and configured to be coupled to a silicon photonics device. A control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device [0068], [0085].
In view of the utility, to provide an integrated electrical optics multiple chip module and methods, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Thacker to include the teachings such as that taught by Ray.
With regards to claim 10, the method mirrors the device claims 1 and 8, as such, see the rejections of claims 1 and 8.
With regards to claim 11, see the rejections of claims 1, 2 and 8.
With regards to claim 12, see the rejection of claims 1, 4 and 11.
With regards to claim 13, see the rejections of claims 1, 5 and 11.
With regards to claim 14, see the rejections of claims 1, 5 and 11.
With regards to claim 15, see the rejections of claims 1, 8 and 11.
With regards to claim 16, see the rejection of claim 1 and 15.
With regards to claims 17 and18, Thacker discloses the claimed invention according to claim 15 but fails to expressly disclose all the to specifically claimed electronics, processors, electronic devices and/or units, elements configuration, amplifiers, and the like, are well known and considered only a design choice involving routine skill of the art. Many of these components, parts and configurations are rejected elsewhere. Notice that the selection of a known material, components and/or configuration based on its suitability for its intended usage supports a prima facie obviousness determination. The examiner takes office notice of this fact, that these components, processes, physical features and/or types are well known.
In view of the utility, to discover the optimum or workable ranges, parts and connections by routine experimentation, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Thacker to include the teachings such as that taught by that that is well known and conventional in the art.
With regards to claims 19 and 20, Thacker discloses the claimed invention according to claim 15 but fails to expressly disclose all the to specifically claim all the solder joint, component joining, fixing connecting, interconnecting, soldering, soldering bump, bridge and associated terms in electronics assembly related concepts are generally processes, features and connection types are only considered an obviousness modification and design choice to one of routine skill of the art. The examiner takes office notice of this fact, that these processes, physical features and/or types and manufacturing connection and circuit types are well known.
In view of the utility, to provide an integrated electrical optics multiple chip module, methods, and processes, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Thacker to include the teachings such as that taught by that that is well known and conventional in the art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DJURA MALEVIC whose telephone number is (571)272-5975. The examiner can normally be reached M-F (9-5).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uzma Alam can be reached at 571.272. 3995The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DJURA MALEVIC/Examiner, Art Unit 2884
/UZMA ALAM/Supervisory Patent Examiner, Art Unit 2884
Prosecution Insights