Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 07/08/2026 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7, and 9 are rejected under 35 U.S.C. §103 as being unpatentable over Thacker et al. (US 2014/0321803 A1) in view of Deshpande et al. (WO 2015/130264 A1 (English)).
With regard to claim 1, Thacker teaches the processing circuit (integrated circuit 110-1), an optional I/O integrated circuit 134-1 that serializes/deserializes and provides photonic driver/receiver functions, optical integrated circuit 128-1, direct optical fiber 156, and package memory embodiments with memory-controller circuitry, Thacker [0045], [0047]-[0048], [0054]-[0056], [0064]-[0066], (Figures 1, 9 & 10).
Thacker, however, does not expressly teach: (1) “the transceiver directly drives a channel of the optical engine through the substrate” in the amended common-surface arrangement; and (2) the same recited substrate simultaneously serving as the common first-surface support and the embedded die-to-die high-speed route. Thacker's Figure 1 high-speed route is described as wiring on interposer 118 without passing through its TSVs, Thacker [0051]-[0053], (Figure 1).
Deshpande teaches devices attached at a first surface of a microelectronic substrate, with a bridge disposed within a substrate cavity and a local signal line electrically connecting the devices through the embedded bridge. The bridge may be passive and its signal lines may be formed in a dielectric interconnection layer, Deshpande, printed p. 3:2-11, p. 5:21-32, p. 6:3-14 and 31-34, (Figures 1 & 2A).
In view of the utility of Deshpande's localized embedded bridge for high-density die-to-die signaling while permitting separately optimized dies to share a package surface, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to implement Thacker's I/O-integrated-circuit-to-optical-integrated-circuit electrical connection using Deshpande's passive embedded bridge, thereby preserving Thacker's functional partition while providing the amended common-surface embedded signal route with predictable electrical communication.
With regard to claim 2, For the inherited limitations, refer to claim 1 above. Thacker teaches optical fiber 156 directly coupled to optical integrated circuit 128-1 and carrying high-speed optical signals to and from the package, Thacker [0054]-[0056], (Figures 1-4).
With regard to claim 3, For the inherited limitations, refer to claim 1 above. Thacker teaches optional I/O integrated circuit 134-1 as a separate die between integrated circuit 110-1 and optical integrated circuit 128-1, Thacker [0048], (Figure 1).
With regard to claim 7, For the inherited limitations, refer to claim 1 above. Deshpande teaches the added embedded interconnection by its bridge signal line within the substrate cavity, Deshpande, printed p. 5:21-32 and p. 6:3-14, (Figures 1 & 2A).
With regard to claim 9, For the inherited limitations, refer to claim 1 above. Thacker teaches multiple memory-bearing substrates/stacks and expressly permits multiple memory stacks coupled to interposer 118, Thacker [0064]-[0066], (Figures 9 & 10).
Claims 4 are rejected under 35 U.S.C. §103 as being unpatentable over Thacker et al. (US 2014/0321803 A1) in view of Deshpande et al. (WO 2015/130264 A1 (English)) and further in view of Sefidvash et al. (US 2007/0258551 A1).
With regard to claim 4, For the limitations inherited from claim 1, refer to the rejection of claim 1 above. Thacker teaches serializer/deserializer functionality in I/O integrated circuit 134-1, Thacker [0048].
Thacker, however, does not expressly teach “the transceiver comprises a transceiver physical-layer circuit that directly drives the channel.”
Sefidvash teaches a single-chip multi-sublayer PHY having PMD transmit/receive blocks and explicit serializer/deserializer structures in the PHY architecture, Sefidvash [0032]-[0036], [0040]-[0049], (Figures 1-3).
In view of the utility of integrating high-speed serialization/deserialization and PMD functions in a PHY for reduced signal distortion and standardized high-speed optical interfacing, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to implement Thacker's I/O integrated circuit as the known PHY architecture taught by Sefidvash, while retaining the embedded direct electrical route supplied by Deshpande, thereby predictably providing the claimed transceiver physical-layer circuit.
Claims 5 are rejected under 35 U.S.C. §103 as being unpatentable over Thacker et al. (US 2014/0321803 A1) in view of Deshpande et al. (WO 2015/130264 A1 (English)) and Sefidvash et al. (US 2007/0258551 A1)and further in view of Gloeckner et al. (US 2015/0381273 A1) and Wu et al. (US 2005/0105574 A1).
With regard to claim 5, For the inherited limitations, refer to claims 1 and 4 above. Thacker and Sefidvash establish the transceiver/PHY and serializer/deserializer context.
The inherited set, however, does not expressly teach: (1) “a serializer that directly drives the channel of the optical engine”; and (2) “a deserializer that directly receives signals from a transimpedance amplifier and limiting amplifier block in the optical engine.”
Gloeckner teaches a photonically-enabled optical transceiver in which received optical signals are converted by integrated photodetectors and pass through a TIA/LA chain; the photonic platform may be implemented with optical and electronic functions on one or multiple dies, Gloeckner [0016]-[0017], [0026]-[0031], [0073], (Figures 1A-2B & 4).
Wu teaches deficiency (1) by directly coupling serializer/deserializer 50 to laser driver 10, which drives laser diode 36, and teaches deficiency (2) by directly coupling receiving photodiode 37 through limiting-amplifier/transimpedance-amplifier 40 to serializer/deserializer 50, Wu [0024]-[0026], (Figure 7).
In view of the utility of the conventional short direct transmit and receive chains for minimizing high-speed interface stages, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to implement the optical side of the Thacker-Sefidvash package using Gloeckner's photonic receive front end and Wu's direct SerDes/laser-driver and TIA-LA/SerDes topology, thereby predictably providing the recited direct transmit and receive relationships.
Claims 6 are rejected under 35 U.S.C. §103 as being unpatentable over Thacker et al. (US 2014/0321803 A1) in view of Deshpande et al. (WO 2015/130264 A1 (English)) and further in view of Shubin et al. (US 2017/0199328 A1).
With regard to claim 6, For the inherited limitations, refer to claim 1 above. Thacker further teaches multiple optical integrated circuits and multiple corresponding I/O circuits in one MCM, Thacker [0062]-[0063], (Figures 6-8).
Thacker, however, does not expressly teach “an additional optical engine mounted on top of the transceiver.”
Shubin teaches an optical gain chip and photonic chip disposed on the top surface of a VLSI driver integrated circuit, electrically coupled to that driver, Shubin [0042]-[0046], (Figures 1 & 2).
In view of the utility of vertical optical-on-driver integration for compact high-bandwidth MCM packaging and alignment of optical/electrical functions, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to vertically stack one of Thacker's additional optical-engine instances on the corresponding transceiver/driver die as taught by Shubin, thereby predictably increasing package density while retaining the already-disclosed additional optical channel capacity.
Claims 8 are rejected under 35 U.S.C. §103 as being unpatentable over Thacker et al. (US 2014/0321803 A1) in view of Deshpande et al. (WO 2015/130264 A1 (English)) and further in view of Nagarajan (US 2016/0080090 A1).
With regard to claim 8, For the inherited limitations, refer to claim 1 above. Thacker teaches high-speed photonic-modulator driver signaling from the I/O integrated circuit to the optical integrated circuit, Thacker [0048].
Thacker does not expressly characterize the direct drive as “using one or more analog signals.”
Nagarajan teaches a signal-processing/driver architecture in which digital data is converted into modulation representations and a driver interface communicates analog-format signaling with the silicon photonics device, Nagarajan [0063], [0066]-[0070], (Figures 3, 5-8).
In view of the utility of analog modulator-drive signaling for directly controlling a silicon-photonic modulator from an electrical transceiver, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to use Nagarajan's analog driver-interface signaling in the Thacker-Deshpande direct path, thereby predictably driving the optical channel with the claimed analog signal.
Claims 10 and 11 are rejected under 35 U.S.C. §103 as being unpatentable over Thacker et al. (US 2014/0321803 A1) in view of Deshpande et al. (WO 2015/130264 A1 (English)) and Nagarajan (US 2016/0080090 A1).
With regard to claim 10, Thacker teaches a main integrated circuit, separate I/O/transceiver circuit, optical integrated circuit, direct optical fiber interface, and memory with memory-controller circuitry, Thacker [0048], [0054]-[0056], [0064]-[0066], [0078]-[0079], (Figures 1, 9-10, 16-17).
Thacker, however, does not expressly teach: (1) the transceiver sending the analog signals “through an interconnection embedded in a substrate of the multichip package”; and (2) expressly labeling the transmitted photonic-driver signals as analog.
Deshpande teaches deficiency (1) by the embedded passive bridge signal connection between devices on the substrate surface, Deshpande, printed p. 3:2-11, p. 5:21-32, p. 6:3-14 and 31-34, (Figures 1 & 2A).
Nagarajan teaches deficiency (2) by the driver/control interface communicating analog-format signals with the silicon-photonic device, Nagarajan [0063], [0066]-[0070], (Figures 3, 5-8).
In view of the utility of a localized embedded high-density connection and analog optical-modulator drive for reducing the electrical distance between a transceiver and photonic device, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to implement Thacker's transceiver-to-optical path using Deshpande's embedded bridge and Nagarajan's analog interface, thereby predictably transmitting analog driver signals through an embedded package interconnection.
The recited retrieval of data from memory and transmission of that data through the already-disclosed I/O path is a predictable use of Thacker's point-to-point memory/controller architecture and communications I/O, rather than an inherency assertion, Thacker [0048], [0066].
With regard to claim 11, For the claim 10 limitations, refer to claim 10 above. Thacker further teaches the reverse optical receive path: I/O circuit 134-1 accepts serial electrical data from photodetectors on optical integrated circuit 128-1 and converts the data for integrated circuit 110-1, while the memory-controller architecture provides storage access, Thacker [0048], [0066]. Nagarajan provides the analog receive/front-end context, Nagarajan [0066]-[0070].
In view of the utility of using the same bidirectional optical-transceiver interface for receive traffic as for transmit traffic, it would have been obvious to route the received data back through the transceiver to the main chip and store the resulting data in the package memory, thereby providing the predictable reverse operation of the disclosed full-duplex package.
Claims 12 are rejected under 35 U.S.C. §103 as being unpatentable over Thacker et al. (US 2014/0321803 A1) in view of Deshpande et al. (WO 2015/130264 A1 (English)) and Nagarajan (US 2016/0080090 A1) and further in view of Sefidvash et al. (US 2007/0258551 A1).
With regard to claim 12, For the limitations inherited from claim 10, refer to claim 10 above.
The claim-10 set does not expressly identify the direct-drive circuitry as “a physical-layer component in the transceiver chip.”
Sefidvash teaches a single-chip multi-sublayer PHY with PMD transmit/receive and serializer/deserializer structures, Sefidvash [0032]-[0036], [0040]-[0049], (Figures 1-3).
In view of the utility of placing serialization, PMD and related high-speed interface functions in a PHY block, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to implement the transceiver's direct optical-engine drive using the known PHY organization of Sefidvash, thereby predictably providing the recited physical-layer component.
Claims 13 are rejected under 35 U.S.C. §103 as being unpatentable over Thacker et al. (US 2014/0321803 A1) in view of Deshpande et al. (WO 2015/130264 A1 (English)) and Nagarajan (US 2016/0080090 A1) and Sefidvash et al. (US 2007/0258551 A1) and further in view of Lesea et al.(US 2015/0358084 A1).
With regard to claim 13, For the limitations inherited from claim 12, refer to claims 10 and 12 above.
The inherited set does not expressly teach “with a serializer in the physical-layer component of the transceiver chip, directly driving a channel in the optical engine chip.”
Lesea teaches a serializer 122 supplying driver circuit 124, with optical circuit 126 receiving the driver's output in the same package; alternative embodiments place serializer/driver/optical functions on the optical-side interposer/package wiring, Lesea [0020]-[0026], (Figures 1-6).
In view of the utility of directly coupling the serializer output to the optical-interface driver to reduce high-speed electrical path length, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to use Lesea's serializer-to-driver optical-interface topology in the transceiver PHY of the inherited combination, thereby predictably directly driving the claimed optical-engine channel.
Claims 14 are rejected under 35 U.S.C. §103 as being unpatentable over Thacker et al. (US 2014/0321803 A1) in view of Deshpande et al. (WO 2015/130264 A1 (English)) and Nagarajan (US 2016/0080090 A1) and Sefidvash et al. (US 2007/0258551 A1) and Lesea et al. (US 2015/0358084 A1) and Gloeckner et al. (US 2015/0381273 A1) and further in view of Wu et al. (US 2005/0105574 A1).
With regard to claim 14, For the limitations inherited from claim 13, refer to claim 13 above.
The inherited set does not expressly teach “with a deserializer in the physical-layer component of the transceiver chip, directly receiving signals from a transimpedance and limiting amplifier block in the optical engine chip.”
Gloeckner teaches the optical-side receive front end: integrated photodetectors and a TIA/LA chain in a photonically-enabled optical transceiver implementation, Gloeckner [0026]-[0031], [0065]-[0068], (Figures 1A-2B & 4).
Wu teaches the direct electrical relationship from receiving photodiode 37 through limiting-amplifier/transimpedance-amplifier 40 to serializer/deserializer 50, Wu [0024]-[0026], (Figure 7).
In view of the utility of a short direct optical-receiver amplifier-to-SerDes path for high-speed receive signaling, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to implement the optical-engine receive side of the inherited combination with Gloeckner's TIA/LA front end and couple that front end directly to the PHY deserializer in the conventional manner taught by Wu, thereby predictably providing the claimed receive relationship.
Claims 15 and 16 are rejected under 35 U.S.C. §103 as being unpatentable over Thacker et al. (US 2014/0321803 A1) in view of Deshpande et al. (WO 2015/130264 A1 (English)) and Nagarajan (US 2016/0080090 A1).
With regard to claim 15, Thacker teaches the package substrate/system shell, integrated circuit, transceiver-like I/O circuit, optical integrated circuit, direct fiber interface, and memory architecture, Thacker [0045]-[0056], [0064]-[0066], (Figures 1, 9-10).
Thacker, however, does not expressly teach: (1) the integrated circuit, transceiver and optical engine “formed on the top surface of the package substrate” in one consistent package-substrate mapping; and (2) direct analog drive “via conductors embedded in the package substrate.”
Deshpande teaches deficiency (1) and the embedded conductor portion of deficiency (2) by same-surface microelectronic devices electrically connected through a bridge disposed within the substrate cavity, Deshpande, printed p. 3:2-11, p. 5:21-32, p. 6:3-14 and 31-34, (Figures 1 & 2A).
Nagarajan teaches the analog portion of deficiency (2) by an electrical silicon driver/control interface that sends analog-format signaling to the silicon photonics device, Nagarajan [0063], [0066]-[0070], (Figures 3, 5-8).
In view of the utility of Deshpande's localized high-density embedded interconnect and Nagarajan's analog photonic-drive interface, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to implement Thacker's package with same-top-surface dies interconnected by the embedded bridge and to use analog direct-drive signaling at the optical boundary, thereby predictably producing the claimed compact package system.
With regard to claim 16, For the claim 15 limitations, refer to claim 15 above. Thacker teaches an optical receive path to the integrated circuit through the I/O circuit and memory-controller circuitry with accessible package memory, Thacker [0048], [0064]-[0066].
In view of the utility of storing received communications data in the package memory already controlled by the main integrated circuit, it would have been obvious to store data received through the optical engine in that memory, thereby providing the predictable receive-and-store use of the disclosed architecture.
Claims 17 and 19 are rejected under 35 U.S.C. §103 as being unpatentable over Thacker et al. (US 2014/0321803 A1) in view of Deshpande et al. (WO 2015/130264 A1 (English)) and Nagarajan (US 2016/0080090 A1) and Basso et al. (US 2015/0381312 A1) and further in view of Sefidvash et al. (US 2007/0258551 A1).
With regard to claim 17, For the limitations inherited from claim 15, refer to claim 15 above.
The claim-15 set does not expressly teach the complete recited transceiver internal chain: (1) a media access controller; (2) a physical coding sublayer and forward error correction block receiving from the MAC; (3) a serializer receiving from the PCS/FEC block; and (4) a deserializer outputting to the PCS/FEC block.
Basso teaches a PCS transmit structure configured to receive data from a MAC sublayer, with the PCS transmit structure comprising a FEC module that performs FEC sub-functions on the data, and further teaches PMA lanes configured to transmit data from the PCS transmit structure, Basso, claims 1 and 4, (Figures 1-3 corroborative).
Sefidvash teaches the directional serializer/deserializer organization of a multi-sublayer PHY, including the transmit-side PMD serializer and receive-side deserializer feeding the PCS-side digital core, Sefidvash [0032]-[0036], (Figure 3).
In view of the utility of Basso's PCS/FEC integration for reducing redundant coding operations and latency, and Sefidvash's known PHY serializer/deserializer organization for high-speed line transmission, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to implement Thacker's transceiver die with Basso's MAC-to-PCS/FEC structure and couple that structure to Sefidvash's transmit serializer and receive deserializer, thereby predictably providing the claimed MAC -> PCS/FEC -> serializer and deserializer -> PCS/FEC relationships.
With regard to claim 19, For the limitations inherited from claim 17, refer to claim 17 above. Deshpande already teaches an embedded multi-die interconnection between adjacent devices by a passive bridge signal line disposed in the substrate cavity, Deshpande, printed p. 5:21-32 and p. 6:3-14, (Figures 1-3B).
The claim requires a first embedded multi-die interconnection between the integrated circuit and transceiver and a second embedded multi-die interconnection between the transceiver and optical engine. Repeating Deshpande's known localized bridge connection for the second adjacent die pair would have been an ordinary duplication of the same high-density package interconnection to serve a second high-speed interface, with the predictable result that each adjacent die pair receives a localized embedded electrical path. Deshpande's multi-device embodiments expressly contemplate a plurality of devices attached to the bridge/substrate architecture, (Figure 3B).
Claims 18 are rejected under 35 U.S.C. §103 as being unpatentable over Thacker et al. (US 2014/0321803 A1) in view of Deshpande et al. (WO 2015/130264 A1 (English)) and Nagarajan (US 2016/0080090 A1) and Basso et al. (US 2015/0381312 A1) and Sefidvash et al. (US 2007/0258551 A1) and Lesea et al. (US 2015/0358084 A1) and Gloeckner et al. (US 2015/0381273 A1) and further in view of Wu et al. (US 2005/0105574 A1).
With regard to claim 18, For the limitations inherited from claim 17, refer to claim 17 above.
The inherited set does not expressly teach the complete optical-engine chain recited by claim 18.
Lesea teaches a serializer/driver/optical transmit path in which serializer circuitry supplies driver circuitry coupled to the optical circuit, Lesea [0020]-[0026], (Figures 1-6).
Gloeckner teaches the receive side of a photonically-enabled optical transceiver with integrated photodetectors and a TIA/LA chain, Gloeckner [0026]-[0031], [0065]-[0068], (Figures 1A-2B & 4).
Wu supplies the direct end-point relationships: serializer/deserializer 50 -> laser driver 10 -> laser diode 36 on transmit, and photodiode 37 -> TIA/limiting amplifier 40 -> serializer/deserializer 50 on receive, Wu [0024]-[0026], (Figure 7).
In view of the utility of using established short direct electrical chains at both optical transmit and receive boundaries, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to implement the optical engine of the inherited package with Lesea's serializer-driven transmit path and Gloeckner/Wu's optical-receiver amplifier path, thereby predictably providing the recited channel, optical transmitter, optical receiver, and amplifier-to-deserializer relationships.
Claims 20 are rejected under 35 U.S.C. §103 as being unpatentable over Thacker et al. (US 2014/0321803 A1) in view of Deshpande et al. (WO 2015/130264 A1 (English)) and Nagarajan (US 2016/0080090 A1) and Basso et al. (US 2015/0381312 A1) and Sefidvash et al. (US 2007/0258551 A1) and further in view of Hutton et al. (US 9,106,229 B1).
With regard to claim 20, For the limitations inherited from claim 19, refer to claims 17 and 19 above.
The inherited set does not expressly teach the claimed bump allocation and size relationship: the integrated circuit conducting signals to the package substrate via solder bumps while conducting signals to the first embedded multi-die interconnection only via microbumps, with the microbumps at least two times smaller than the solder bumps.
Thacker further teaches integrating the package chips using fine-pitch microbumps and coupling the chips to substrate 136 using C4-type interconnects, Thacker [0061]. Hutton quantifies the known size hierarchy: dies are coupled to an interposer through microbumps 134 having an exemplary diameter of about 10 um, while the interposer is coupled to the package substrate through C4/flip-chip bumps 120 having an exemplary diameter of about 100 um, Hutton, (Col. 6, Lines 13-42), (Figure 2).
In view of the utility of Thacker's fine-pitch microbumps for local chip integration and C4-type connections for coupling the chips to the package substrate, and Hutton's express dimensional teaching distinguishing the fine-pitch local microbumps from substantially larger C4/flip-chip package bumps, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to implement the Deshpande embedded-bridge connection with the fine-pitch microbumps while retaining the separate C4 package-substrate connection, thereby predictably providing the claimed routing distinction and a microbump size at least two times smaller than the solder bumps.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DJURA MALEVIC whose telephone number is (571)272-5975. The examiner can normally be reached M-F (9-5).
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/DJURA MALEVIC/Examiner, Art Unit 2884
/UZMA ALAM/Supervisory Patent Examiner, Art Unit 2884
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