Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed July 16, 2026.
Status of claims to be treated in this office action:
a. Independent: 1, 9, 16
b. Pending: 1-22
Claims 1, 8, 9, and 19 have been amended.
Specification
The amendments to the Specification have been reviewed and are accepted by
the Examiner. The objections to the Specification are withdrawn.
Claim Objections
The claim objections are withdrawn pursuant to claim amendments.
Claim Rejections - 35 USC § 112
The 112(b) claim rejections are withdrawn pursuant to claim amendments.
Response to Arguments
Applicant's arguments filed July 16, 2026 have been fully considered but they are not persuasive.
Regarding the arguments against the rejection of claims 1 and 9 using Nakagawa and Song on p.18:
The Applicant argues: “Nakagawa fails to disclose a “swing detector” that detects a voltage level difference between two transmission lines to output a “detection value.”” The Examiner finds this argument unpersuasive because, per p.5 of the Non-Final Rejection, para. [0134] explicitly teaches a circuit (Fig. 3: input buffer circuit 21) that detects “a voltage level difference between the first transmission line and the second transmission line”. In the Non-Final Rejection, Examiner mapped the input buffer circuit 21 to the swing detector, not the preamble detection circuit 100 of Fig. 1, as argued on p.18.
The Applicant further argues: “neither Nakagawa nor Song discloses or suggests transmitting a comparison result back to the transmitting device specifically for the purpose of dynamically adjusting the intensity of pre-level driving”. Examiner points to the updated rejection below. Using the broadest reasonable interpretation of the claim language, Examiner has updated the rejection to use Nakagawa Fig. 3: input/output circuit 14 as the first integrated circuit device and interface circuit 13 as the second integrated circuit device. Thus, AND circuit 24 transmits a comparison result, the data strobe signal DQSd, to the second integrated circuit device. Note that the argument cites a “transmitting device,” while claims 1 and 9 teach “the second integrated circuit device” and “a device”, respectively. See updated claim 1 rejection below for further detail.
Regarding the rejection of claim 16 using Kim on pp.18-19:
The Applicant argues “Examiner alleges that Kim teaches adjusting the intensity of pre-level driving based on transmitted results. However, Kim merely discloses applying a "predetermined" precharge voltage level deliberately to induce a voltage difference for testing purposes (Open-loop test mode)”. Examiner finds this argument unpersuasive because Kim indeed teaches a pre-level driving circuit (transistors MN0 and MN1) that adjusts the intensity of the pre-level driving (by adjusting the bit line selections via selection signals Y) based on pre-level driving intensity information (data from bit line amplifiers at the bottom of Kim Fig. 1).
The Applicant also argues “Applicant's Claim 16 requires dynamically adjusting the pre-level driving intensity based on feedback (pre-level driving intensity information) received from the receiving device. Kim does not disclose this closed-loop feedback mechanism, and the cited art provides no motivation to implement such dynamic calibration”. Although Examiner used the rejection of claim 2 to reject claim 16 in the Non-Final Rejection, the claim language of claim 2 teaches the “adjust an intensity of the pre-level driving according to the comparison result transmitted from the first integrated circuit device”, while claim 16 teaches “adjust an intensity of the pre-level driving according to the pre-level driving intensity information”. Because claim 16 does not include the “comparison result” language, there is no indication that the pre-level driving intensity information dynamically changes. Thus, this argument is not persuasive.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8, 9, and 13 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Nakagawa (US Pub. 20110227604 A1).
Regarding independent claim 1, Nakagawa discloses a system (Figs. 2A & 2B: system 10; [0026]) comprising:
a first integrated circuit device (Fig. 3: input/output circuit 14; [0042]); and
a second integrated circuit device (interface circuit 13; [0046]) coupled to the first integrated circuit device through a first transmission line (first transmission line L1; [0044]) and a second transmission line (second transmission line L2; [0044]. Examiner asserts that due to output buffer circuit 22, input buffer circuit 21, and signal control circuit 16, the two integrated circuit devices are connected through the two transmission lines),
wherein the first integrated circuit device (14) includes:
a swing detector configured to detect a voltage level difference between the first transmission line and the second transmission line (Fig. 3: input buffer circuit 21; [0134]: The input buffer circuit 21 may determine the data strobe signal DQSa based on the level difference between the two transmission lines L1 and L2; also see claim 8);
a comparator (Fig. 1: determination circuit 23; [0047]) configured to compare a detection value (data strobe signal DQSb; [0044]) of the swing detector with a reference swing value ([0050]-[0051]: When the termination control signal So is at the high-level (ODT ON), the determination circuit 23 outputs the permission signal Se in accordance with the data strobe signal DQS or the setting signal Ss…The determination circuit 23 counts transitions of the data strobe signal DQSb. Transitions of the data strobe signal DQSb, such as the rising edges and the falling edges of the data strobe signal DQSb, may occur for the number of data blocks to be read from the memory 11, such as the burst value. When the counted value exceeds a value set based on the setting signal Ss, the determination circuit 23 outputs the low-level (prohibition mode) permission signal Se. Examiner concludes that the “value set based on the setting signal Ss” is analogous to a reference swing value that is compared with transitions of the data strobe signal DQSb, which is analogous to the detection value); and
a comparison result transmission circuit (AND circuit 24; [0047]) configured to transmit a comparison result of the comparator (21) to the second integrated circuit device (13) for adjusting an intensity of pre-level driving of the second integrated circuit device ([0053]: The AND circuit 24 outputs a data strobe signal DQSd to the interface circuit 13 in accordance with the data strobe signal DQSb and the permission signal Se. When the permission signal Se is at the high-level (permission mode), the AND circuit 24 outputs the data strobe signal DQSd at a level substantially equal to the level of the data strobe signal DQSb…When the permission signal Se is at the low-level (prohibition mode), the AND circuit 24 outputs the low-level data strobe signal DQSd. Examiner asserts that adjusting an intensity of a pre-level driving can include increasing or decreasing voltages, currents, signals, clock periods, or impedances. Thus the adjusting of the level of the data strobe signal DQSd is analogous to “adjusting an intensity of pre-level driving of the second integrated circuit device”).
Regarding claim 8, Nakagawa discloses the limitations of claim 1, and further:
comprising a differential receiving circuit (Fig. 3: terminating circuit 18; [0079]) configured to receive the differential signal transmitted through the first transmission line and the second transmission line ([0083]: the interface circuit 13 activates the terminating circuit 18 for the transmission lines L1 and L2 based on the termination control signal So).
Independent claim 9 contains limitations that are mostly the same in claimed subject matter as the last three limitations of claim 1, and therefore claim 9 is rejected for the same reasons as independent claim 1.
Regarding claim 13, Nakagawa discloses the limitations of claim 9. Claim 13 recites mostly the same limitations as claim 8, and henceforth is rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa (US Pub. 20110227604 A1) as applied to claim 1 above, and further in view of Kim (KR 20100027402 A).
Regarding claim 2, Nakagawa discloses the limitations of claim 1, and further through Nakagawa:
wherein the second integrated circuit device (Fig. 3: memory 11) includes:
a differential transmission circuit (termination control circuit 17) configured to transmit a differential signal ([0044]: a data strobe signal DQSb in accordance with the differential voltage between the data strobe signal DQSa and the inverted data strobe signal BDQSa) through the first transmission line and the second transmission line ([0086]: the determination circuit 23 outputs the high-level permission signal Se. In response to the permission signal Se, the termination control circuit 17 adjusts the resistance of the terminating circuit 18 so that the levels of the first and second transmission lines L1 and L2 may become a middle voltage of the high potential voltage VDD); and
Nakagawa does not disclose:
a pre-level driving circuit configured to perform pre-level driving to reduce a voltage difference between the first transmission line and the second transmission line, and adjust an intensity of the pre-level driving according to the comparison result transmitted from the first integrated circuit device.
However, Kim teaches:
a pre-level driving circuit configured to perform pre-level driving to reduce a voltage difference between the first transmission line and the second transmission line (page 8, lines 11-16: in order to detect errors caused by a data transmission unit operating abnormally at an early stage in the present invention, the precharge voltage of the second transmission line in test mode is supplied at a predetermined level compared to the normal precharge voltage level, thereby intentionally reducing the voltage difference (ΔV) for detecting data of the second transmission line), and adjust an intensity of the pre-level driving according to the comparison result transmitted from the first integrated circuit device (p. 6, lines 12-16: a precharge unit for precharging the second transmission line to a normal precharge voltage level in response to a precharge signal when waiting for data transmission, or for precharging the second transmission line to a voltage level adjusted to a predetermined level relative to the normal precharge voltage level in response to a test precharge signal. Examiner asserts that the precharge unit is analogous to a pre-level driving circuit, and that the predetermined level is affected by the transmitted data).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kim to Nakagawa wherein an integrated circuit device includes a pre-level driving circuit configured to perform pre-level driving to reduce a voltage difference between the first transmission line and the second transmission line, and adjust an intensity of the pre-level driving according to the comparison result transmitted from the first integrated circuit device in order to detect errors quicky and accurately without affecting non-test circuitry (Kim, p. 8, line 20 – p. 9, line 3).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa (US Pub. 20110227604 A1) and Kim (KR 20100027402 A) as applied to claim 2 above, respectively, and further in view of Lee et al. (US Pub. 20170287535 A1; “Lee”).
Regarding claim 3, Nakagawa and Kim together disclose the limitations of claim 2. Neither Nakagawa nor Kim discloses:
wherein the swing detector, the comparator and the comparison result transmission circuit of the first integrated circuit device are configured to operate during a training operation.
However, Lee teaches:
wherein the swing detector (Fig. 3: search logic SRL; [0061]: Based on such level transition of the buffer signal SB, the search logic SRL may search for the code value of the training control code SCD corresponding the minimum difference between the voltage level VIH or VIL of the input signal SI and the reference voltage VREF), the comparator (selector MUX; [0053]: The selector MUX, also described as a selecting circuit, may select one of the training control code SCD from the search logic SRL and the optimum code OCD from the calculator CAL in response to a mode signal MD to output the selected one as the control code CCD. Examiner asserts that a person with ordinary skill in the art would know that a multiplexer can function as a digital comparator) and the comparison result transmission circuit (Figs. 1 or 3: reception buffer BF; [0043]: The reception buffer BF may…generate a buffer signal SB, also described as a buffer output or buffer output signal) of the first integrated circuit device (Fig. 1: second device 40; [0040]) are configured to operate during a training operation ([0069]: As described above, the self-training circuit 62 may output a training control code SCD as the control code CCD in a training mode such that the training control code SCD is changed sequentially to search for an optimum code OCD corresponding to an optimal voltage level of the reference voltage VREF and output the optimum code OCD as the control code CCD in a normal mode).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lee to modified Nakagawa wherein the swing detector, the comparator and the comparison result transmission circuit of the first integrated circuit device are configured to operate during a training operation in order to provide a training method that efficiently provides a reference voltage (Lee, [0009]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa (US Pub. 20110227604 A1) and Kim (KR 20100027402 A) as applied to claim 2 above, and further in view of Yamada et al. (US Pat. 5545977 A; “Yamada”).
Regarding claim 4, Nakagawa and Kim together disclose the limitations of claim 2, and further through Nakagawa:
wherein the first integrated circuit device (Fig. 3: system circuit 12) further includes:
a reference voltage generator (Fig. 1: reference voltage generating circuit 101; [0022]) configured to generate a high reference voltage and a low reference voltage ([0023]: The reference voltage generating circuit 101 generates a first reference voltage Vr11 (>Vm) that is higher than the middle potential Vm and a second reference voltage Vr12 (<Vm) that is lower than the middle potential Vm); and
Neither Nakagawa nor Kim discloses:
a reference swing detector configured to detect a voltage difference between the high reference voltage and the low reference voltage and provide a detection result as the reference swing value.
However, Yamada teaches:
a reference swing detector configured to detect a voltage difference between the high reference voltage and the low reference voltage and provide a detection result as the reference swing value (col. 3, lines 26-37: A second constant voltage generating circuit arrangement according to the present invention comprises: a first reference potential generating circuit for generating a predetermined difference in potential between a first reference potential line thereof and a first node thereof; a second reference potential generating circuit for generating a predetermined difference in potential between a second reference potential line thereof and a second node thereof; a comparator circuit for comparing the potential of the first node with the potential of the second node; and a driver circuit for driving the output line under control by an output of the comparator circuit. Examiner asserts that this comparator is analogous to the claimed reference swing detector).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Yamada to modified Nakagawa wherein the first integrated circuit comprises a reference swing detector configured to detect a voltage difference between the high reference voltage and the low reference voltage and provide a detection result as the reference swing value in order to reduce the temperature-dependency of the output line voltage (Yamada, col. 7, lines 16-27).
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa (US Pub. 20110227604 A1) and Kim (KR 20100027402 A) as applied to claim 2 above, and further in view of Kim et al. (US Pub. 20070139084 A1; “Kim-084”).
Regarding claim 5, Nakagawa and Kim together disclose the limitations of claim 2. Neither Nakagawa nor Kim discloses:
wherein the second integrated circuit device further includes a time control circuit configured to adjust a pre-level driving time of the pre-level driving circuit.
However, Kim-084 teaches:
wherein the second integrated circuit device (Fig. 6: data receiving circuit 600; [0117]) further includes a time control circuit (bias units of amplifier circuit 610, which are not shown per [0093]) configured to adjust a pre-level driving time ([0117]: The data receiving circuit 600…can reduce total current consumption by reducing the time (1), that is, operating time of the amplifier circuit 610; [0076] describes pre-level driving: When the level of the external reference signal XVREF or the level of the external input signal XlN is varied, swing ranges and output delay times of data DATA and inverted data DATAB of the amplifier circuit 400 are prevented from varying by using the first and second bias units 410 and 420; per [0094], amplifier circuits 400 and 610 have the same structure and operation) of the pre-level driving circuit (amplifier circuit 610).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kim-084 to modified Nakagawa wherein the second integrated circuit device further includes a time control circuit configured to adjust a pre-level driving time of the pre-level driving circuit in order to maintain a constant output swing range and delay time despite variations in input and reference signals (Kim-084, [0022]).
Regarding claim 6, Nakagawa, Kim, and Kim-084 together disclose the limitations of claim 5. Further, through Kim-084:
wherein the pre-level driving circuit (Fig. 6: 610) is configured to be activated for a predetermined time before the differential transmission circuit (the first transmission unit 631 and the second transmission unit 633; [0111]) is activated (in reference to Fig. 8, per [0101]: a pulse KPATH for turning on sixth and seventh transistors TR6 and TR7 of the amplifier circuit 610 changes to a high level as shown in position (i); [0104]: The amplifier circuit 610 continues to operate until the internal latch circuit driving pulse KSPB changes to a low level as shown in position (iv); [0110]: The first transmission unit 631 latches the data DATA output from the output node OUTN or outputs the data DATA through a first transmission node NTM1 in response to the data control pulse KSP2. The second transmission unit 633 latches the inverted data DATAB output from the inverted output node OUTNB or outputs the inverted data DATAB through a second transmission node NTM2 in response to the data control pulse KSP2. Examiner asserts that [0101] and [0104] describe the pre-level driving circuit activation and [0110] describes the differential transmission circuit activation), and the time control circuit is configured to adjust the predetermined time ([0117]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kim-084 to modified Nakagawa wherein the pre-level driving circuit is configured to be activated for a predetermined time before the differential transmission circuit is activated, and the time control circuit is configured to adjust the predetermined time in order to maintain a constant output swing range and delay time despite variations in input and reference signals (Kim-084, [0022]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa (US Pub. 20110227604 A1) and Kim (KR 20100027402 A) as applied to claim 2 above, and further in view of Park (US Pub. 20100054073 A1).
Regarding claim 7, Nakagawa and Kim together disclose the limitations of claim 2. Neither Nakagawa nor Kim discloses:
wherein, when the first integrated circuit device is a memory and the second integrated circuit device is a memory controller, the differential signal is a data clock.
However, Park teaches:
wherein, when the first integrated circuit device is a memory and the second integrated circuit device is a memory controller ([0013]: the high-speed semiconductor memory device receives an address signal and a command signal from an external controller on the basis of a system clock HCK, and outputs data stored in the semiconductor memory device to the external controller on the basis of a data clock WCK), the differential signal ([0086]: two multiple-phase data division clocks MULTI_DIV_WCK_0 and MULTI_DIV_WCK_180 having a 180-degree phase difference in response to the data division clock DIV_WCK; Fig. 7 shows that MULTI_DIV_WCK_0 and MULTI_DIV_WCK_180 are a differential pair) is a data clock ([0013]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Park to modified Nakagawa wherein when the first integrated circuit device is a memory and the second integrated circuit device is a memory controller, the differential signal is a data clock in order to improve memory device efficiency by providing an auto click alignment training mode (Park, [0031]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa (US Pub. 20110227604 A1) as applied to claim 9 above, and further in view of Yamada (US Pat. 5545977 A).
Regarding claim 10, Nakagawa discloses the limitations of claim 9. Claim 10 recites exactly the same limitations as claim 4, and henceforth is rejected for the same reasons.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa (US Pub. 20110227604 A1) as applied to claim 9 above, and further in view of Nosaka et al. (JP 2004187188 A; “Nosaka”) and Cho (US Pub. 20200036925 A1).
Regarding claim 11, Nakagawa discloses the limitations of claim 9. Nakagawa does not disclose:
wherein the swing detector includes:
a first analog-to-digital converter configured to convert a voltage level of the first transmission line into a first digital code;
a second analog-to-digital converter configured to convert a voltage level of the second transmission line into a second digital code; and
a subtractor configured to generate the detection value by using a difference between the first digital code and the second digital code.
However, Nosaka teaches:
wherein the swing detector (Fig. 5: analog-to-digital converter; [0044]) includes:
a first analog-to-digital converter (comparator 31, boundary detector 41, and flip-flops 61 and 81; [0036]-[0037]) configured to convert a voltage level of the first transmission line (transmission line 90; [0046]) into a first digital code;
a second analog-to-digital converter (comparator 32, boundary detector 42, and flip-flops 62 and 82; [0036]-[0037]) configured to convert a voltage level of the second transmission line (transmission line 91; [0046]) into a second digital code; and
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Nosaka to modified Nakagawa wherein the swing detector includes a first analog-to-digital converter configured to convert a voltage level of the first transmission line into a first digital code; and a second analog-to-digital converter configured to convert a voltage level of the second transmission line into a second digital code in order to reduce the generation of standing waves by providing impedance matching in the wires of a parallel ADC (Nosaka, [0010]).
Also, Cho teaches:
a subtractor (Fig. 1: subtractor 60; [0026]) configured to generate the detection value by using a difference between the first digital code and the second digital code ([0026]: The subtractor 60 may subtract the second digital signals Δd from each of the first digital signals d1 to dm to generate each of digital pixel data D1 to Dm).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Cho to modified Nakagawa wherein the swing detector includes a subtractor configured to generate the detection value by using a difference between the first digital code and the second digital code in order to provide compensation for digital data signals that include noise (Cho, [0031], [0053], [0059], [0083]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa (US Pub. 20110227604 A1) as applied to claim 9 above, and further in view of Aaron (US Pub. 20240126510 A1).
Regarding claim 12, Nakagawa discloses the limitations of claim 9. Nakagawa does not disclose:
wherein the swing detector includes:
a first oscillator configured to generate a first periodic wave corresponding to a voltage level of the first transmission line;
a second oscillator configured to generate a second periodic wave corresponding to a voltage level of the second transmission line;
a first counter configured to count a number of activations of the first periodic wave to generate a first counting value;
a second counter configured to count a number of activations of the second periodic wave to generate a second counting value; and
a subtractor configured to generate the detection value by using a difference between the first counting value and the second counting value.
However, Aaron teaches:
wherein the swing detector (Fig. 1B: readout circuit 40; [0070]) includes:
a first oscillator (oscillator
λ
0
ν
0
) configured to generate a first periodic wave ([0006]: each of the prime oscillators configured to generate a corresponding one of the prime waves having a frequency corresponding to a prime number, and a dividend oscillator configured to be tuned to generate the dividend wave to have a frequency that corresponds to the dividend) corresponding to a voltage level of the first transmission line (transmission line paths 800; [0075]; [0077]: The input controller 100 can be configured to program one of the oscillators 300 (which can be referred to as the dividend oscillator 300) with a value corresponding to the input dividend integer, for example, by providing an input waveform 200 representing the integer to the dividend oscillator 300; [0010] In some embodiments, the transmission circuit further comprises: a plurality of gyrators, each of the gyrators configured to convert a corresponding one of the prime waves and the dividend waves from a voltage wave to a current wave. Examiner concludes that the waves that correspond to a voltage level of the first transmission line are voltage waves);
a second oscillator (
λ
1
ν
1
) configured to generate a second periodic wave ([0006]) corresponding to a voltage level of the second transmission line (800; [0075]; [0077]; [0010]);
a first counter (Fig. 2C: register 502; [0089]) configured to count a number of activations of the first periodic wave to generate a first counting value ([0089]: Each of the one or more amplifiers 602 of the zero-crossing detector 600 can be connected to a corresponding register 502. The corresponding register 502 can be configured to count the number of zero crossings of the wave within);
a second counter configured to count a number of activations of the second periodic wave to generate a second counting value ([0089]); and
a subtractor (Fig. 1B: analog computing blocks 750; [0154]) configured to generate the detection value by using a difference between the first counting value and the second counting value ([0154]: The analog computing blocks 750 can be configured to compute operations such as summing the zero-crossing pulses for number factoring and/or sending the sinusoidal signals to analog computers for the purposes of, but not limited to, addition, integration, differentiation, logarithms, including trigonometric identities, multiplication, and convolution. Examiner asserts that since the analog computing blocks 750 are capable of addition and multiplication, they are also capable of subtraction (i.e.: adding -1 times a counting value to the other counting value)).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Aaron to modified Nakagawa wherein the swing detector includes: a first oscillator configured to generate a first periodic wave corresponding to a voltage level of the first transmission line; a second oscillator configured to generate a second periodic wave corresponding to a voltage level of the second transmission line; a first counter configured to count a number of activations of the first periodic wave to generate a first counting value; a second counter configured to count a number of activations of the second periodic wave to generate a second counting value; and a subtractor configured to generate the detection value by using a difference between the first counting value and the second counting value in order to prevent an increase in computation time that usually results from increasing inputs (Aaron, [0003], [0005]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa (US Pub. 20110227604 A1) as applied to claim 9 above, and further in view of Park (US Pub. 20100054073 A1).
Regarding claim 14, Nakagawa discloses the limitations of claim 9 above. Claim 14 recites mostly the same limitations as claim 7, and henceforth is rejected for the same reasons.
Claims 15 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa (US Pub. 20110227604 A1) and Park (US Pub. 20100054073 A1) as applied to claim 14 above, and further in view of Lee (US Pub. 20170287535 A1).
Regarding claim 15, Nakagawa and Park together disclose the limitations of claim 14. Claim 15 recites mostly the same limitations as claim 3, and henceforth is rejected for the same reasons.
Regarding claim 22, Nakagawa, Park, and Lee together disclose the limitations of claim 15. Claim 22 recites mostly the same limitations as claim 7, and henceforth is rejected for the same reasons.
Claims 16 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa (US Pub. 20110227604 A1) in view of Kim (KR 20100027402 A).
Independent claim 16 contains a first limitation that is mostly the same in claimed subject matter as claim 8, and that limitation is thus rejected for the same reasons using Nakagawa.
Nakagawa does not disclose:
a receiving circuit configured to receive pre-level driving intensity information from a device that receives the differential signal; and
a pre-level driving circuit configured to perform pre-level driving to reduce a voltage difference between the first transmission line and the second transmission line, and adjust an intensity of the pre-level driving according to the pre-level driving intensity information.
However, Kim teaches:
a receiving circuit (Fig. 1: plurality of data transfer transistors 120; p.2, line 12) configured to receive pre-level driving intensity information (data from the bit line amplifiers at the bottom of Fig. 1. Per p.2. lines 12-14: a plurality of data transfer transistors (120) for selectively transferring data of a plurality of bit line pairs (111A·111B, 112A·112B, 113A·113B) to a data transfer line pair (130A·130B) in response to a selection signal (YI<0:2>). Examiner asserts that the data from the selected bit line pairs, selected based on a selection signal, is analogous to pre-level driving intensity information because it affects the levels of the transmission lines 130A and 130B) from a device that receives the differential signal (bit line amplifiers at the bottom of Fig. 1); and
a pre-level driving circuit (first and second data transfer transistors MN0 and MN1; p.5, lines 10-11) configured to perform pre-level driving to reduce a voltage difference between the first transmission line and the second transmission line (p.5, lines 9-16: there may be cases where the potential of the gate terminal rises momentarily due to 'M2C (METAL TO CONTACT) NOT OPEN'. In this case, the first and second data transfer transistors (MN0, MN1) cannot maintain a complete turn-off state, and thus the voltage level of the data transmission line pair (130A·130B) changes according to the signal level of the first bit line pair (111A, 111B). Under the conditions described above, due to abnormal operation of the first and second data transmission transistors (MN0, MN1), the precharge voltage level (VCORE) of the data transmission line pair (130A·130B) is affected, and the voltage difference (ΔV2) is reduced. Examiner concludes that the first and second data transfer transistors MN0 and MN1 reduce a voltage difference between the first and second transmission lines 130A and 130B. Per para. [0035] of the present application, “The pre-level driving may reduce a voltage difference between the first transmission line 301 and the second transmission line 302”, thus pre-level driving is equivalent to changing a voltage difference between two transmission lines), and adjust an intensity of the pre-level driving according to the pre-level driving intensity information (the selection signal YI<0:2> and the state of the first and second data transfer transistors MN0 and MN1 determine the intensity or voltage difference between the transmission line).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kim to Nakagawa wherein an integrated circuit device includes a receiving circuit configured to receive pre-level driving intensity information from a device that receives the differential signal; and a pre-level driving circuit configured to perform pre-level driving to reduce a voltage difference between the first transmission line and the second transmission line, and adjust an intensity of the pre-level driving according to the pre-level driving intensity information in order to detect errors quicky and accurately without affecting non-test circuitry (Kim, p. 8, line 20 – p. 9, line 3).
Regarding claim 21, Nakagawa and Kim together disclose the limitations of claim 16. Claim 21 recites mostly the same limitations as claim 2, and henceforth is rejected for the same reasons.
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa (US Pub. 20110227604 A1) and Kim (KR 20100027402 A) as applied to claim 16 above, and further in view of Kim-084 (US Pub. 20070139084 A1).
Regarding claim 17, Nakagawa and Kim together disclose the limitations of claim 16. Claim 17 recites mostly the same limitations as claim 5, and henceforth is rejected for the same reasons.
Regarding claim 18, Nakagawa, Kim, and Kim-084 together disclose the limitations of claim 17. Claim 18 recites exactly the same limitations as claim 6, and henceforth is rejected for the same reasons.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa (US Pub. 20110227604 A1), Kim (KR 20100027402 A), and Kim-084 (US Pub. 20070139084 A1) as applied to claim 18 above, and further in view of Kim (US Pub. 20200143855 A1; “Kim-855”) and Jung (US Pat. 11018677 B1).
Regarding claim 19, Nakagawa, Kim, and Kim-084 together disclose the limitations of claim 18. Neither Nakagawa, Kim, nor Kim-084 discloses:
wherein the time control circuit includes:
a plurality of shift circuits configured to shift an activation signal in synchronization with a clock to generate a transmission activation signal of the differential transmission circuit;
a selection circuit configured to select one of former signals of the transmission activation signal from the plurality of shift circuits in response to selection information; and
a signal generation circuit configured to receive the signal selected by the selection circuit, and activate a pre-level driving activation signal for activating the pre-level driving circuit in response to the received signal, and deactivate the pre-level driving activation signal in response to the transmission activation signal.
However, Kim-855 teaches:
wherein the time control circuit (Fig. 4: clock delay circuit 230; [0050]) includes:
a plurality of shift circuits configured to shift an activation signal in synchronization with a clock ([0052]: The clock delay circuit 230 may generate first to fourth delay clocks R1DOCLK, F1DOCLK, R2DOCLK and F2DOCLK by delaying the phase of the clock CLK, when the strobe enable signal LTOE_OUT is enabled) to generate a transmission activation signal of the differential transmission circuit ([0053]: The data output circuit 240 may generate the read strobe signal RDQS by combining the first to fourth delay clocks…and output the converted cell data CDATA as the read data DOUT<7:0>; [0046]: The write control circuit 130 may latch the test data DIN<7:0> inputted serially from the controller in response to the read strobe signal RDQS…and then provide the internal circuit 140 with the parallel data as cell data CDATA. Examiner concludes that RDQS is a transmission activation signal);
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kim-855 to modified Nakagawa wherein the time control circuit includes a plurality of shift circuits configured to shift an activation signal in synchronization with a clock to generate a transmission activation signal of the differential transmission circuit in order to test a memory device without receiving a data strobe signal through a pad (Kim-855, [0005]).
Also, Jung teaches:
a selection circuit (Fig. 2: selector 253; col. 5, line 12) configured to select one of former signals of the transmission activation signal (signal PRE_TX_EN; col. 3, line 60) from the plurality of shift circuits (plurality of D flip-flops 211_1 to 211_N; col. 4, lines 14-15) in response to selection information (phase comparison result EARLY_1 to EARLY_N and LATE_1 to LATE_N; col. 4, lines 51-52); and
a signal generation circuit (Fig. 2: selection code generator 251; col. 4, lines 53-54) configured to receive the signal selected by the selection circuit, and activate a pre-level driving activation signal (selection codes SEL<1:N>; col. 4, line 64 through col. 5, line 1: the selection code generator 251 may generate the selection codes SEL<1:N> such that the preliminary transmission enable signal TX_EN_Q3 can be selected as the transmission enable signal TX_EN) for activating the pre-level driving circuit (Fig. 1: transmitter 110; col. 3, line 22) in response to the received signal (transmission enable signal TX_EN; col. 3, lines 28-30: The transmitter 110 may be enabled in response to a transmission enable signal TX_EN), and deactivate the pre-level driving activation signal in response to the transmission activation signal (col. 5, lines 4-8: the selection code generator 251 may be disabled when the training enable signal T_EN is disabled. The selection code generator 251 may hold the generated selection codes SEL<1:N> when it is disabled).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Jung to modified Nakagawa wherein the time control circuit includes a selection circuit configured to select one of former signals of the transmission activation signal from the plurality of shift circuits in response to selection information; and a signal generation circuit configured to receive the signal selected by the selection circuit, and activate a pre-level driving activation signal for activating the pre-level driving circuit in response to the received signal, and deactivate the pre-level driving activation signal in response to the transmission activation signal in order to accurately adjust enable time for a transmitter (Jung, col. 2, lines 34-35).
Regarding claim 20, Nakagawa, Kim, Kim-084, Kim-855, and Jung together disclose the limitations of claim 19. Kim-855 teaches a time control circuit, and further through Jung:
a delay circuit (Fig. 1: data delay circuit 130; col. 3, line 23) configured to delay the signal selected by the selection circuit (col. 3, lines 48-49: The data delay circuit 130 may delay data DATA to generate the transmission data DATA_TX), and transmit a delayed signal to the signal generation circuit (Examiner concludes that the delayed DATA_TX signal delays selection code generator 251, which is analogous to the signal generation circuit, because DATA_TX is the input to phase comparison circuit 230, which precedes selection code generator 251. Thus, the selector 253, analogous to the selection circuit, is also delayed).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Jung to modified Nakagawa wherein the time control circuit further includes a delay circuit configured to delay the signal selected by the selection circuit, and transmit a delayed signal to the signal generation circuit in order to accurately adjust enable time for a transmitter (Jung, col. 2, lines 34-35).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Song (US Pub. 20200143852 A1): para. [0030] and Fig. 1 are relevant to claims 1, 9, and 16.
Stark (US Pat. US 7148699 B1): col. 11, lines 24-38 and Fig. 9 are relevant to claims 1, 9, and 16.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Khamdan N. Alrobaie/Primary Examiner, Art Unit 2824
9/24/2026
/E.R.A./Examiner, Art Unit 2824
9/18/2026
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