DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-16 and 18-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over SUZUKI et al. US 2018/0033704 A1 (hereinafter referred to as Suzuki) in view of Takasu JP2002340990A.
Regarding Claim 1, Suzuki discloses a semiconductor fault analysis device (fig. 1, inspection system 1, par. [0028]) comprising: a first analysis part (fig. 1, observation optical system 13, par. [0031]) in which a first optical detection part (fig. 1, two-dimensional camera 15, par. [0035]) receives light emitted by a semiconductor device (fig. 1, semiconductor device D, par. [0032]) via a first optical system (fig. 1, objective lens and the beam splitter, par. [0035]), and the first optical system is moved relative to the semiconductor device by a first drive part (fig. 1, XYZ stage 14, par. [0034]); a second analysis part (fig. 1, laser light source 31, par. [0040]) in which a second optical detection part (fig. 1, imaging device 34, par. [0040]) receives light emitted by the semiconductor device via a second optical system (fig. 1, laser marking optical system 32, par. [0040]), and the second optical system is moved relative to the semiconductor device by a second drive part (fig. 1, XYZ stag 33, par. [0045]); a device arrangement part (fig. 1, sample stage 40, par. [0029]) having a chuck disposed between the first analysis part (13) and the second analysis part (31) to hold the semiconductor device (see fig. 1);a stimulus signal application part (fig. 1, tester unit 11, par. [0031]) configured to apply a stimulus signal to the semiconductor device (par. [0032]); and a control part (fig. 1, computer 21, par. [0032]) configured to output a command to the first analysis part, the second analysis part (par. [0034]), the device arrangement part (40), and the stimulus signal application part (11), wherein the control part (21) outputs an alignment command that outputs an analysis command that applies a stimulus signal to the semiconductor device (D) and receives light from the semiconductor device emitted according to the stimulus signal with at least one of the first optical detection part (15) and the second optical detection part (34), the second analysis part (31), the stimulus signal application part (11), and the device arrangement part (par. [0045]-[0055]).
Suzuki does not disclose the chuck being moved relative to the first analysis part and the second analysis part.
Takasu discloses the chuck (fig. 2, elm. 11, par. [0005], [0036]) being moved relative to the first analysis part (fig. 2, elm. 21, par. [0028]) and the second analysis part (fig. 2, elm. 22, par. [0028]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a sample holder mounted on a stage movable in a two-dimensional direction or the like by a stage drive mechanism, as taught in Takasu in modifying the apparatus of Suzuki. The motivation would be to provide stage movable in a two-dimensional direction (see ).
Regarding Claim 2, Suzuki and Takasu discloses the semiconductor fault analysis device according to claim 1, Takasu discloses wherein the analysis command causes the chuck (fig. 2, elm. 11, par. [0005], [0036]) to be moved by a third drive part (fig. 2, elm. 13, par. [0005], [0036]) included in the device arrangement part (fig. 2, elm. 12, par. [0036]) so that the semiconductor device (fig. 2, elm. 10, par. [0009]) overlaps the optical axis of the first optical system (fig. 2, elm. 21, par. [0036]) and the optical axis of the second optical system (fig. 2, elm. 22, par. [0037]) then causes the semiconductor device to be analyzed (par. [0026]-[0029]).
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding Claim 3, Suzuki and Takasu discloses the semiconductor fault analysis device according to claim 1, Suzuki discloses wherein the first optical detection part (fig. 7, camera 15B, par. [0071]) is a first infrared camera, and the second optical detection part (fig. 1, imaging device 34, par. [0040]) is a second camera.
Suzuki and Takasu do not disclose a second infrared camera. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a second infrared camera, since it has been held that the mere duplication of the essential working parts of a device involves only routine skill in the art. See St. Regis Paper Co. v. Bemis Co., 193 USPQ 8 and MPEP 2144.04.
Regarding Claim 5, Suzuki and Takasu discloses the semiconductor fault analysis device according to claim 1, Suzuki discloses wherein the control part (fig. 1, computer 21, par. [0032]) outputs an analysis command to receive light from the semiconductor device (fig. 1, semiconductor device D, par. [0032]) emitted according to the stimulus signal (par. [0034]-[0042]) with both the first optical detection part (fig. 1, two-dimensional camera 15, par. [0035]) and the second optical detection part (fig. 1, imaging device 34, par. [0040]), to the first analysis part (fig. 1, observation optical system 13, par. [0031]) and the second analysis part (fig. 1, laser light source 31, par. [0040]).
Regarding Claim 6, Suzuki discloses a semiconductor fault analysis device (fig. 1, inspection system 1, par. [0028]) comprising: a first analysis part (fig. 1, observation optical system 13, par. [0031]) configured to irradiate a semiconductor device (fig. 1, semiconductor device D, par. [0032]) with light generated by a first light source (fig. 1, light source 12, par. [0033]) via a first optical system (fig. 1, observation optical system 13, par. [0031]) in which a first optical detection part (fig. 1, two-dimensional camera 15, par. [0035]) having a first optical scanning part (fig. 6, optical scanning unit 16, par. [0076]); a second analysis part (fig. 1, laser light source 31, par. [0040]) configured to irradiate the semiconductor device with light generated by a second light source (fig. 1, laser light source 35, par. [0040]) via a second optical system (fig. 1, laser marking optical system 32, par. [0040]), having a second optical scanning part (fig. 1, optical scanning unit, par. [0047]); a device arrangement part (fig. 1, sample stage 40, par. [0029]) having a chuck disposed between the first analysis part and the second analysis part to hold the semiconductor device (see fig. 1), an electrical signal acquisition part (fig. 5, electric signal detector 52, par. [0078]) configured to receive an electrical signal output by the semiconductor device (fig. 1, semiconductor device D, par. [0032]); and a control part (fig. 1, computer 21, par. [0032]) configured to output a command to the first analysis part (13), the second analysis part (31), the device arrangement part (40), and the electrical signal acquisition part (52), wherein the control part outputs an analysis command that irradiates the semiconductor device with light from at least one of the first analysis part and the second analysis part and receives an electrical signal from the semiconductor device by the electrical signal acquisition part to the first analysis part, the second analysis part, the electrical signal acquisition part, and the device arrangement part (par. [0045]-[0055], [0077]-[0078]).
Suzuki does not disclose the chuck being moved relative to the first analysis part and the second analysis part.
Takasu discloses the chuck (fig. 2, elm. 11, par. [0005], [0036]) being moved relative to the first analysis part (fig. 2, elm. 21, par. [0028]) and the second analysis part (fig. 2, elm. 22, par. [0028]).
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding Claim 7, Suzuki and Takasu discloses the semiconductor fault analysis device according to claim 6, Takasu discloses wherein the analysis command causes the chuck (fig. 2, elm. 11, par. [0005], [0036]) to be moved by a third drive part (fig. 2, elm. 13, par. [0005], [0036]) included in the device arrangement part (fig. 2, elm. 12, par. [0036]) so that the semiconductor device (fig. 2, elm. 10, par. [0009]) overlaps the optical scanning region of the first optical system (fig. 2, elm. 21, par. [0028]) and the optical scanning region of the second optical system (fig. 2, elm. 22, par. [0028]) of the second optical system then causes the semiconductor device to be analyzed (par. [0026]-[0028]).
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding Claim 8, Suzuki and Takasu discloses the semiconductor fault analysis device according to claim 6, Suzuki discloses wherein the first light source (fig. 1, light source 12A, par. [0077]) and the second light source (fig. 1, laser light source 35, par. [0040]) output laser light having a wavelength band in which the semiconductor device (fig. 1, semiconductor device D, par. [0077]) does not generate a charge.
Regarding Claim 9, Suzuki and Takasu discloses the semiconductor fault analysis device according to claim 6, Suzuki discloses wherein the control part (fig. 1, computer 21, par. [0032]) causes the semiconductor device (fig. 1, semiconductor device D, par. [0077]) to be irradiated with light from both the first analysis part and the second analysis part, and outputs an analysis command that receives an electrical signal from the semiconductor device by the electrical signal acquisition part (fig. 5, electric signal detector 52, par. [0078]), to the first analysis part (fig. 1, observation optical system 13, par. [0031]), the second analysis part (fig. 1, laser light source 31, par. [0040]) the electrical signal acquisition part, and the device arrangement part (40).
Regarding Claim 10, Suzuki discloses a semiconductor fault analysis device (fig. 1, inspection system 1, par. [0028]) comprising: a first analysis part (fig. 1, observation optical system 13, par. [0031]) in which a semiconductor device (fig. 1, semiconductor device D, par. [0032]) is irradiated with light generated by a first light source (fig. 1, light source 12, par. [0033]) via a first optical system part (fig. 1, two-dimensional camera 15, par. [0035]) having a first optical scanning part (fig. 1 optical scanning unit 16 , par. [0077]), and a first optical detection part (fig. 1, two-dimensional camera 15, par. [0035]) receives first response light from the semiconductor device generated according to the light of the first light source (par. [0049]); a second analysis part (fig. 1, laser light source 31, par. [0040]) in which the semiconductor device is irradiated with light generated by a second light source (fig. 1, laser light source 35, par. [0040]) via a second optical system (fig. 1, laser marking optical system 32, par. [0040]), a laser marking optical system (fig. 1, laser marking optical system 32, par. [0040]), having a second optical scanning part (fig. 1, optical scanning unit, par. [0047]), and a second optical detection part (fig. 1, imaging device 34, par. [0040]) receives second response light from the semiconductor device generated according to the light of the second light source (par. [0048]); a device arrangement part (fig. 1, sample stage 40, par. [0029], [0057]) having a chuck disposed between the first analysis part and the second analysis part to hold the semiconductor device; a stimulus signal application part (fig. 1, tester unit 11, par. [0032]) configured to apply a stimulus signal to the semiconductor device; and a control part (fig. 1, computer 21, par. [0031]) configured to output a command to the first analysis part (13), the second analysis part (31), the device arrangement part (40), and the stimulus signal application part (11), and wherein the control part (21) outputs an alignment command that outputs an analysis command that irradiates the semiconductor device with light from at least one of the first analysis part and the second analysis part and receives at least one of the first response light and the second response light from the semiconductor device with at least one of the first optical detection part (15) and the second optical detection part (34) in the stimulus signal is applied to the semiconductor device to the first analysis part, the second analysis part, the stimulus signal application part, and the device arrangement part (par. [0034]-[0037], [0047]-[0050]).
Suzuki does not disclose the chuck being moved relative to the first analysis part and the second analysis part.
Takasu discloses the chuck (fig. 2, elm. 11, par. [0005], [0036]) being moved relative to the first analysis part (fig. 2, elm. 21, par. [0028]) and the second analysis part (fig. 2, elm. 22, par. [0028]).
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding Claim 11, Suzuki and Takasu discloses the semiconductor fault analysis device according to claim 10, Takasu discloses wherein the analysis command causes the chuck (fig. 2, elm. 11, par. [0005], [0036]) to be moved by a third drive part (fig. 2, elm. 13, par. [0005], [0036]) included in the device arrangement part (fig. 2, elm. 12, par. [0036]) so that the semiconductor device (fig. 2, elm. 10, par. [0009]) overlaps the optical scanning region of the first optical system (fig. 2, elm. 21, par. [0028]) and the optical scanning region of the second optical system (fig. 1, laser marking optical system 32, par. [0040]) of the second optical system then causes the semiconductor device (fig. 2, elm. 10, par. [0009]) to be analyzed.
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding Claim 12, Suzuki and Takasu discloses the semiconductor fault analysis device according to claim 10, Suzuki discloses wherein the stimulus signal application part (fig. 1, tester unit 11, par. [0032]) applies a stimulus signal having a predetermined modulation frequency (par. [0032]) to the semiconductor device (fig. 2, elm. 10, par. [0009]), the control part (fig. 1, computer 21, par. [0031]) extracts a signal component having a predetermined frequency based on at least one from the first response light and the second response light, then displays as a passage of time of the signal component or a two-dimensional mapping of the signal component (par. [0037]-[0038]).
Regarding Claim 13, Suzuki and Takasu discloses the semiconductor fault analysis device according to claim 10, wherein the control part (fig. 1, computer 21, par. [0031]) outputs an analysis command that irradiates the semiconductor device (fig. 2, elm. 10, par. [0009]) with light from both the first analysis part (fig. 1, observation optical system 13, par. [0031]) and the second analysis part (fig. 1, laser light source 31, par. [0040]), in a state in which the stimulus signal (stimulus signal, par. [0032]) is applied to the semiconductor device, and receives at least one of the first response light and the second response light from the semiconductor device by the first optical detection part (fig. 1, two-dimensional camera 15, par. [0035]) and the second optical detection part, to the first analysis part, the second analysis part, the stimulus signal application part, and the device arrangement part.
Regarding Claim 14, A semiconductor fault analysis method using a semiconductor fault analysis device (fig. 1, inspection system 1, par. [0028]) for analyzing a semiconductor device (fig. 1, semiconductor device D, par. [0032]), the semiconductor fault analysis device comprising: a first analysis part (fig. 1, observation optical system 13, par. [0031]) in which a first optical detection part (fig. 1, two-dimensional camera 15, par. [0035]) receives light emitted by a semiconductor device via a first optical system, and the first optical system is moved relative to the semiconductor device by a first drive part (fig. 1, XYZ stage 14, par. [0034]); a second analysis part (fig. 1, laser light source 31, par. [0040]) in which a second optical detection part fig. 1, imaging device 34, par. [0040]) receives light emitted by the semiconductor device via a second optical system (fig. 1, laser marking optical system 32, par. [0040]), and the second optical system is moved relative to the semiconductor device by a second drive part (fig. 1, XYZ stag 33, par. [0045]); a device arrangement part (fig. 1, sample stage 40, par. [0029]) having a chuck disposed between the first analysis part and the second analysis part to hold the semiconductor device (see fig. 1); a stimulus signal application part (fig. 1, tester unit 11, par. [0031]) configured to apply a stimulus signal to the semiconductor device; and a control part (fig. 1, computer 21, par. [0032]) configured to output a command to the first analysis part, the second analysis part, the device arrangement part, and the stimulus signal application part, wherein the semiconductor fault analysis method includes a step of applying the stimulus signal to the semiconductor device, and a step of receiving light from the semiconductor device emitted according to the stimulus signal by at least one of the first optical detection part and the second optical detection part (par. [0045]-[0055]).
Suzuki does not disclose the chuck being moved relative to the first analysis part and the second analysis part.
Takasu discloses the chuck (fig. 2, elm. 11, par. [0005], [0036]) being moved relative to the first analysis part (fig. 2, elm. 21, par. [0028]) and the second analysis part (fig. 2, elm. 22, par. [0028]).
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding Claim 15, Suzuki and Takasu discloses the semiconductor fault analysis method according to claim 14, Takasu discloses further comprising a step of causing the chuck (fig. 2, elm. 11, par. [0005], [0036]) to be moved by a third drive part (fig. 2, elm. 13, par. [0005], [0036]) included in the device arrangement part (fig. 2, elm. 12, par. [0036]) so that the semiconductor device (fig. 2, elm. 10, par. [0009]) overlaps the optical axis of the first optical system (fig. 2, elm. 21, par. [0028]) and the optical axis of the second optical system (fig. 1, laser marking optical system 32, par. [0040]), before the step of applying the stimulus signal.
Regarding Claim 16, Suzuki and Takasu discloses the semiconductor fault analysis method according to claim 14, Suzuki discloses wherein light from the semiconductor device is received by a first infrared camera (fig. 7, camera 15B, par. [0071]) that is the first optical detection part (fig. 1, two-dimensional camera 15, par. [0035]) and a second camera that is the second optical detection part (fig. 1, imaging device 34, par. [0040]), in the step of receiving light from the semiconductor device (fig. 1, semiconductor device D, par. [0032]).
Suzuki and Takasu do not disclose a second infrared camera. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a second infrared camera, since it has been held that the mere duplication of the essential working parts of a device involves only routine skill in the art. See St. Regis Paper Co. v. Bemis Co., 193 USPQ 8 and MPEP 2144.04.
Regarding Claim 18, Suzuki and Takasu discloses the semiconductor fault analysis method according to claim 14, Suzuki discloses wherein the light from the semiconductor device (fig. 1, semiconductor device D, par. [0032]) emitted according to the stimulus signal is received with both the first optical detection part (fig. 1, two-dimensional camera 15, par. [0035]) and the second optical detection part (fig. 1, imaging device 34, par. [0040]), in the step of receiving light from the semiconductor device.
Regarding Claim 19, Suzuki discloses a semiconductor fault analysis method using a semiconductor fault analysis device(fig. 1, inspection system 1, par. [0028]) for analyzing a semiconductor device (fig. 1, semiconductor device D, par. [0032]), the semiconductor fault analysis device comprising: a first analysis part (fig. 1, observation optical system 13, par. [0031]) configured to irradiate a semiconductor device with light generated by a first light source(fig. 1, light source 12, par. [0033]) via a first optical system (fig. 1, two-dimensional camera 15, par. [0035]) having a first optical scanning part (fig. 6, optical scanning unit 16, par. [0076]); a second analysis part (fig. 1, laser light source 31, par. [0040]) configured to irradiate the semiconductor device with light generated by a second light source (fig. 1, laser light source 35, par. [0040]) via a second optical system (fig. 1, elm. 32, par. [0042]) having a second optical scanning part (fig. 1, optical scanning unit, par. [0047]); a device arrangement part (fig. 1, sample stage 40, par. [0029], [0057]) having a chuck disposed between the first analysis part and the second analysis part to hold the semiconductor device (see fig. 1); an electrical signal acquisition part (fig. 5, electric signal detector 52, par. [0078]) configured to receive an electrical signal output by the semiconductor device (D); and a control part fig. 1, computer 21, par. [0032]) configured to output a command to the first analysis part, the second analysis part, the device arrangement part, and the electrical signal acquisition part (52), wherein the semiconductor fault analysis method comprises a step of irradiating the semiconductor device with light from at least one of the first analysis part (par. [0049]) and the second analysis part (par. [0034]), and a step of receiving an electrical signal from the semiconductor device by the electrical signal acquisition part (par. [0045]-[0055], [0077]-[0078]).
Suzuki does not disclose the chuck being moved relative to the first analysis part and the second analysis part.
Takasu discloses the chuck (fig. 2, elm. 11, par. [0005], [0036]) being moved relative to the first analysis part (fig. 2, elm. 21, par. [0028]) and the second analysis part (fig. 2, elm. 22, par. [0028]).
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding Claim 20, Suzuki and Takasu discloses the semiconductor fault analysis method according to claim 19, Takasu discloses further comprising a step of causing the chuck (fig. 2, elm. 11, par. [0005], [0036]) to be moved by a third drive part (fig. 2, elm. 13, par. [0005], [0036]) included in the device arrangement part (fig. 2, elm. 12, par. [0036]) so that the semiconductor device (fig. 2, elm. 10, par. [0009]) overlaps the optical scanning region of the first optical system (fig. 2, elm. 21, par. [0028]) and the optical scanning region of the second optical system (fig. 2, elm. 22, par. [0028]), before the step of irradiating the semiconductor device with light.
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding Claim 21, Suzuki and Takasu discloses the semiconductor fault analysis method according to claim 19, Suzuki discloses wherein laser light (fig. 1, light source 12A, par. [0077]) having a wavelength band in which the semiconductor device does not generate a charge is output from the first light source (fig. 1, laser light source 35, par. [0040]) and the second light source (fig. 1, laser light source 35, par. [0040]), in the step of irradiating the semiconductor device (fig. 1, semiconductor device D, par. [0077]) with light.
Regarding Claim 22, Suzuki and Takasu discloses semiconductor fault analysis method according to claim 19, Suzuki discloses wherein the semiconductor device (fig. 1, semiconductor device D, par. [0077]) is irradiated with light from both the first analysis part (fig. 1, observation optical system 13, par. [0031]), the second analysis part (fig. 1, laser light source 31, par. [0040]) in the step of irradiating the semiconductor device with light, and an electrical signal is received from the semiconductor device by the electrical signal acquisition part (fig. 5, electric signal detector 52, par. [0078]) in the step of receiving a step of receiving the electrical signal from the semiconductor device.
Regarding Claim 23, Suzuki discloses a semiconductor fault analysis method using a semiconductor fault analysis device (fig. 1, inspection system 1, par. [0028]) for analyzing a semiconductor device (fig. 1, semiconductor device D, par. [0032]), the semiconductor fault analysis device comprising: a first analysis part (fig. 1, observation optical system 13, par. [0031]) in which a semiconductor device is irradiated with light generated by a first light source (fig. 1, light source 12, par. [0033]) via a first optical system (fig. 1, observation optical system 13, par. [0031]) having a first optical scanning part (fig. 6, optical scanning unit 16, par. [0076]), and a first optical detection part (fig. 1, two-dimensional camera 15, par. [0035]) receives first response light from the semiconductor device generated according to the light of the first light source (par. [0049]); a second analysis part (fig. 1, laser light source 31, par. [0040]) in which the semiconductor device is irradiated with light generated by a second light source (fig. 1, laser light source 35, par. [0040]) via a second optical system (fig. 1, laser marking optical system 32, par. [0040]) having a second optical scanning part (fig. 1, optical scanning unit, par. [0047]), and a second optical detection part (fig. 1, imaging device 34, par. [0040]) receives second response light from the semiconductor device generated according to the light of the second light source; a device arrangement part (fig. 1, sample stage 40, par. [0029]) having a chuck disposed between the first analysis part and the second analysis part to hold the semiconductor device (see fig. 1); a stimulus signal application part (fig. 1, tester unit 11, par. [0031]) configured to apply a stimulus signal to the semiconductor device (D); and a control part (fig. 1, computer 21, par. [0032]) configured to output a command to the first analysis part, the second analysis part, the device arrangement part, and the stimulus signal application part, and wherein the semiconductor fault analysis method includes a step of irradiating the semiconductor device with light from at least one of the first analysis part and the second analysis part in a state in which the stimulus signal is applied to the semiconductor device, and a step of receiving at least one of the first response light and the second response light from the semiconductor device by at least one of the first optical detection part and the second optical detection part (par. [0034]-[0037], [0047]-[0050]).
Suzuki does not disclose the chuck being moved relative to the first analysis part and the second analysis part.
Takasu discloses the chuck (fig. 2, elm. 11, par. [0005], [0036]) being moved relative to the first analysis part (fig. 2, elm. 21, par. [0028]) and the second analysis part (fig. 2, elm. 22, par. [0028]).
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding Claim 24, Suzuki and Takasu discloses the semiconductor fault analysis method according to claim 23, Takasu discloses further comprising a step of causing the chuck (fig. 2, elm. 11, par. [0005], [0036]) to be moved by a third drive part (fig. 2, elm. 13, par. [0005], [0036]) included in the device arrangement part (fig. 2, elm. 12, par. [0036]) so that the semiconductor device (fig. 2, elm. 10, par. [0009]) overlaps the optical scanning region of the first optical system (fig. 2, elm. 21, par. [0028]) and the optical scanning region of the second optical system (fig. 2, elm. 22 par. [0028]) , before the step of irradiating the semiconductor device with light.
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding Claim 25, Suzuki and Takasu discloses the semiconductor fault analysis method according to claim 23, Suzuki discloses further comprising a step of applying a stimulus signal (fig. 1, tester unit 11, par. [0032]) having a predetermined modulation frequency (par. [0032]) to the semiconductor device (fig. 2, elm. 10, par. [0009]), before the step of irradiating the semiconductor device with light (par. [0034]), and a step of extracting a signal component having a predetermined frequency, based on at least one from the first response light and the second response light then displaying as a passage of time of the signal component or a two-dimensional mapping of the signal component before the step of receiving at least one of the first response light and the second response light from the semiconductor device (par. [0037]-[0038]).
Regarding Claim 26, Suzuki and Takasu discloses semiconductor fault analysis method according to claim 23, Suzuki discloses, wherein the semiconductor device (fig. 1, semiconductor device D, par. [0077]) is irradiated with light from both the first analysis part (fig. 1, observation optical system 13, par. [0031]), the second analysis part (fig. 1, laser light source 31, par. [0040]), in the step of irradiating the semiconductor device with light.
Claim(s) 4 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki in view of Takasu as applied to claim 3/16 above, and further in view of Deslandes KR20170040778 A.
Regarding Claim 4, Suzuki and Takasu discloses the semiconductor fault analysis device according to claim 3, Suzuki and Takasu do not disclose infrared camera detect light having a wavelength of 2 µm to 10 µm.
Deslandes discloses infrared camera detect light having a wavelength of 2 µm to 10 µm. (par. [0037]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide cameras with MCT (Mercury Cadmium Telluride, HgCdTe) detector arrays, as taught in Deslandes in modifying the apparatus of Suzuki and Takasu. The motivation would be they have a desirable (uniform and broad) response over short and medium IR spectra (see Deslandes: par. [0037]).
Regarding Claim 17, Suzuki and Takasu discloses the semiconductor fault analysis method according to claim 16, Suzuki discloses the first infrared camera (fig. 7, camera 15B, par. [0071]) that is the first optical detection part (fig. 1, two-dimensional camera 15, par. [0035]) and the second infrared camera that is the second optical detection part (fig. 1, imaging device 34, par. [0040]), in the step of receiving light from the semiconductor device (fig. 1, semiconductor device D, par. [0032]).
Deslandes discloses disclose wherein light having a wavelength of 2 pm to 10 pm is detected by the first and second infrared cameras (see Deslandes: par. [0037]).
The references are combined for the same reason already applied in the rejection of claim 4.
Conclusion
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/COURTNEY G MCDONNOUGH/ Examiner, Art Unit 2858
/EMAN A ALKAFAWI/ Supervisory Patent Examiner, Art Unit 2858 7/15/2026
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