Prosecution Insights
Last updated: July 17, 2026
Application No. 18/795,647

AUTHENTICATED STATELESS MOUNT STRING FOR A DISTRIBUTED FILE SYSTEM

Final Rejection §102
Filed
Aug 06, 2024
Priority
Aug 20, 2018 — provisional 62/719,916 +3 more
Examiner
MCMAHON, DANIEL F
Art Unit
2111
Tech Center
2100 — Computer Architecture & Software
Assignee
Weka Io Ltd.
OA Round
2 (Final)
90%
Grant Probability
Favorable
3-4
OA Rounds
2m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
926 granted / 1034 resolved
+34.6% vs TC avg
Minimal +2% lift
Without
With
+2.3%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
24 currently pending
Career history
1048
Total Applications
across all art units

Statute-Specific Performance

§101
4.3%
-35.7% vs TC avg
§103
56.4%
+16.4% vs TC avg
§102
20.8%
-19.2% vs TC avg
§112
11.2%
-28.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1034 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This action is in response to amendments and remarks received 05/07/2026. Claims 1 – 20 are cancelled. Claims 21 – 40 are new. Claims 21 – 40 are pending. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Claims 21 – 40 are rejected on the ground of nonstatutory double patenting over claims 1 – 20 of U.S. Patent No. 12,086,452 since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent. The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows: Claim 21 – Application 18/795647 Claim 1 – Patent 12,086,452 A system comprising: A system comprising: a first processor; and a plurality of storage devices operable to a plurality of storage devices, wherein: the first processor is operable to build a plurality of failure-protected stripes, maintain each block of a plurality of blocks, of a failure-protected stripe, in a different storage device of the plurality of storage devices; and each failure-protected stripe comprise a plurality of storage blocks, each storage block of a failure-protected stripe is located in a different storage device of the plurality of storage devices, and a processor operable to access the failure-protected stripe according to a stateless mount string. the plurality of failure-protected stripes is accessible, via a second processor, according to a stateless mount string. One of ordinary skill in the art would clearly recognize independent claim 1, of application 18/795647 is an obvious variation of the claimed subject matter of independent claim 1, of patent 12,086,452. Specifically, both claim 21, of the current application 18/795647, and claim 1, of patent 12,086,452 discloses: A system, comprising “a plurality of storage devices”, “a failure-protected stripe, in a different storage device of the plurality of storage devices” and a “stateless mount string”. One of ordinary skill in the art would recognize the system disclosed by claim 21, of the current application 18/795647, as a broad recitation of the operations performed by the system disclosed in claim 1 of Patent 12,086,452. A system performing operations and a system capable of performing the disclosed operations would be recognize by one of ordinary skill in the art as obvious variants of each other. Therefore, one of ordinary skill in the art would recognize the system of claim 21, of the current application 18/795647, as performing the operations of the system of claim 1, of U.S. Patent 12,086,452, and as such are obvious variants of each other. Claim 22 – Application 18/795647 Claim 2 – Patent 12,086,452 Claim 23 – Application 18/795647 Claim 3 – Patent 12,086,452 Claim 24 – Application 18/795647 Claim 4 – Patent 12,086,452 Claim 25 – Application 18/795647 Claim 5 – Patent 12,086,452 Claim 26 – Application 18/795647 Claim 6 – Patent 12,086,452 Claim 27 – Application 18/795647 Claim 7 – Patent 12,086,452 Claim 28 – Application 18/795647 Claim 8 – Patent 12,086,452 Claim 29 – Application 18/795647 Claim 9 – Patent 12,086,452 Claim 30 – Application 18/795647 Claim 10 – Patent 12,086,452 Claim 31 – Application 18/795647 Claim 11 – Patent 12,086,452 Claim 32 – Application 18/795647 Claim 12 – Patent 12,086,452 Claim 33 – Application 18/795647 Claim 13 – Patent 12,086,452 Claim 34 – Application 18/795647 Claim 14 – Patent 12,086,452 Claim 35 – Application 18/795647 Claim 15 – Patent 12,086,452 Claim 36 – Application 18/795647 Claim 16 – Patent 12,086,452 Claim 37 – Application 18/795647 Claim 17 – Patent 12,086,452 Claim 38 – Application 18/795647 Claim 18 – Patent 12,086,452 Claim 39 – Application 18/795647 Claim 19 – Patent 12,086,452 Claim 40 – Application 18/795647 Claim 20 – Patent 12,086,452 Claims 21 – 40 are rejected on the ground of nonstatutory double patenting over claims 1 – 20 of U.S. Patent No. 11,693,581 since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent. The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows: Claim 21 – Application 18/795647 Claim 1 – Patent 11,693,581 A system comprising: A system comprising: a local computing device; and a plurality of storage devices operable to a plurality of storage devices, wherein: maintain each block of a plurality of blocks, of a failure-protected stripe, in a different storage device of the plurality of storage devices; and a computing device is operable to build a plurality of failure-protected stripes, each failure-protected stripe comprise a plurality of storage blocks, each storage block of a failure-protected stripe is located in a different storage device of the plurality of storage devices, the plurality of failure-protected stripes is accessible by a first external computing device, and a processor operable to access the failure-protected stripe according to a stateless mount string. a request, to access the plurality of failure-protected stripes, comprises a stateless mount string. One of ordinary skill in the art would clearly recognize independent claim 1, of application 18/795647 is an obvious variation of the claimed subject matter of independent claim 1, of patent 11,693,581. Specifically, both claim 21, of the current application 18/795647, and claim 1, of patent 11,693,581 discloses: A system, comprising “a plurality of storage devices”, “a failure-protected stripe, in a different storage device of the plurality of storage devices” and a “stateless mount string”. One of ordinary skill in the art would recognize the system disclosed by claim 21, of the current application 18/795647, as a broad recitation of the operations performed by the system disclosed in claim 1 of Patent 11,693,581. A system performing operations and a system capable of performing the disclosed operations would be recognize by one of ordinary skill in the art as obvious variants of each other. Therefore, one of ordinary skill in the art would recognize the system of claim 21, of the current application 18/795647, as performing the operations of the system of claim 1, of U.S. Patent 11,693,581, and as such are obvious variants of each other. Claim 22 – Application 18/795647 Claim 2 – Patent 11,693,581 Claim 23 – Application 18/795647 Claim 3 – Patent 11,693,581 Claim 24 – Application 18/795647 Claim 4 – Patent 11,693,581 Claim 25 – Application 18/795647 Claim 5 – Patent 11,693,581 Claim 26 – Application 18/795647 Claim 6 – Patent 11,693,581 Claim 27 – Application 18/795647 Claim 7 – Patent 11,693,581 Claim 28 – Application 18/795647 Claim 8 – Patent 11,693,581 Claim 29 – Application 18/795647 Claim 9 – Patent 11,693,581 Claim 30 – Application 18/795647 Claim 10 – Patent 11,693,581 Claim 31 – Application 18/795647 Claim 11 – Patent 11,693,581 Claim 32 – Application 18/795647 Claim 12 – Patent 11,693,581 Claim 33 – Application 18/795647 Claim 13 – Patent 11,693,581 Claim 34 – Application 18/795647 Claim 14 – Patent 11,693,581 Claim 35 – Application 18/795647 Claim 15 – Patent 11,693,581 Claim 36 – Application 18/795647 Claim 16 – Patent 11,693,581 Claim 37 – Application 18/795647 Claim 17 – Patent 11,693,581 Claim 38 – Application 18/795647 Claim 18 – Patent 11,693,581 Claim 39 – Application 18/795647 Claim 19 – Patent 11,693,581 Claim 40 – Application 18/795647 Claim 20 – Patent 11,693,581 Claims 21 – 40 are rejected on the ground of nonstatutory double patenting over claims 1 – 20 of U.S. Patent No. 11,340,823 since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent. The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows: Claim 21 – Application 18/795647 Claim 1 – Patent 11,340,823 A system comprising: A file system comprising: a cluster of one or more computing devices; and a plurality of storage devices operable to a plurality of storage devices, wherein: maintain each block of a plurality of blocks, of a failure-protected stripe, in a different storage device of the plurality of storage devices; and each computing device of the cluster is operable to build one or more failure-protected stripes, each failure-protected stripe comprises a plurality of storage blocks, each storage block of a failure-protected stripe is located in a different storage device of the plurality of storage devices, and a processor operable to access the failure-protected stripe according to a stateless mount string. a first client other than the one or more computing devices of the cluster is operable to request access to a first portion of the file system via a first stateless mount string. One of ordinary skill in the art would clearly recognize independent claim 1, of application 18/795647 is an obvious variation of the claimed subject matter of independent claim 1, of patent 11,340,823. Specifically, both claim 21, of the current application 18/795647, and claim 1, of patent 11,340,823 discloses: A system, comprising “a plurality of storage devices”, “a failure-protected stripe, in a different storage device of the plurality of storage devices” and a “stateless mount string”. One of ordinary skill in the art would recognize the system disclosed by claim 21, of the current application 18/795647, as a broad recitation of the operations performed by the system disclosed in claim 1 of Patent 11,340,823. A system performing operations and a system capable of performing the disclosed operations would be recognize by one of ordinary skill in the art as obvious variants of each other. Therefore, one of ordinary skill in the art would recognize the system of claim 21, of the current application 18/795647, as performing the operations of the system of claim 1, of U.S. Patent 11,340,823, and as such are obvious variants of each other. Claim 22 – Application 18/795647 Claim 2 – Patent 11,340,823 Claim 23 – Application 18/795647 Claim 3 – Patent 11,340,823 Claim 24 – Application 18/795647 Claim 4 – Patent 11,340,823 Claim 25 – Application 18/795647 Claim 5 – Patent 11,340,823 Claim 26 – Application 18/795647 Claim 6 – Patent 11,340,823 Claim 27 – Application 18/795647 Claim 7 – Patent 11,340,823 Claim 28 – Application 18/795647 Claim 8 – Patent 11,340,823 Claim 29 – Application 18/795647 Claim 9 – Patent 11,340,823 Claim 30 – Application 18/795647 Claim 10 – Patent 11,340,823 Claim 31 – Application 18/795647 Claim 11 – Patent 11,340,823 Claim 32 – Application 18/795647 Claim 12 – Patent 11,340,823 Claim 33 – Application 18/795647 Claim 13 – Patent 11,340,823 Claim 34 – Application 18/795647 Claim 14 – Patent 11,340,823 Claim 35 – Application 18/795647 Claim 15 – Patent 11,340,823 Claim 36 – Application 18/795647 Claim 16 – Patent 11,340,823 Claim 37 – Application 18/795647 Claim 17 – Patent 11,340,823 Claim 38 – Application 18/795647 Claim 18 – Patent 11,340,823 Claim 39 – Application 18/795647 Claim 19 – Patent 11,340,823 Claim 40 – Application 18/795647 Claim 20 – Patent 11,340,823 Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 21 – 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al., U.S. Publication 2022/0019505 (herein Lee). Regarding claims 21 and 31, claim 21 as representative, Lee discloses: A system comprising: a plurality of storage devices operable to maintain each block of a plurality of blocks, of a failure-protected stripe, in a different storage device of the plurality of storage devices (figure 1A, element 170A; paragraph 0074, 0238 “Data is laid out or distributed across multiple storage nodes in data fragments or stripes that support data recovery in some embodiments”); anda processor operable to access the failure-protected stripe according to a stateless mount string (paragraph 0107, 0108 “Because authorities 168 are stateless, they can migrate between blades 252. Each authority 168 has a unique identifier. NVRAM 204 and flash 206 partitions are associated with authorities' 168 identifiers” would be understood as a “stateless mount string”). Regarding claims 22 and 32, claim 22 as representative, Lee discloses: an access to the failure- protected stripe is granted independently of any previous requests by the processor (paragraph 0028, “storage array controller 110A-D may be independently coupled to the LAN”). Regarding claims 23 and 33, claim 23 as representative, Lee discloses: a plurality of processors is operable to access the failure-protected stripe concurrently (paragraph 0106, “regardless of client access pattern, and maximizes concurrency by eliminating much of the need for inter-blade coordination that typically occurs with conventional distributed locking”). Regarding claims 24 and 34, claim 24 as representative, Lee discloses: the plurality of processors is mapped to a common user identification number (paragraph 0107, 0108 “authorities”). Regarding claims 25 and 35, claim 25 as representative, Lee discloses: access to the failure- protected stripe is exclusive to the processor (paragraph 0070, “reservation or exclusion primitives may be provided”). Regarding claims 26 and 36, claim 26 as representative, Lee discloses: the stateless mount string is encrypted by a cryptographically-signed key (paragraph 0123 “may make use of Key Management-as-a-Service (‘KMaaS’) to manage encryption keys, keys for locking and unlocking storage devices”). Regarding claims 27 and 37, claim 27 as representative, Lee discloses: the stateless mount string comprises data encrypted by a cryptographically-signed key (paragraph 0123, “the storage systems may encrypt data at rest”). Regarding claims 28 and 38, claim 28 as representative, Lee discloses: the stateless mount string encapsulates one or more authentication parameters (paragraph 0107 “the authorities store every update in their NVRAM 204 partitions”). Allowable Subject Matter Claims 29, 30, 39, and 40 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest Prior Arts of Record KARR; RONALD et al. US 20180357019 A1 a plurality of storage devices operable to maintain each block of a plurality of blocks, of a failure-protected stripe, in a different storage device of the plurality of storage devices (paragraph 0176) a processor operable to access the failure-protected stripe according to a stateless mount string (paragraph 0093) BESTLER; Caitlin et al. US 20160057226 A1 a plurality of storage devices operable to maintain each block of a plurality of blocks, of a failure-protected stripe, in a different storage device of the plurality of storage devices (paragraph 0746) a processor operable to access the failure-protected stripe according to a stateless mount string (paragraph 0651) Lee; Robert et al. US 20210382800 A1 a plurality of storage devices operable to maintain each block of a plurality of blocks, of a failure-protected stripe, in a different storage device of the plurality of storage devices (paragraph 0002) a processor operable to access the failure-protected stripe according to a stateless mount string (paragraph 00139) Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Bernat; Andrew et al. US 11112990 B1 Noveck; David et al. US 5218695 A Uppala; Radha Krishna US 7447839 B2 Lee; Robert et al. US 20220019505 A1 a plurality of storage devices operable to maintain each block of a plurality of blocks, of a failure-protected stripe, in a different storage device of the plurality of storage devices Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL F MCMAHON whose telephone number is (571)270-3232. The examiner can normally be reached Monday-Thursday 9am - 5pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571)270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Daniel F. McMahon/Primary Examiner, Art Unit 2111
Read full office action

Prosecution Timeline

Aug 06, 2024
Application Filed
Dec 19, 2025
Non-Final Rejection mailed — §102
Feb 24, 2026
Response after Non-Final Action
Feb 24, 2026
Response Filed
May 07, 2026
Response Filed
Jul 07, 2026
Final Rejection mailed — §102 (current)

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Prosecution Projections

3-4
Expected OA Rounds
90%
Grant Probability
92%
With Interview (+2.3%)
2y 1m (~2m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1034 resolved cases by this examiner. Grant probability derived from career allowance rate.

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