Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of Claims
1. Applicant's submittal of claims 1-11 in the “Claims” filed on 08/06/2024 is acknowledged and entered by the Examiner.
This office action consider claims 1-11 pending for prosecution.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (100; Fig 3A; [0063]) = (element 100; Figure No. 3A; Paragraph No. [0063]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
2. Claims 1, 5, and 8 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by
Hshieh (US 20080042208 A1; hereinafter Hshieh).
Regarding claim 1, Hshieh teaches a capacitor (see the entire document, specifically Figs. 11-13; [0023+], and as cited below; see alternative rejection for claim 1, below), comprising:
a semiconductor surface layer ({1105}; Fig. 13 in view of Figs. 11-12; see [0023-0024]) of a substrate ({1100}; Fig. 13 in view of Figs. 11-12; see [0023-0024]);
a doped polysilicon layer (1125; Fig. 13 in view of Figs. 11-12; [0024]) over the semiconductor surface layer ({1105}; Fig. 13 in view of Figs. 11-12; see [0023-0024]);
a dielectric layer (1130; Fig. 13; [0025]) on the doped polysilicon layer (1125; Fig. 13 in view of Figs. 11-12; [0024]); and
an undoped polysilicon layer (1135; Fig. 13; [0025]; undoped polysilicon layer 1135 is deposited on the thick oxide layer 1130) on the dielectric layer (1130; Fig. 13; [0025]).
Regarding claim 5, modified Hshieh (by Lin) teaches all of the features of claim 1.
Modified Hshieh (by Lin) further wherein the substrate ({1100}; Fig. 13 in view of Figs. 11-12; see [0023-0024]) is a semiconductor substrate, and the semiconductor surface layer ({1105}; Fig. 13 in view of Figs. 11-12; see [0023-0024]) comprises an epitaxial semiconductor surface layer ({1105}; Fig. 13 in view of Figs. 11-12; see [0023-0024]) located on the semiconductor substrate, the epitaxial semiconductor surface layer ({1105}; Fig. 13 in view of Figs. 11-12; see [0023-0024]) having a doping level that is less than a doping level of the semiconductor substrate ({1100}; Fig. 13 in view of Figs. 11-12; see [0023-0024])
Regarding claim 8, Hshieh teaches a capacitor (see the entire document, specifically Figs. 11-17; [0023+], and as cited below), comprising:
a semiconductor substrate ({1100}; Fig. 17 in view of Figs. 11-16; see [0023-0024]);
a semiconductor surface layer ({1105}; Fig. 17 in view of Figs. 11-16; see [0023-0024]) on the semiconductor substrate ({1100}; Fig. 17 in view of Figs. 11-16; see [0023-0024]);
an integrated trench capacitor (Fig. 17 in view of Figs. 11-16; see [0023-0029])
comprising:
a plurality of trenches (Fig. 17 in view of Fig. 11; see [0023]) in the semiconductor surface layer ({1105}; Fig. 17 in view of Figs. 11-16; see [0023-0024]);
a first dielectric layer ({1110}; Fig. 17 in view of Fig. 12; see [0024]) that lines respective surfaces of the plurality of trenches;
a doped polysilicon layer (1125; Fig. 17 in view of Fig. 12; [0024]) on the first dielectric layer ({1110}; Fig. 17 in view of Fig. 12; see [0024]);
a second dielectric layer (1130; Fig. 17 in view of Fig. 13; [0025]) on the doped polysilicon layer (1125; Fig. 17 in view of Fig. 12; [0024]); and
an undoped polysilicon layer (1135; Fig. 17 in view of Fig. 13; [0025]; undoped polysilicon layer 1135 is deposited on the thick oxide layer 1130) on the second dielectric layer (1130; Fig. 17 in view of Fig. 13; [0025]); and
a top side metal contacts (1145; Fig. 17; [0029])coupled to the doped polysilicon layer (1125; Fig. 17 in view of Fig. 12; [0024]) in regions lateral to the plurality of trenches.
3. Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by
Gluschenkov et al. (US 6838334 B1; hereinafter Gluschenkov). Regarding claim 1, Gluschenkov teaches a capacitor (see the entire document, specifically Figs. 1A+; C2 L17+, and as cited below; see alternative rejection for claim 1, above), comprising:
a semiconductor surface layer of a substrate ({100, 140}; see Fig. 1N in view Figs. 1A-1M; see C2 L17-34);
a doped polysilicon layer (155; see Fig. 1N in view Figs. 1A-1M; C3 L5-6; doped polysilicon) over the semiconductor surface layer ({100, 140} see C2 L17-34);
a dielectric layer ({190, 165}; see Fig. 1N in view Figs. 1L-1M; see C4 L34-34, where layer 165 is converted into layer 190)on the doped polysilicon layer (155; see Fig. 1N in view Figs. 1A-1M; C3 L5-6; doped polysilicon); and
an undoped polysilicon layer (195; Fig. 1N; C4 L43-46; polysilicon layer 195) on the dielectric layer ({190, 165}; see Fig. 1N in view Figs. 1L-1M; see C4 L34-34, where layer 165 is converted into layer 190).
Regarding claim 6, Gluschenkov teaches all of the features of claim 1.
Gluschenkov further teaches wherein the dielectric layer (165; Fig. 1E; C3 L26-32) comprises a tetraethoxysilane (TEOS)-derived oxide material (C3 L26-32; tetraethoxysilane (TEOS) oxide).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
4. Claims 2 and 3 are rejected under 35 U.S.C.103 as being unpatentable over Hshieh (US 20080042208 A1; hereinafter Hshieh), in view of Lin (US 20160020267 A1; hereinafter Lin).
Regarding claim 2, Hshieh teaches all of the features of claim 1.
But, Hshieh does not expressly teach “wherein the dielectric layer is a first dielectric layer, the capacitor further comprising: a plurality of trenches in the semiconductor surface layer of the substrate; a second dielectric layer that lines respective surfaces of the plurality of trenches, the doped polysilicon layer being on the second dielectric layer and the undoped polysilicon layer being on the first dielectric layer to fill the plurality of trenches”.
However, in the analogous art, Lin teaches an integrated circuit ([0003]), wherein (Fig. 1A+; [0003+]) a semiconductor substrate (300; Fig. 5A; [0029])) with a doping region (400; [0030]). Trenches (500; Fig. 5A; [0031]) are formed in the doping region (400; [0030]). A first dielectric layer (600; Fig. 6; [0033]) is formed over the respective sidewalls and bottom portions of the trenches via a thermal oxidation can be carried out to form a thin oxide layer. a first conductive layer (700; Fig. 7; [0034]), such as a poly1 layer is formed over the first dielectric layer (600; Fig. 6; [0033]). A second dielectric layer (800; Fig. 8; [0035]) is formed in the trenches over the first conductive layer. A second conductive layer (900; Fig. 9; [0036]), such as a poly2 layer is formed over the second dielectric layer. After the second conductive layer (900; Fig. 9; [0036]) is formed, a photoresist mask (not shown) or other mask in formed, and an etch is carried out with the mask in place to form sidewalls (902a, 902b; Fig. 8; [0036]), which exposed the second dielectric layer (800; Fig. 9). An interconnect structure (1100; Fig. 11; [0038]), where contacts (1102h) and a metal1 layer 1104 are in contact with an exposed surface of dielectric layer (800; Fig. 11).
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lin’s structural layers into Hshieh’s device, and thereby, modified Hshieh’s (by Lin) device will have wherein the dielectric layer (1130; Fig. 13; [0025]) is a first dielectric layer, the capacitor further comprising: a plurality of trenches (Hshieh see Fig. 11; [0023] in view of Lin 500; Fig. 5A; [0031]) in the semiconductor surface layer of the substrate (Hshieh {1100, 1105} see [0023]); a second dielectric layer (in view of Lin 600; Fig. 6; [0033]) that lines respective surfaces of the plurality of trenches (Hshieh see Fig. 11; [0023] in view of Lin 500; Fig. 5A; [0031]), the doped polysilicon layer (Hshieh 1125; Fig. 13 in view of Figs. 11-12; [0024]) being on the second dielectric layer (in view of Lin 600; Fig. 6; [0033]) and the undoped polysilicon layer (Hshieh 1135; Fig. 13; [0025]; undoped polysilicon layer 1135 in view of Lin 900; Fig. 9; [0036]; undoped polysilicon layer 900) being on the first dielectric layer (in view of Lin 800; Fig. 8; [0035]) to fill the plurality of trenches (in view of Lin see Fig. 9; [0036]).
The ordinary artisan would have been motivated to modify Hshieh in the manner set forth above, at least, because this inclusion provides an interconnect to be formed above the device structure, (Lin [0036, 0038]), which allows the device to connect to external devices or connections.
Regarding claim 3, modified Hshieh (by Lin) teaches all of the features of claim 2.
Modified Hshieh (by Lin) further comprising metal contacts (in view of Lin {1102h, 1104}; Fig. 11; [0038]) coupled to the doped polysilicon layer (Hshieh 1125; Fig. 13 in view of Figs. 11-12; [0024]) in the regions lateral to the plurality of trenches (in view of Lin Fig. 11; [0038]).
5. Claims 4 and 9 are rejected under 35 U.S.C.103 as being unpatentable over Hshieh (US 20080042208 A1; hereinafter Hshieh), in view of Jia (US 20190229181 A1; hereinafter Jia).
Regarding claim 4, Hshieh teaches all of the features of claim 3.
Hshieh does not expressly disclose a back side metal layer on a back side of the substrate opposite the semiconductor surface layer.
However, in the analogous art, Jia teaches integrated trench capacitors ([0002]), wherein (Fig. 1+; [0015+]) depositing a back side metal on the back side of the substrate to provide a solderable die attach metal stack to ensure good electrical contact to the back side of the chip (ohmic contact) or proper bonding of the chips to their mounting cases. The BSM layer can comprise gold or silver on titanium on nickel (Fig. 1; see [0022]; see Claim 8).
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Jia’s back side metal into Hshieh’s device, and thereby, modified Hshieh’s (by Jia) device will have a back side metal layer (Jia Fig. 1; see [0022]; see Claim 8) on a back side of the substrate ({1100}; Fig. 13 in view of Figs. 11-12; see [0023-0024]) opposite the semiconductor surface layer ({1105}; Fig. 13 in view of Figs. 11-12; see [0023-0024]).
The ordinary artisan would have been motivated to modify Hshieh in the manner set forth above, at least, because this inclusion provides a back side metal on the back side of the substrate to provide a solderable die attach metal stack to ensure good electrical contact to the back side of the chip (ohmic contact) or proper bonding of the chips to their mounting cases (Jia [0022]), which allows the device to connect to external devices or connections.
Regarding claim 9, Hshieh teaches all of the features of claim 8.
Hshieh does not expressly disclose a back side metal layer on a back side of the substrate opposite the semiconductor surface layer.
However, in the analogous art, Jia teaches integrated trench capacitors ([0002]), wherein (Fig. 1+; [0015+]) depositing a back side metal on the back side of the substrate to provide a solderable die attach metal stack to ensure good electrical contact to the back side of the chip (ohmic contact) or proper bonding of the chips to their mounting cases. The BSM layer can comprise gold or silver on titanium on nickel (Fig. 1; see [0022]; see Claim 8).
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Jia’s back side metal into Hshieh’s device, and thereby, modified Hshieh’s (by Jia) device will have a back side metal layer (Jia Fig. 1; see [0022]; see Claim 8) on a back side of the substrate ({1100}; Fig. 13 in view of Figs. 11-12; see [0023-0024]) opposite the semiconductor surface layer ({1105}; Fig. 13 in view of Figs. 11-12; see [0023-0024]).
The ordinary artisan would have been motivated to modify Hshieh in the manner set forth above, at least, because this inclusion provides a back side metal on the back side of the substrate to provide a solderable die attach metal stack to ensure good electrical contact to the back side of the chip (ohmic contact) or proper bonding of the chips to their mounting cases (Jia [0022]), which allows the device to connect to external devices or connections.
6. Claims 7 and 11 are rejected under 35 U.S.C.103 as being unpatentable over Hshieh (US 20080042208 A1; hereinafter Hshieh), in view of the following statement.
Regarding claim 7, Hshieh teaches all of the features of claim 1.
Hshieh further teaches wherein the dielectric layer (1130; Fig. 13; [0025]) (see below for “has a thickness in a range between about 40 nm and about 120 nm”), the doped polysilicon layer (1125; Fig. 13 in view of Figs. 11-12; [0024]) (see below for “has a thickness in a range between about 250 nm and about 350 nm”), and the undoped polysilicon layer (1135; Fig. 13; [0025]; undoped polysilicon layer 1135 is deposited on the thick oxide layer 1130) (see below for “has a thickness in a range between about 650 nm and about 1000 nm”).
While Hshieh teaches a dielectric layer, a doped polysilicon layer, and an undoped polysilicon layer, Hshieh does not expressly disclose “wherein the dielectric layer has a thickness in a range between about 40 nm and about 120 nm, the doped polysilicon layer has a thickness in a range between about 250 nm and about 350 nm, and the undoped polysilicon layer has a thickness in a range between about 650 nm and about 1000 nm” (emphasis added).
However, it has been held that “wherein the dielectric layer has a thickness in a range between about 40 nm and about 120 nm, the doped polysilicon layer has a thickness in a range between about 250 nm and about 350 nm, and the undoped polysilicon layer has a thickness in a range between about 650 nm and about 1000 nm” will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating that the dielectric layer has a thickness in a range between about 40 nm and about 120 nm, the doped polysilicon layer has a thickness in a range between about 250 nm and about 350 nm, and the undoped polysilicon layer has a thickness in a range between about 650 nm and about 1000 nm is critical, “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation”. In re Aller, 220 F. 2d 454, 105 USPQ 233, 235 (CCPA 1955). In this case, there is nothing in the present application to indicate that the claimed wherein the dielectric layer has a thickness in a range between about 40 nm and about 120 nm, the doped polysilicon layer has a thickness in a range between about 250 nm and about 350 nm, and the undoped polysilicon layer has a thickness in a range between about 650 nm and about 1000 nm is critical and will achieve unexpected results over the range outside of the claimed range. Therefore, it would have been obvious to have wherein the dielectric layer has a thickness in a range between about 40 nm and about 120 nm, the doped polysilicon layer has a thickness in a range between about 250 nm and about 350 nm, and the undoped polysilicon layer has a thickness in a range between about 650 nm and about 1000 nm as claimed in device because having wherein the dielectric layer has a thickness in a range between about 40 nm and about 120 nm, the doped polysilicon layer has a thickness in a range between about 250 nm and about 350 nm, and the undoped polysilicon layer has a thickness in a range between about 650 nm and about 1000 nm can be optimized during routine experimentation depending upon a particular application which is desired.
The applicants have not established the criticality (see next paragraph below) of said first predetermined amount.
The specification contains no disclosure of either the critical nature of the claimed distance or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 11, Hshieh teaches all of the features of claim 8.
Hshieh further teaches wherein the dielectric layer (1130; Fig. 13; [0025]) (see below for “has a thickness in a range between about 40 nm and about 120 nm”), the doped polysilicon layer (1125; Fig. 13 in view of Figs. 11-12; [0024]) (see below for “has a thickness in a range between about 250 nm and about 350 nm”), and the undoped polysilicon layer (1135; Fig. 13; [0025]; undoped polysilicon layer 1135 is deposited on the thick oxide layer 1130) (see below for “has a thickness in a range between about 650 nm and about 1000 nm”).
While Hshieh teaches a dielectric layer, a doped polysilicon layer, and an undoped polysilicon layer, Hshieh does not expressly disclose “wherein the dielectric layer has a thickness in a range between about 40 nm and about 120 nm, the doped polysilicon layer has a thickness in a range between about 250 nm and about 350 nm, and the undoped polysilicon layer has a thickness in a range between about 650 nm and about 1000 nm” (emphasis added).
However, it has been held that “wherein the dielectric layer has a thickness in a range between about 40 nm and about 120 nm, the doped polysilicon layer has a thickness in a range between about 250 nm and about 350 nm, and the undoped polysilicon layer has a thickness in a range between about 650 nm and about 1000 nm” will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating that the dielectric layer has a thickness in a range between about 40 nm and about 120 nm, the doped polysilicon layer has a thickness in a range between about 250 nm and about 350 nm, and the undoped polysilicon layer has a thickness in a range between about 650 nm and about 1000 nm is critical, “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation”. In re Aller, 220 F. 2d 454, 105 USPQ 233, 235 (CCPA 1955). In this case, there is nothing in the present application to indicate that the claimed wherein the dielectric layer has a thickness in a range between about 40 nm and about 120 nm, the doped polysilicon layer has a thickness in a range between about 250 nm and about 350 nm, and the undoped polysilicon layer has a thickness in a range between about 650 nm and about 1000 nm is critical and will achieve unexpected results over the range outside of the claimed range. Therefore, it would have been obvious to have wherein the dielectric layer has a thickness in a range between about 40 nm and about 120 nm, the doped polysilicon layer has a thickness in a range between about 250 nm and about 350 nm, and the undoped polysilicon layer has a thickness in a range between about 650 nm and about 1000 nm as claimed in device because having wherein the dielectric layer has a thickness in a range between about 40 nm and about 120 nm, the doped polysilicon layer has a thickness in a range between about 250 nm and about 350 nm, and the undoped polysilicon layer has a thickness in a range between about 650 nm and about 1000 nm can be optimized during routine experimentation depending upon a particular application which is desired.
The applicants have not established the criticality (see next paragraph below) of said first predetermined amount.
The specification contains no disclosure of either the critical nature of the claimed distance or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
7. Claims 6 and 10 are rejected under 35 U.S.C.103 as being unpatentable over Hshieh (US 20080042208 A1; hereinafter Hshieh), in view of Gluschenkov et al. (US 6838334 B1; hereinafter Gluschenkov).
Regarding claim 6, Hshieh teaches all of the features of claim 1.
Hshieh further teaches wherein the first dielectric layer ({1110}; Fig. 17 in view of Fig. 12; see [0024]; oxide) comprises (see below for “a tetraethoxysilane (TEOS)-derived oxide material”). (C3 L26-32; tetraethoxysilane (TEOS) oxide)
As noted above Hshieh does not expressly disclose the first dielectric layer comprises a tetraethoxysilane (TEOS)-derived oxide material”). (C3 L26-32; tetraethoxysilane (TEOS) oxide
However, in the analogous art, Gluschenkov teaches a semiconductor device ([Abstract]), wherein (Fig. 1A+) a third dielectric layer 165 is about 50 to 200 .ANG. of tetraethoxysilane (TEOS) oxide (C3 L26-32; tetraethoxysilane (TEOS) oxide)
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to substitute modified Hshieh’s oxide material with Kashiwagi’s tetraethoxysilane (TEOS) oxide material, because they have equivalent properties, as recognized by Kashiwagi’s tetraethoxysilane (TEOS) oxide material of an insulating layer (C3 L26-32), whereas modified Hshieh teaches an insulating layer comprising of an oxide ([0024]). It has been held that the substitution of one prior teaching by another art supports an obviousness rejection, as in the instant case, the equivalency is being recognized in the prior art, and the substitution is then within the level of ordinary skill in the art. [MPEP 2144.06.II],
and thereby, modified Hshieh’s (by Gluschenkov) device will have wherein the first dielectric layer (Hshieh {1110}; Fig. 17 in view of Fig. 12; see [0024] in view of Gluschenkov C3 L26-32; tetraethoxysilane (TEOS) oxide) comprises a tetraethoxysilane (TEOS)-derived oxide material (in view of Gluschenkov C3 L26-32; tetraethoxysilane (TEOS) oxide).
Regarding claim 10, Hshieh teaches all of the features of claim 8.
Hshieh further teaches wherein the first dielectric layer ({1110}; Fig. 17 in view of Fig. 12; see [0024]; oxide) comprises (see below for “a tetraethoxysilane (TEOS)-derived oxide material”). (C3 L26-32; tetraethoxysilane (TEOS) oxide)
As noted above Hshieh does not expressly disclose the first dielectric layer comprises a tetraethoxysilane (TEOS)-derived oxide material”). (C3 L26-32; tetraethoxysilane (TEOS) oxide
However, in the analogous art, Gluschenkov teaches a semiconductor device ([Abstract]), wherein (Fig. 1A+) a third dielectric layer 165 is about 50 to 200 .ANG. of tetraethoxysilane (TEOS) oxide (C3 L26-32; tetraethoxysilane (TEOS) oxide)
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to substitute modified Hshieh’s oxide material with Kashiwagi’s tetraethoxysilane (TEOS) oxide material, because they have equivalent properties, as recognized by Kashiwagi’s tetraethoxysilane (TEOS) oxide material of an insulating layer (C3 L26-32), whereas modified Hshieh teaches an insulating layer comprising of an oxide ([0024]). It has been held that the substitution of one prior teaching by another art supports an obviousness rejection, as in the instant case, the equivalency is being recognized in the prior art, and the substitution is then within the level of ordinary skill in the art. [MPEP 2144.06.II],
and thereby, modified Hshieh’s (by Gluschenkov) device will have wherein the first dielectric layer (Hshieh {1110}; Fig. 17 in view of Fig. 12; see [0024] in view of Gluschenkov C3 L26-32; tetraethoxysilane (TEOS) oxide) comprises a tetraethoxysilane (TEOS)-derived oxide material (in view of Gluschenkov C3 L26-32; tetraethoxysilane (TEOS) oxide).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Omar Mojaddedi whose telephone number is 313-446-6582. The examiner can normally be reached on Monday – Friday, 8:00 a.m. to 4:00 p.m..
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/OMAR F MOJADDEDI/Examiner, Art Unit 2898
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