DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in Korean Patent Application No. 10-2023-0183087, filed on 12/15/2023.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/6/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The title of the invention has been suggested as, “IMAGE SENSOR WITH A DEEP ISOLATION PATTERN SURROUNDING PIXELS WHEREIN THE DEEP ISOLATION PATTERN COMPRISES AN INTERVENING INSULATING LAYER BETWEEN TWO BURIED LAYERS, A CONDUCTIVE LINER AND AN INSULATING LINER, AND METHOD OF FABRICATING THE SAME”
Drawings
The drawings are objected to because In Figs. 5A and 5B, the label 322 representing the intervening insulating pattern 322 points at a different structure (insulating liner 12). Also, in Fig. 5B, the label 16 representing the buried insulating pattern 16 points at intervening insulating pattern 322.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 16 and 20 are objected, because the following limitations/phrases should be aligned to the prior limitations/phrases to avoid 112 issues due to indefiniteness:
In both claims 16 and 20, there is no antecedent basis for “the interposed insulating pattern” (lines 1-2 of claim 16, and lines 1-2 of claim 20). These occurrences should be due to typo where “the intervening insulating pattern” is misspelled as “the interposed insulating pattern”.
Appropriate corrections are required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kobayashi (US 2020/0321367 A1).
Regarding claim 1, Kobayashi teaches an image sensor (imaging element 12, Figs. 2-3, [0061]: “The imaging element 12 can be a complementary metal oxide semiconductor (CMOS) image sensor.”) comprising:
a substrate (substrate 70, Fig. 3, [0076]) having a first surface (see first surface as labeled in Illustrative Fig. 1, which is an annotated version of Kobayashi’s Fig. 3), the substrate (substrate 70, Illustrative Fig. 1) including a plurality of pixel regions (pixels 50/50a, Illustrative Fig. 1 (see also Fig. 4), [0076]-[0077]);
PNG
media_image1.png
673
880
media_image1.png
Greyscale
a deep isolation pattern (comprising deep trench isolation (DTI) 82 and P-type solid-phase diffused layer 83, Illustrative Fig. 1, [0087]) extending from the first surface (first surface, Illustrative Fig. 1) into the substrate (substrate 70, Illustrative Fig. 1), the deep isolation pattern (comprising deep trench isolation (DTI) 82 and P-type solid-phase diffused layer 83, Illustrative Fig. 1) interposed between the plurality of pixel regions (pixels 50/50a, Illustrative Fig. 1, [0086]: “This DTI 82 is formed between adjacent pixels 50a in a shape which penetrates the Si substrate 70”, see also Fig. 4); and
a shallow device isolation pattern (shallow trench isolation (STI)) 78, Illustrative Fig. 1, [0083]) extending from the first surface (first surface, Illustrative Fig. 1) into the substrate (substrate 70, Illustrative Fig. 1),
wherein the deep isolation pattern (comprising deep trench isolation (DTI) 82 and P-type solid-phase diffused layer 83, Illustrative Fig. 1) and the shallow device isolation (STI 78, Illustrative Fig. 1) pattern are spaced apart from each other (see the gap between the STI 78 and P-type solid-phase diffused layer 83),
wherein a width of the deep isolation pattern (comprising deep trench isolation (DTI) 82 and P-type solid-phase diffused layer 83, Illustrative Fig. 1) is constant (see Illustrative Fig. 1), and
wherein a width of the shallow device isolation pattern (STI 78, Illustrative Fig. 1) decreases as a distance from the first surface (first surface, Illustrative Fig. 1) increases.
Regarding claim 2, Kobayashi teaches the image sensor of claim 1, wherein the shallow device isolation pattern (STI 78, Illustrative Fig. 1) is disposed in a pixel region (pixel 50a, Illustrative Fig. 1) of the plurality of pixel regions (array of pixels 50a, Illustrative Fig. 1 and Fig. 4).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3-4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi (US 2020/0321367 A1) as applied to claims 1-2 above, and further in view of Chen (US 2023/0082312 A1).
Regarding claim 3, while Kobayashi teaches the image sensor of claim 1,
Kobayashi does not teach that the deep isolation pattern includes:
a buried insulating pattern contacting the first surface,
a buried layer on the buried insulation pattern,
a conductive liner on the buried layer, and
an insulating liner on the conductive liner, and
wherein an upper surface of the buried insulating pattern contacts the conductive liner and the buried layer.
Chen, on the other hand, teaches an image sensor (semiconductor device 200, Fig. 14, [0029]; “… semiconductor device 200, which is a back-side illuminated image sensor in an embodiment.” ) comprising a deep isolation structure pattern (deep trench isolation (DTI) 240, Fig. 14, [0028]) between adjacent pixels (pixel regions 1000, Fig. 14, [0026]), wherein the deep isolation pattern (DTI 240, Fig. 14) includes:
a buried insulating pattern (first STI structure 204’ comprising dielectric layer 230 and first STI structure 204, Fig. 14 (see Fig. 10 for the labels of 204 and 230), [0023]: “the first STI structure 204 and the dielectric layer 230 may include silicon oxide.”) contacting the first surface (see first surface and substrate 202 (see substrate 202 in Fig. 9) as labeled in Illustrative Fig. 2, [0034]: substrate 202 in Illustrative Fig. 2 is analogous to the substrate of Kobayashi as the light sensing region is in this region),
PNG
media_image2.png
684
1116
media_image2.png
Greyscale
a buried layer (fill layer 220, Fig. 14, [0021]) on the buried insulation pattern (first STI structure 204’, Fig. 14),
a conductive liner (conductive layer 218, Fig. 14, [0020]) on the buried layer (fill layer 220, Fig. 14), and
an insulating liner (dielectric liner 216, Fig. 14, [0019]) on the conductive liner (conductive layer 218, Fig. 14), and
wherein an upper surface of the buried insulating pattern (first STI structure 204’, Fig. 14) contacts the conductive liner (conductive layer 218, Fig. 14) and the buried layer (fill layer 220, Fig. 14).
Chen further discloses that Chen’s “DTI structure is a hybrid structure extending through a substrate and includes an upper portion and a lower portion, which includes a first layer sandwiched by a second layer. The first layer is spaced apart from the substrate by the second layer. A refractive index of the first layer may be smaller than a refractive index of the second layer such that at least a portion of an incident light may be reflected to the corresponding pixel. The second layer may be a conductive layer such that a bias voltage may be applied to the DTI structure to induce carrier accumulation and thus reduce dark current. In some embodiments, the second layer is spaced apart form the substrate by a dielectric layer. By forming the hybrid DTI structure, neighboring pixels may be electrically and optically isolated, the quantum efficiency may be increased, and optical cross talk may be reduced.” Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to replace the layers of the deep isolation pattern of the image sensor of Kobayashi with the layers of the deep isolation pattern of the image sensor of Chen to obtain an image sensor with increased quantum efficiency and reduced optical cross-talk, where the pixels are more effectively isolated both electrically and optically.
Thus, the combination of Kobayashi and Chen meets all the limitations of claim 3.
Regarding claim 4, Kobayashi in view of Chen teaches the image sensor of claim 3, wherein
the combination of Kobayashi and Chen (deep isolation pattern of Kobayashi replaced by deep isolation pattern of Chen (see claim 3 rejection above)) further teaches that the deep isolation pattern (deep isolation pattern of Chen (see claim 3 rejection above), Illustrative Fig. 2) includes a doped region (doped region 214, Illustrative Fig. 2, [0018]; Examiner notes that there is also a doped region in the deep isolation pattern of Kobayashi, P-type solid-phase diffused layer 83 (Illustrative Fig. 1, [0089])) on the insulating liner (dielectric liner 216, Fig. 14), and
wherein the doped region (doped region 214, Illustrative Fig. 2) includes boron ([0018]: “the doped region 214 is a p-type doped region (doped by boron, for example)”).
Regarding claim 7, Kobayashi in view of Chen teaches the image sensor of claim 3, wherein
the combination of Kobayashi and Chen (deep isolation pattern of Kobayashi replaced by deep isolation pattern of Chen (see claim 3 rejection above)) the buried insulating pattern (Chen’s (first STI structure 204’ comprising dielectric layer 230 and first STI structure 204, Fig. 14) includes oxide (Chen, [0023]: “the first STI structure 204 and the dielectric layer 230 may include silicon oxide.”).
Claim 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi (US 2020/0321367 A1) in view of Chen (US 2023/0082312 A1) as applied to claims 3-4 and 7 above, and further in view of Park (US 2017/0207263 A1).
Regarding claim 5, while Kobayashi in view of Chen teaches the image sensor of claim 3,
neither Kobayashi nor Chen teaches that the deep isolation pattern includes an intervening insulating pattern surrounding the buried insulating pattern, and
wherein the intervening insulating pattern is disposed between the insulating liner and the buried insulating pattern, between the buried layer and the buried insulating pattern, and between the conductive liner and the buried insulating pattern.
Park, on the other hand, teaches a low current image sensor (Figs. 3-4, [0045]) with shallow trench isolation structures (second device isolation layer 105, Fig. 4, [0056]), wherein the shallow trench isolation structure (second device isolation layer 105, Fig. 4) comprises a silicon nitride liner (not shown in figures, see [0056]) and an insulating material ([0056]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to also include a silicon nitride liner in the shallow trench isolation structures (including first STI structure 204 of Chen as part of the buried insulating pattern, Figs. 10 and 14) of Kobayashi in view of Chen, as it is known that a nitride liner in a shallow trench isolation (STI) structure provides several benefits, including improved corner rounding near the STI region corners, reduced stress adjacent the STI region, and reduced leakage, as evidenced by Li (US 2007/0048927 A1, [0008]). Accordingly, the combination of Kobayashi, Chen, and Park leads to an image sensor comprising a silicon nitride liner surrounding the first STI structure 204 of Chen (see Illustrative Fig. 3, which is an annotated version of Chen’s Fig. 14, for the location of silicon nitride liner), which is an intervening layer, and therefore the image sensor includes
PNG
media_image3.png
410
652
media_image3.png
Greyscale
the deep isolation pattern (DTI 240 of Chen replacing the deep isolation pattern of Kobayashi, Illustrative Fig. 3) includes an intervening insulating pattern (silicon nitride liner, Illustrative Fig. 3) surrounding the buried insulating pattern (first STI structure 204’ comprising dielectric layer 230 and first STI structure 204, Illustrative Fig. 3), and
wherein the intervening insulating pattern (silicon nitride liner surrounding the first STI structure 204 of Chen, see Illustrative Fig. 2) is disposed between the insulating liner (dielectric liner 216, Chen’s Fig. 14) and the buried insulating pattern (first STI structure 204’ comprising dielectric layer 230 and first STI structure 204, Illustrative Fig. 3), between the buried layer (fill layer 220, Illustrative Fig. 3) and the buried insulating pattern (first STI structure 204’ comprising dielectric layer 230 and first STI structure 204, Illustrative Fig. 3: silicon nitride liner is between the first STI structure 204 and fill layer 220 in the vertical direction), and between the conductive liner (conductive layer 218, Illustrative Fig. 3) and the buried insulating pattern (first STI structure 204’ comprising dielectric layer 230 and first STI structure 204, Illustrative Fig. 3: silicon nitride liner is between the first STI structure 204 and conductive layer 218 in the vertical direction).
Regarding claim 6, Kobayashi in view of Chen and Park teaches the image sensor of claim 5, wherein
the combination of Kobayashi, Chen, and Park further teaches that the intervening insulating pattern includes nitride (silicon nitride, see claim 5 rejection above).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi (US 2020/0321367 A1) in view of Chen (US 2023/0082312 A1) as applied to claims 3-4 and 7 above, and further in view of Hung (US 2017/0207263 A1).
Regarding claim 8, while Kobayashi in view of Chen teaches the image sensor of claim 3,
neither Kobayashi nor Chen teaches that a distance from the first surface to an upper surface of the buried insulating pattern is 500 to 4000 Å.
Hung, on the other hand, teaches shallow trench isolations (STIs) for CMOS image sensor circuit devices to isolate structures and regions (Fig. 2, [0002] and [0012]). Hung further discloses that STI trenching, used to isolate individual circuit elements, or groups of elements, to prevent interference from adjacent circuit elements, has a standard depth for an STI trench of approximately 2300-2600 angstroms ([0017]).
Considering that a distance from the first surface to an upper surface of the buried insulating pattern in the image sensor of Kobayashi in view of Chen is equivalent to the depth of shallow isolation pattern (Chen, Fig. 9, [0022]: “a depth of the second trench 226 is substantially equal to the depth of the first STI structure 204 to prevent or reduce any current leakage at the front side of the workpiece 200”, and the depth of second STI structures 206 are identical to the depth of the first STI structures (see Chen’s Fig. 2)), for an effective suppression of leakage current between circuit elements and regions, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to set the depth of the STI structures in the image sensor of Kobayashi in view of Chen to a standard depth (2300-2600 angstroms) as disclosed by Chen.
Thus, the combination of Kobayashi, Chen, and Hung meets the limitation that a distance from the first surface to an upper surface of the buried insulating pattern is 500 to 4000 Å.
Claims 9-10 and 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi (US 2020/0321367 A1) in views of Chen (US 2023/0082312 A1) and Li (CN 109638026 A).
Regarding claim 9, Kobayashi teaches an image sensor (imaging element 12, Figs. 2-3, [0061]: “The imaging element 12 can be a complementary metal oxide semiconductor (CMOS) image sensor.”) comprising:
a substrate (substrate 70, Fig. 3, [0076]) having a first surface (see first surface as labeled in Illustrative Fig. 4, which is an annotated version of Kobayashi’s Fig. 3), the substrate (substrate 70, Illustrative Fig. 4) including a plurality of pixel regions (pixels 50/50a, Illustrative Fig. 4 (see also Fig. 4), [0076]-[0077]);
a deep isolation pattern (comprising deep trench isolation (DTI) 82 and P-type solid-phase diffused layer 83, Illustrative Fig. 4, [0087]) extending from the first surface (first surface, Illustrative Fig. 4) into the substrate (substrate 70, Illustrative Fig. 4), the deep isolation pattern (comprising deep trench isolation (DTI) 82 and P-type solid-phase diffused layer 83, Illustrative Fig.) interposed between the plurality of pixel regions (pixels 50/50a, Illustrative Fig. 1, [0086]: “This DTI 82 is formed between adjacent pixels 50a in a shape which penetrates the Si substrate 70”, see also Fig. 4); and
PNG
media_image4.png
794
1061
media_image4.png
Greyscale
a shallow device isolation pattern (shallow trench isolation (STI) 78, Illustrative Fig. 4, [0083]) extending from the first surface (first surface, Illustrative Fig. 4) into the substrate (substrate 70, Illustrative Fig. 4).
Kobayashi, however, does not teach that
the deep isolation pattern includes:
a buried insulating pattern contacting the first surface;
a buried layer on the intervening insulating pattern;
a conductive liner on the buried layer;
an insulating liner on the conductive liner; and
a doped region on the insulating liner, and
wherein the intervening insulating pattern surrounds side and upper surfaces of the buried insulating pattern, and the intervening insulating pattern is interposed between the buried insulating pattern and the buried layer.
Chen, on the other hand, teaches an image sensor (semiconductor device 200, Fig. 14, [0029]; “… semiconductor device 200, which is a back-side illuminated image sensor in an embodiment.” ) comprising a deep isolation structure pattern (deep trench isolation (DTI) 240, Fig. 14, [0028]) between adjacent pixels (pixel regions 1000, Fig. 14, [0026]), wherein the deep isolation pattern (DTI 240, Fig. 14) includes:
a buried insulating pattern (dielectric layer 230, Fig. 14 (see Fig. 10 for the labels of dielectric layer 230), [0023]: “the first STI structure 204 and the dielectric layer 230 may include silicon oxide.”) contacting the first surface (see first surface and substrate 202 (see substrate 202 in Fig. 9) as labeled in Illustrative Fig. 5, which is an annotated version of Chen’s Fig. 14, [0034]: substrate 202 in Illustrative Fig. 5 is analogous to the substrate of Kobayashi as the light sensing region is in this region),
a buried layer (fill layer 220, Illustrative Fig. 5, [0021]) on the buried insulation pattern (dielectric layer 230, Illustrative Fig. 5),
a conductive liner (conductive layer 218, Illustrative Fig. 5, [0020]) on the buried layer (fill layer 220, Illustrative Fig. 5), and
an insulating liner (dielectric liner 216, Illustrative Fig. 5, [0019]) on the conductive liner (conductive layer 218, Illustrative Fig. 5),
a doped region (doped region 214, Illustrative Fig. 5, [0018]) on the insulating liner (dielectric liner 216, Illustrative Fig. 5).
PNG
media_image5.png
761
1180
media_image5.png
Greyscale
Chen further discloses that Chen’s “DTI structure is a hybrid structure extending through a substrate and includes an upper portion and a lower portion, which includes a first layer sandwiched by a second layer. The first layer is spaced apart from the substrate by the second layer. A refractive index of the first layer may be smaller than a refractive index of the second layer such that at least a portion of an incident light may be reflected to the corresponding pixel. The second layer may be a conductive layer such that a bias voltage may be applied to the DTI structure to induce carrier accumulation and thus reduce dark current. In some embodiments, the second layer is spaced apart form the substrate by a dielectric layer. By forming the hybrid DTI structure, neighboring pixels may be electrically and optically isolated, the quantum efficiency may be increased, and optical cross talk may be reduced.” Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to replace the layers of the deep isolation pattern of the image sensor of Kobayashi with the layers of the deep isolation pattern of the image sensor of Chen to obtain an image sensor with increased quantum efficiency and reduced optical cross-talk, where the pixels are more effectively isolated both electrically and optically.
The combination of Kobayashi and Chen, however, does not disclose an intervening insulating pattern, and therefore does not teach
an intervening insulating pattern on the buried insulating pattern;
a buried layer on the intervening insulating pattern; and
that the intervening insulating pattern surrounds side and upper surfaces of the buried insulating pattern, and the intervening insulating pattern is interposed between the buried insulating pattern and the buried layer.
Li, on the other hand, teaches a CMOS image sensor (Fig. 1, [0069]) with a plurality of deep isolation patterns (isolation structures 104, Fig 1, [0070]) comprising a buried insulating pattern (first filling layer 110/310, Figs. 1 and 3F, [0070]: “The first filling layer 110 can be a dielectric layer”) and
an intervening insulating pattern (first dielectric substrate/liner 112/308, Figs. 1 and 3F, [0070]; first dielectric layer 112/310 separated the first filling layer 110/310 from the other layers (second trench isolation structure 108, Fig. 1, [0070]) of the deep isolation pattern) on the buried insulating pattern (first filling layer 110/310, Figs. 1 and 3F),
a buried layer (second filling layer 114, Fig. 1, [0070]) on the intervening insulating pattern (first dielectric substrate 112, Fig. 1); and
wherein the intervening insulating pattern (first dielectric substrate 112, Fig. 1) surrounds side and upper surfaces of the buried insulating pattern (first filling layer 110, Fig. 1), and the intervening insulating pattern (first dielectric substrate 112, Fig. 1) is interposed between the buried insulating pattern (first filling layer 110, Fig. 1) and the buried layer (second filling layer 114, Fig. 1).
Li further discloses that the intervening insulating pattern (first dielectric substrate/liner 112/308, Figs. 1 and 3F) and the buried insulating pattern (first filling layer 110/310, Figs. 1 and 3F) form a muti-layer dielectric structure that can be used to isolate the light exchange between isolating areas ([0076]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to replace the buried insulating pattern of Kobayashi in view of Chen with the buried insulation pattern of Li to include an intervening insulating pattern surrounding the buried insulating pattern, as taught by Li, in the image sensor of Kobayashi in view of Chen to be able to improve the light isolation between pixel regions. Thus, the inclusion of the intervening insulating pattern in the image sensor meets the limitations that the image sensor comprises
an intervening insulating pattern on the buried insulating pattern;
a buried layer on the intervening insulating pattern; and
that the intervening insulating pattern surrounds side and upper surfaces of the buried insulating pattern, and the intervening insulating pattern is interposed between the buried insulating pattern and the buried layer.
Regarding claim 10, Kobayashi in views of Chen and Li teaches the image sensor of claim 9, wherein
Kobayashi further teaches that the deep isolation pattern (comprising deep trench isolation (DTI) 82 and P-type solid-phase diffused layer 83 replaced by the layers of the deep isolation patten of Chen (see claim 9 rejection above), Illustrative Fig. 4) and the shallow device isolation pattern (STI 78, Illustrative Fig. 4) are spaced apart from each other (see Illustrative Fig. 4),
wherein the deep isolation pattern (comprising deep trench isolation (DTI) 82 and P-type solid-phase diffused layer 83 replaced by the layers of the deep isolation patten of Chen (see claim 9 rejection above), Illustrative Fig. 4) is disposed between the plurality of pixel regions (pixels 50/50a, Illustrative Fig. 4, [0086]: “This DTI 82 is formed between adjacent pixels 50a in a shape which penetrates the Si substrate 70”, see also Fig. 4), and
wherein the shallow device isolation pattern (shallow trench isolation (STI) 78, Illustrative Fig. 4) is disposed in a pixel region of the plurality of pixel regions (pixels 50/50a, Illustrative Fig. 4).
Regarding claim 12, Kobayashi in views of Chen and Li teaches the image sensor of claim 9, wherein
the combination of Kobayashi, Chen, and Li (see claim 9 rejection above) teaches that the buried layer (fill layer 220 of Chen, Illustrative Fig. 5) includes polysilicon or SiO2 ([0021]: ”the fill layer 220 includes silicon oxide.”), and
wherein the conductive liner (conductive layer 218 of Chen, Illustrative Fig. 5) includes silicon ([0020]: “the conductive layer 218 may be a p-type doped polycrystalline silicon.”).
The combination of Kobayashi, Chen, and Li, however, does not explicitly disclose that the conductive liner includes
a boron-doped silicon.
The combination of Kobayashi, Chen, and Li, however, teaches a doped region (the doped region 214, see claim 9 rejection above), which is a p-doped region doped by boron (Chen: [0018]). A person of ordinary skill in the art before the effective filing date of the claimed invention would already know that boron is a common p-type dopant in silicon, and therefore would be motivated to use the well-known dopant boron as the p-dopant in the conductive layer in the image sensor of Kobayashi in views of Chen and Li to simplify the manufacturing the device by using only one type of dopant to obtain the predictable result of obtaining a reliable p-type doping (see MPEP 2143 (I) (A)).
Regarding claim 13, Kobayashi in views of Chen and Li teaches the image sensor of claim 9, wherein
Kobayashi further teaches that a width of the deep isolation pattern (comprising deep trench isolation (DTI) 82 and P-type solid-phase diffused layer 83, Illustrative Fig. 4; see claim 9 rejection above: only layers of the deep isolation pattern of Kobayashi is replaced by the layers of the deep isolation pattern of Chen to keep the shape of other structures unchanged) is constant (see Illustrative Fig. 4, and
wherein a width of the shallow device isolation pattern (STI 78, Illustrative Fig. 1) decreases as a distance from the first surface (first surface, Illustrative Fig. 4) increases.
Regarding claim 14, Kobayashi in views of Chen and Li teaches the image sensor of claim 9, wherein
the combination of Kobayashi, Chen and Li further teaches that the intervening insulating pattern (Li’s first dielectric substrate/liner 112/308, Figs. 1 and 3F) includes nitride ([0070]: “first dielectric substrate 112 is, for example, a material such … SiON”).
Regarding claim 15, Kobayashi in views of Chen and Li teaches the image sensor of claim 9, wherein
Kobayashi further teaches that the image sensor comprises a transfer gate (transfer transistor (gate) 80, Illustrative Fig. 4, [0084]) disposed on the first surface (first surface, Illustrative Fig. 4) of the substrate (substrate 70, Illustrative Fig. 4),
wherein the transfer gate (transfer transistor (gate) 80, Illustrative Fig. 4) extends into the substrate (substrate 70, Illustrative Fig. 4).
Regarding claim 16, Kobayashi in views of Chen and Li teaches the image sensor of claim 9, wherein
the combination of Kobayashi, Chen, and Li (see claim 9 rejection above) teaches that an inner wall of the interposed insulating pattern (Li’s first dielectric substrate/liner 112/308, Figs. 1 and 3F covering the surfaces of the dielectric layer 230 of Chen (Fig. 14)) contacts the buried insulating pattern (dielectric layer 230 of Chen, Fig. 14), and
wherein an outer wall of the intervening insulating pattern (Li’s first dielectric substrate/liner 112/308, Figs. 1 and 3F covering the surfaces of the dielectric layer 230 of Chen (Illustrative Fig. 5)) contacts the insulating liner (dielectric liner 216, Illustrative Fig. 5: the inner bottom corner point of the dielectric liner 216 touches the dielectric layer 230).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi (US 2020/0321367 A1) in views of Chen (US 2023/0082312 A1) and Li (CN 109638026 A) as applied to claims 9-10 and 12-16 above, and further in view of another embodiment of Kobayashi (US 2020/0321367 A1, Fig. 26)
Regarding claim 11, Kobayashi in views of Chen and Li teaches the image sensor of claim 9,
Kobayashi, Chen, and Li do not teach that
a first sidewall of the deep isolation pattern contacts the shallow device isolation pattern, and
wherein a second sidewall of the deep isolation pattern is spaced apart from the shallow device isolation pattern.
Another embodiment of Kobayashi (Fig. 26), however, teaches an image sensor (Fig. 26, [0224]) wherein
a first sidewall of the deep isolation pattern (side wall of DTI 82 on the left, Fig. 26) contacts the shallow device isolation pattern (STI 78 in contact with DTI 82 on the left, Fig. 26), and
wherein a second sidewall of the deep isolation pattern (side wall of DTI 82 on the right, Fig. 26) is spaced apart from the shallow device isolation pattern (STI 78 in contact with DTI 82 on the left, Fig. 26).
The other embodiment of Kobayashi further discloses that the embodiment in Fig. 26 includes two transfer gates (transfer transistor gates 80, Fig. 26) of different lengths (Fig. 26) which provides the benefit of optimize each transfer of charges at a shallow portion and a deep portion of the photodiode (PD, Fig. 26,, [0233]), and having the STI region overlapping with the deep isolation pattern on one side provides the benefit of keeping the pixel size small ([0117]) while opening space for the second transfer gate. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention who is aiming to use a second gate in the pixels of the image sensor of Kobayashi in views of Chen and Li would be motivated to overlap one of the shallow device isolation patterns with the deep isolation pattern, as taught by the embodiment of Kobayashi shown in Fig. 26, to open space for the second gate.
This the combination of Kobayashi, Chen, Li, and another embodiment of Kobayashi meet all the limitations of claim 11.
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi (US 2020/0321367 A1) in views of Kim (US 2020/0227449) and Li (CN 109638026 A).
Regarding claim 17, Kobayashi teaches an image sensor (imaging element 12, Figs. 2-3, [0061]: “The imaging element 12 can be a complementary metal oxide semiconductor (CMOS) image sensor.”) comprising:
a substrate (substrate 70, Fig. 3, [0076]) having a first surface (see first surface as labeled in Illustrative Fig. 6, which is an annotated version of Kobayashi’s Fig. 3) and a second surface (second surface, Illustrative Fig. 6), the substrate (substrate 70, Illustrative Fig. 6) including a plurality of pixel regions (pixels 50/50a, Illustrative Fig. 6 (see also Fig. 4), [0076]-[0077]);
PNG
media_image6.png
790
1051
media_image6.png
Greyscale
a plurality of microlenses (on-chip lens (OCL) 76, Illustrative Fig. 6, [0081]; while Kobayashi does not disclose that the lenses are microlenses, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that the lenses have the size of a pixel which is a microscale) on the second surface (second surface, Illustrative Fig. 6) of the substrate (substrate 70, Illustrative Fig. 6);
a transfer gate (transfer gate (TG) 80, Illustrative Fig. 6, [0080]) disposed on the first surface (first surface, Illustrative Fig. 6) of the substrate (substrate 70, Illustrative Fig. 6);
a deep isolation pattern (comprising deep trench isolation (DTI) 82 and P-type solid-phase diffused layer 83, Illustrative Fig. 6, [0087]) extending from the first surface (first surface, Illustrative Fig. 6) into the substrate (substrate 70, Illustrative Fig. 6), the deep isolation pattern (comprising deep trench isolation (DTI) 82 and P-type solid-phase diffused layer 83, Illustrative Fig. 6) interposed between the plurality of pixel regions (pixels 50/50a, Illustrative Fig. 6, [0086]: “This DTI 82 is formed between adjacent pixels 50a in a shape which penetrates the Si substrate 70”, see also Fig. 4);
a shallow device isolation pattern (shallow trench isolation (STI) 78, Illustrative Fig. 6, [0083]) extending from the first surface (first surface, Illustrative Fig. 6) into the substrate (substrate 70, Illustrative Fig. 6),
wherein the shallow device isolation pattern (shallow trench isolation (STI) 78, Illustrative Fig. 6) is spaced apart from the deep isolation pattern (comprising deep trench isolation (DTI) 82 and P-type solid-phase diffused layer 83, Illustrative Fig. 6),
Kobayashi, however, does not teach
an anti-reflective layer on the deep isolation pattern; and
that the deep isolation pattern includes:
a buried insulating pattern contacting the first surface;
an intervening insulating pattern on the buried insulating pattern;
a buried layer on the intervening insulating pattern;
a conductive liner on the buried layer;
an insulating liner on the conductive liner; and
a doped region on the insulating liner, and
wherein the intervening insulating pattern surrounds side and upper surfaces of the buried insulating pattern, and the intervening insulating pattern is interposed between the buried insulating pattern and the buried layer.
Kim, on the other hand, teaches an image sensor (image sensor, Figs. 1-4, [0010]-[0014]) comprising a deep isolation structure pattern (pixel separation structure 150, Figs. 3-4) between adjacent pixels (pixel region PR, Fig. 4), wherein
an anti-reflective layer (anti-reflection layer 132, Fig. 4 [0048]) on the deep isolation pattern (pixel separation structure 150, Fig. 4); and
the deep isolation pattern (comprising pixel separation structure 150 and doped region 105, Figs. 4) includes:
a buried insulating pattern (capping pattern 157, Figs. 4 and 5A, [0056]: “capping pattern 157 may be formed of or include at least one of, for example, silicon oxide, silicon oxynitride, or silicon nitride.”) contacting the first surface (top surface of the photoelectric conversion layer 10 in Figs. 4 and 5A, [0034]: photoelectric conversion layer 10 is analogous to the substrate of Kobayashi as the light sensing region is in the photoelectric conversion layer 10),
a buried layer (gapfill pattern 151, Figs. 4 and 5A, [0054] and [0059]) on the buried insulation pattern (capping pattern 157, Figs. 4 and 5A),
a conductive liner (conductive pattern 153, Fig. 4, [0059]) on the buried layer (gapfill pattern 151, Figs. 4 and 5A), and
an insulating liner (insulating pattern 155, Fig. 4 and 5A, [0056]) on the conductive liner (conductive pattern 153, Figs. 4 and 5A),
a doped region (doped region 105, Fig. 4, [0053]) on the insulating liner (insulating pattern 155, Fig. 4).
Kim also discloses that the anti-reflection layer is configured to prevent light, which is incident into the second surface (lower surface in Fig. 4) of the substrate, from being reflected, and this may allow the incident light to be effectively incident into the photoelectric conversion layer 10 (Fig. 4, [0048]). Kim further discloses that the conductive liner (conductive pattern 153, Fig. 4) in the deep isolation pattern (comprising pixel separation structure 150 and doped region 105, Fig. 4) of Kim can be connected to a negative voltage to provide the benefit of improving a dark current property of the image sensor ([0063]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include an anti-reflective layer on the deep isolation pattern, as taught by Kim, in the image sensor of Kobayashi to improve the light access to the image sensor. Furthermore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be also motivated to replace the layers of the deep isolation pattern of the image sensor of Kobayashi with the layers of the deep isolation pattern of Kim’s image sensor to obtain an image sensor with improved dark current property. Thus, the combination of Kobayashi and Kim meets the limitations that the image sensor comprises
an anti-reflective layer on the deep isolation pattern; and
the deep isolation pattern includes
a buried layer on the intervening insulating pattern;
a conductive liner on the buried layer;
an insulating liner on the conductive liner; and
a doped region on the insulating liner.
The combination of Kobayashi and Kim, however, is silent about an intervening insulating pattern, and therefore, does not teach that
the deep isolation pattern includes:
an intervening insulating pattern on the buried insulating pattern; and
the buried layer on the intervening insulating pattern;
that the intervening insulating pattern surrounds side and upper surfaces of the buried insulating pattern, and the intervening insulating pattern is interposed between the buried insulating pattern and the buried layer.
Li, on the other hand, teaches a CMOS image sensor (Fig. 1, [0069]) with a plurality of deep isolation patterns (isolation structures 104, Fig 1, [0070]) comprising a buried insulating pattern (first filling layer 110/310, Figs. 1 and 3F, [0070]: “The first filling layer 110 can be a dielectric layer”) and
an intervening insulating pattern (first dielectric substrate/liner 112/308, Figs. 1 and 3F, [0070]; first dielectric layer 112/310 separated the first filling layer 110/310 from the other layers (second trench isolation structure 108, Fig. 1, [0070]) of the deep isolation pattern) on the buried insulating pattern (first filling layer 110/310, Figs. 1 and 3F),
a buried layer (second filling layer 114, Fig. 1, [0070]) on the intervening insulating pattern (first dielectric substrate 112, Fig. 1); and
wherein the intervening insulating pattern (first dielectric substrate/liner 112/308, Figs. 1 and 3F) surrounds side and upper surfaces of the buried insulating pattern (first filling layer 110/310, Figs. 1 and 3F), and the intervening insulating pattern (first dielectric substrate/liner 112/308, Fig. 1) is interposed between the buried insulating pattern (first filling layer 110, Fig. 1) and the buried layer (second filling layer 114, Fig. 1).
Li further discloses that the intervening insulating pattern (first dielectric substrate/liner 112/308, Figs. 1 and 3F) and the buried insulating pattern (first filling layer 110/310, Figs. 1 and 3F) form a muti-layer dielectric structure that can be used to isolate the light exchange between isolating areas ([0076]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include an intervening insulating pattern surrounding the buried insulating pattern, as taught by Li, in the image sensor of Kobayashi in view of Kim to be able to improve the light isolation between pixel regions. Thus, the inclusion of the intervening insulating pattern in the image sensor meets the limitations that the image sensor comprises
an intervening insulating pattern on the buried insulating pattern;
a buried layer on the intervening insulating pattern; and
that the intervening insulating pattern surrounds side and upper surfaces of the buried insulating pattern, and the intervening insulating pattern is interposed between the buried insulating pattern and the buried layer.
Regarding claim 18, while Kobayashi in views of Kim and Li teaches the image sensor of claim 17,
Kobayashi and Kim are silent about an intervening insulating pattern, and therefore do not teach that the intervening insulating pattern includes nitride.
Li, on the other hand, teaches that the intervening insulating pattern (first dielectric substrate/liner 112/308, Figs. 1 and 3F) includes nitride ([0070]: “SiON”).
A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that the buried insulating pattern in the image sensor of Kobayashi in view of Kim and Li (buried insulating pattern of Kobayashi replaced by buried insulating pattern (capping pattern 157, Fig. 4) of Kim (see claim 17 rejection above) is silicon oxide or silicon nitride (Kim, [0056]), and therefore an intervening insulating pattern made of SiON (with an index of refraction that can be tuned by adjusting its nitrogen/oxygen composition between the indices of refraction of silicon nitride and silicon oxide) can be used to adjust the combination of indices of refraction of the layers to optimize the light reflection through these layers. Therefore, a person of ordinary skill in the art would be motivated to form the intervening insulating pattern in the image sensor of Kobayashi in view of Kim and Li from SiON as taught by Li.
Regarding claim 19, Kobayashi in views of Kim and Li teaches the image sensor of claim 17, wherein
Kobayashi further teaches that the shallow device isolation pattern (shallow trench isolation (STI) 78, Illustrative Fig. 6) is disposed in a pixel region (pixels 50/50a, Illustrative Fig. 6) of the plurality of pixel regions (pixels 50/50a, Illustrative Fig. 6 and Fig. 4).
PNG
media_image7.png
510
658
media_image7.png
Greyscale
Regarding claim 20, Kobayashi in views of Kim and Li teaches the image sensor of claim 17, wherein
the combination of Kobayashi, Kim, and Li teaches (the image sensor where the layers of the deep isolation pattern of Kobayashi are replaced by the layers of the deep isolation pattern of Kim, and the intervening insulating layer of Li incorporated (see claim 17 rejection above)) an inner wall of the interposed insulating pattern (Li’s first dielectric substrate/liner 112, (Li’s Fig. 1) included surrounding the capping pattern 157 of Chen (Chen’s Fig. 4)) contacts the buried insulating pattern (the capping pattern 157 of Chen, see Illustrative Fig. 7 which is a modified version of Chen’s Fig. 4 incorporating the intervening insulating layer of Li), and
wherein an outer wall of the intervening insulating pattern (intervening insulating pattern, Illustrative Fig. 7) contacts the insulating liner (insulating pattern 155, Illustrative Fig. 7).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park (US 2022/0238571 A1) teaches an image sensor with deep isolation pattern and shallow device isolation pattern, which is relevant to all claims.
Mouli (US 2006/0033132 A1) teaches an image sensor with a shallow device isolation pattern comprising a liner, which is relevant to claims 5-6.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights