Prosecution Insights
Last updated: October 01, 2026
Application No. 18/796,121

MEMORY DEVICE AND OPERATION METHOD THEREOF, AND MEMORY SYSTEM AND STORAGE MEDIUM

Final Rejection §112
Filed
Aug 06, 2024
Priority
Apr 19, 2024 — CN 2024104837822
Examiner
RADKE, JAY W
Art Unit
2137
Tech Center
2100 — Computer Architecture & Software
Assignee
Yangtze Memory Technologies Co., Ltd.
OA Round
2 (Final)
86%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
732 granted / 852 resolved
+30.9% vs TC avg
Moderate +8% lift
Without
With
+8.5%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
15 currently pending
Career history
870
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
41.5%
+1.5% vs TC avg
§102
23.6%
-16.4% vs TC avg
§112
26.0%
-14.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 852 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The disclosure is objected to because of the following informalities: Throughout the specification the term “stages” is used in the context of “stages of read voltages”, which causes much confusion due to indefiniteness as to what is meant by such a word or term or phrase. For example, in the summary portion, perhaps “each page corresponds to a plurality of stages of read voltages” is meant to mean “each page corresponds to a set of read voltages, each needed to be applied at a different time, to read the respective page or bit value of a row of memory cells”. Perhaps, “different pages among the n pages share at least one stage of read voltages” is meant to mean “different pages among the n pages share at least one read voltage”. Perhaps “two stages of read voltages”, “three stages of read voltages”, and “four stages of read voltages” is meant to mean “two read voltages”, “three read voltages”, and “four read voltages”, respectively. Perhaps “different stages of read voltages” is meant to mean “different sets of read votlages”. In other words perhaps Applicant meant “stages” to mean “sets” or “steps of applying read voltages, wherein a different read voltage is applied in each step”. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1: The claim is indefinite since each of the phrase “stages of read voltages” and “different pages among the n pages share at least one stage of read voltages” is not a standard term used in the art, is not defined in the disclosure, and is indefinite in plain English. Various interpretations in plain English may be taken here. One example would be interpreting sharing a stage of read voltages as being an application of a corresponding read voltage value to the pages concurrently (sharing in the context of time). A second example would be interpreting a stage of read voltages as being a step during ramp-up to a final read voltage level., wherein each step is a read voltage value corresponding to a stage and is commonly applied to each page when reading the corresponding page at its respective time (sharing a wave form having a stepped pulse). It is also possible that other interpretations may exist for such an unusual and undefined phrase. It is not known if a single read voltage can have a plurality of stages or does a plurality of stages require a plurality of read voltages. If a single stage corresponds to a single read voltage, then “share at least one stage of read voltages” should be changed to “share at least one read voltage”. If each page is meant to refer to a logical page or bit position within a multibit per cell flash memory then maybe a stage of reading voltages is to refer to a set of read voltages but the claim does not make this definite due to the word “stage”. Claims 2-10 depend on claim 1. Regarding claim 11: The claim is indefinite since each of the phrase “stages of read voltages” and “different pages among the n pages share at least one stage of read voltages” is not a standard term used in the art, is not defined in the disclosure, and is indefinite in plain English. Various interpretations in plain English may be taken here. One example would be interpreting sharing a stage of read voltages as being an application of a corresponding read voltage value to the pages concurrently (sharing in the context of time). A second example would be interpreting a stage of read voltages as being a step during ramp-up to a final read voltage level., wherein each step is a read voltage value corresponding to a stage and is commonly applied to each page when reading the corresponding page at its respective time (sharing a wave form having a stepped pulse). It is also possible that other interpretations may exist for such an unusual and undefined phrase. It is not known if a single read voltage can have a plurality of stages or does a plurality of stages require a plurality of read voltages. If a single stage corresponds to a single read voltage, then “share at least one stage of read voltages” should be changed to “share at least one read voltage”. If each page is meant to refer to a logical page or bit position within a multibit per cell flash memory then maybe a stage of reading voltages is to refer to a set of read voltages but the claim does not make this definite due to the word “stage”. Claims 12 depends on claim 11. Regarding claim 13: The claim is indefinite since each of the phrase “stages of read voltages” and “different pages among the n pages share at least one stage of read voltages” is not a standard term used in the art, is not defined in the disclosure, and is indefinite in plain English. Various interpretations in plain English may be taken here. One example would be interpreting sharing a stage of read voltages as being an application of a corresponding read voltage value to the pages concurrently (sharing in the context of time). A second example would be interpreting a stage of read voltages as being a step during ramp-up to a final read voltage level., wherein each step is a read voltage value corresponding to a stage and is commonly applied to each page when reading the corresponding page at its respective time (sharing a wave form having a stepped pulse). It is also possible that other interpretations may exist for such an unusual and undefined phrase. It is not known if a single read voltage can have a plurality of stages or does a plurality of stages require a plurality of read voltages. If a single stage corresponds to a single read voltage, then “share at least one stage of read voltages” should be changed to “share at least one read voltage”. If each page is meant to refer to a logical page or bit position within a multibit per cell flash memory then maybe a stage of reading voltages is to refer to a set of read voltages but the claim does not make this definite due to the word “stage”. Claims 14-20 depend on claim 13. Response to Arguments Applicant's arguments filed July 7, 2026 have been fully considered but they are not persuasive. Each of claims 1, 11, and 13 uses the phrases “a plurality of stages of read voltages” and “at least one stage of read voltages”. A voltage having a stage or stages is not a standard phrase used in the art of electrical circuits. The meaning of “stage” in plain English is a single phase or step in a process or development OR an element or part of a physical structure such as an amplifier or a rocket. Based on this, one might be able to interpret a single read voltage as being divided into sub-voltages or stages that add up to the single read voltage BUT the plural “read voltages” was used, even causing further confusion. We are left with how to interpret read voltages having a plurality of stages. One would ask does this mean that each of the read voltages has a plurality of sub-voltages (stages) or does the plurality of read voltages as a collective whole have stages? This results in at least two very different interpretations, neither of which Examiner believes is Applicant’s intention. Based on what is known in the art, it may be Applicant’s intention to convey that each page corresponds to a set of read voltages or read voltage levels, wherein reading a respective page is performed in a plurality of stages, wherein each stage of reading applies a corresponding read voltage or read voltage level of the set of read voltages or read voltage levels that correspond to the respective page. Note that in the above paragraph it is the action of reading or applying read voltages that has the steps or phases or stages, and NOT the read voltages themselves. Applicant’s claims are silent on any action using the read voltages that would comprise the stages BUT rather Applicant’s claims clearly state in plain English that the read voltages themselves have a plurality of stages. This is a problem. Applicant’s arguments seem to propose several different ways of interpreting stages of read voltages, which further confirms Examiner’s argument that such a phrase may have multiple interpretations causing indefiniteness (not one is within the scope of the other). One of Applicants interpretation seems to be using stage to mean “level”. It is unheard of in the art to use “voltage stage” to mean “voltage level” and this also would defy the plain English meaning of “stage”. Applicant did not point to a clear definition provided in the original specification that would notify the public that Applicant re-defined the word “stage” to mean “level” as in voltage level. A patent Applicant is strictly expected to clearly redefine any word they intend to use differently from its ordinary and customary meaning. The written description must clearly set forth the custom definition and explicitly express an intent to redefine the term. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. JAY W. RADKE Primary Examiner Art Unit 2827 /JAY W. RADKE/Primary Examiner, Art Unit 2827
Read full office action

Prosecution Timeline

Aug 06, 2024
Application Filed
May 06, 2026
Non-Final Rejection mailed — §112
Jul 07, 2026
Response Filed
Sep 22, 2026
Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12744084
METHOD FOR READING A MULTI-LEVEL NON-VOLATILE MEMORY DEVICE, IN PARTICULAR A PHASE-CHANGE MEMORY DEVICE, AND MULTI-LEVEL NON-VOLATILE MEMORY DEVICE
2y 4m to grant Granted Sep 22, 2026
Patent 12744095
MEMORY DEVICE AND OPERATION METHOD THEREOF
2y 2m to grant Granted Sep 22, 2026
Patent 12738309
ADJUSTING REFRESH RATE DURING SELF-REFRESH STATE
1y 10m to grant Granted Sep 15, 2026
Patent 12725655
REDUNDANCY AND MAJORITY VOTING IN A KEY-VALUE DATA STORAGE SYSTEM USING CONTENT ADDRESSABLE MEMORY
1y 10m to grant Granted Sep 01, 2026
Patent 12718887
OPERATION METHODS OF MEMORY, MEMORY AND MEMORY SYSTEMS
2y 7m to grant Granted Aug 25, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
86%
Grant Probability
94%
With Interview (+8.5%)
2y 0m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 852 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month