DETAILED ACTION
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/6/2024, 3/27/2025, and 09/19/2025 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 10 objected to because of the following informalities:
Claim 10, last line, “that are adjacent” should be “and are adjacent”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 7 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Takeuchi (US 20200161467 A1)
Regarding claim 1, Takeuchi discloses (Fig. 3) A transistor structure, comprising: an epitaxial layer (6); a well region (7), formed on the epitaxial layer; a plurality of gate regions (10), formed in the epitaxial layer (6) and penetrating the well region (7); a plurality of first heavily doped regions (8 n+ on left side of 10), wherein each of the plurality of first heavily doped regions is formed on a first side (left side) of the corresponding gate region, and the plurality of first heavily doped regions are isolated from each other (isolated by 9); and a plurality of second heavily doped regions (8 n+ on right side of 10), wherein each of the plurality of second heavily doped regions is formed on a second side (right side) of the corresponding gate region (10), the plurality of second heavily doped regions are isolated from each other (isolated by 9), and the first side and the second side are different.
Regarding claim 2, Takeuchi discloses the transistor structure according to claim 1. Takeuchi further discloses comprising: a plurality of first semiconductor structures (9), wherein each of the plurality of first semiconductor structures is formed between corresponding two of the plurality of first heavily doped regions (9 between 8 n+ on left side of 10); and plurality of second semiconductor structures, wherein each of the plurality of second semiconductor structures is formed between corresponding two of the plurality of second heavily doped regions (9 between 8 n+ on right side of 10), wherein the plurality of first semiconductor structures, the plurality of second semiconductor structures (same p type 9), and the well region (7) have the same material (SiC, ¶¶ [0048, 0085]).
Regarding claim 3, Takeuchi discloses the transistor structure according to claim 1. Takeuchi further discloses (Fig. 3) comprising: a substrate layer (1), wherein the epitaxial layer (6) is formed on the substrate layer.
Regarding claim 4, Takeuchi discloses the transistor structure according to claim 1. Takeuchi further discloses (Fig. 3) wherein the well region (7) has a first conductive polarity (p-type), each of the plurality of first heavily doped regions (8 n+ on left side of 10) and each of the plurality of second heavily doped regions (8 n+ on right side of 10) have a second conductive polarity (n-type), and the first conductive polarity is opposite to the second conductive polarity.
Regarding claim 5, Takeuchi discloses the transistor structure according to claim 1. Takeuchi further discloses (Fig. 3) wherein each of the plurality of gate regions (10) comprises: a polysilicon structure (12, ¶ [0053]) formed in the epitaxial layer and penetrating the well region, and configured to form a gate structure (10); and an oxide layer (11), formed outside the polysilicon structure and surrounding the polysilicon structure (Fig. 3).
Regarding claim 7, Takeuchi discloses the transistor structure according to claim 1. Takeuchi discloses wherein the plurality of first heavily doped regions and the plurality of second heavily doped regions form a source of the transistor structure ([0048]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable by Takeuchi (US 20200161467 A1) in view of Hu (US 20160336394 A1)
Regarding claim 6, Takeuchi discloses the transistor structure according to claim 5. Takeuchi is silent regarding wherein the polysilicon structure comprises: a first substructure; and a second substructure, wherein the first substructure and the second substructure overlap each other and form a split gate structure.
Hu discloses (Fig. 2, ¶ [0014]) a vertical transistor structure wherein a trench gate is deposited with polysilicon 135-1 and 135-2 portions separating from each other by an insulation layer (138). Artisans in the art would have appreciated splitting the polygate of a vertical transistor can lower gate-drain capacitance and thus improves switching speed. Thus, it would have been obvious to one of ordinary skill in the art before the filing date of the invention to substitute the split polygate of Hu for the polygate region of Takeuchi for a diversity of applications. Doing so would allow for the lower gate-drain capacitance improving switching speed.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable by Takeuchi (US 20200161467 A1) in view of Georgescu (US 20150171174 A1)
Regarding claims 8 and 9, Takeuchi discloses the transistor structure according to claim 1. Takeuchi is silent regarding wherein each of the plurality of gate regions, each of the plurality of first heavily doped regions, and each of the plurality of second heavily doped regions form a ring-shaped structure, wherein a distribution of the plurality of first heavily doped regions and the plurality of second heavily doped regions in a central region has a first density, and a distribution of the plurality of first heavily doped regions and the plurality of second heavily doped regions in a peripheral region has a second density, wherein the first density is greater than or equal to the second density.
Georgescu discloses (Fig. 3A, ¶ [0025]) ring-shaped gate member 340 and source region 320 surrounding the gate, (Fig. 5B, ¶ [0035]) contour lines (gate trenches) are denser in a central region than in a peripheral region.
Artisan in the art would have appreciated a ring-shaped vertical transistor offering better electrostatic control and channel uniformity because the ring geometry helps distribute the electric filed more evenly around the channel. And the density of gate trenches is higher in a center than in a peripheral area because the central region has the shortest gate-to-channel distance and the most direct coupling between gate and channel. Thus, higher trench density ensures stronger electrostatic control over the central channel, reducing leakage current and improving subthreshold swing while peripheral trenches farther from the main channel have weaker coupling, so fewer trenches are needed to maintain performance.
As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate a ring-shaped vertical transistor with denser gate trenches from center out as taught by Georgescu into a vertical transistor of Takeuchi to improve the electrostatic control and channel uniformity. Doing so would reduce the current leakage and improve edge breakdown.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable by Takeuchi (US 20200161467 A1) in view of Quoirin (US 20050127434 A1)
Regarding claim 10, Takeuchi discloses the transistor structure according to claim 1. Takeuchi is silent regarding further comprising: a plurality of third heavily doped regions, wherein each of the plurality of third heavily doped regions is formed between each of the plurality of first heavily doped regions and each of the plurality of second heavily doped regions that are adjacent to each other.
Quoirin discloses a vertical transistor (¶ [0007]) wherein (Fig. 1A, ¶ [0005]) in the P well region 4 formed a heavily-doped N-type ring 5 which is the source regions between gate regions 7 and a more heavily doped region 3 in the central of the P well region 4 between the source regions 5.
Artisans in the art would have appreciated including a heavily doped region in the central of the well of a vertical transistor increase ohmic contact between the source and drain, ensuring efficient current flow through the channel. As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to add a heavily doped region in the center of the well as taught by Quoirin to the well region of the transistor of Takeuchi to enhance current flow through the channel.
Claim(s) 11, 13, 15-17, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable by Takeuchi (US 20200161467 A1) in view of Quoirin (US 20050127434 A1)
Regarding claim 11, Takeuchi discloses (Fig. 3) A transistor structure, comprising: an epitaxial layer (6); a well region (7), formed on the epitaxial layer; a plurality of gate regions (10), formed in the epitaxial layer and penetrating the well region; a plurality of heavily doped regions (8 n+ on left side and right side of 10), wherein two of the plurality of heavily doped regions are respectively formed on both sides of the corresponding gate region;
Takeuchi is silent regarding comprising a plurality of buried heavily doped regions, respectively formed in a plurality of the well regions under a plurality of selected heavily doped regions among the plurality of heavily doped regions.
Quoirin discloses a vertical transistor (¶ [0007]) wherein (Fig. 1A, ¶ [0005]) in the P well region 4 formed a heavily-doped N-type ring 5 which is the source regions between gate regions 7 and a more heavily doped region 3 in the central of the P well region 4 between the source regions 5.
Artisans in the art would have appreciated including a heavily doped region in the central of the well of a vertical transistor increase ohmic contact between the source and drain, ensuring efficient current flow through the channel. As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to add a heavily doped region in the center of the well as taught by Quoirin to the well region of the transistor of Takeuchi to enhance current flow through the channel.
Regarding claim 13, Takeuchi in view of Quoirin discloses the transistor structure according to claim 11. Quoirin further discloses (Fig. 1A) wherein each of the plurality of buried heavily doped regions has a plurality of sub-blocks, and the plurality of sub-blocks do not contact each other (heavily doped portions spaced apart from each other by the trench gate).
Regarding claim 15, Takeuchi in view of Quoirin discloses the transistor structure according to claim 11. Takeuchi further discloses (Fig. 3) comprising: a substrate layer (1), wherein the epitaxial layer (6) is formed on the substrate layer.
Regarding claim 16, Takeuchi in view of Quoirin discloses the transistor structure according to claim 11. Takeuchi further discloses (Fig. 3) wherein the well region has a first conductive polarity (p), each of the plurality of heavily doped regions has a second conductive polarity (n+), and the first conductive polarity is opposite to the second conductive polarity.
Regarding claim 17, Takeuchi in view of Quoirin discloses the transistor structure according to claim 11. Takeuchi further discloses (Fig. 3) wherein each of the plurality of gate regions comprises: a polysilicon structure (12, ¶ [0053]), formed in the epitaxial layer and penetrating the well region, and configured to form a gate structure (10); and an oxide layer (11), formed outside the polysilicon structure and surrounding the polysilicon structure (Fig. 3).
Regarding claim 19, Takeuchi in view of Quoirin discloses the transistor structure according to claim 11. Quoirin further discloses (Fig. 1A) a plurality of third heavily doped regions (3), wherein each of the plurality of third heavily doped regions is formed between adjacent two of the plurality of heavily doped regions (5).
Claim(s) 12, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable by Takeuchi (US 20200161467 A1) in view of Quoirin (US 20050127434 A1) and Georgescu (US 20150171174 A1)
Regarding claim 12 and 14, Takeuchi in view of Quoirin discloses the transistor structure according to claim 11. Takeuchi is silent regarding wherein a distribution of the plurality of buried heavily doped regions in a central region has a first density, and a distribution of the plurality of buried heavily doped regions in a peripheral region has a second density, wherein the first density is greater than or equal to the second density, and wherein each of the plurality of gate regions, each of the plurality of heavily doped regions, and each of the plurality of buried heavily doped regions form a ring-shaped structure.
Georgescu discloses (Fig. 3A, ¶ [0025]) ring-shaped gate member 340 and source region 320 surrounding the gate, (Fig. 5B, ¶ [0035]) contour lines (gate trenches) are denser in a central region than in a peripheral region.
Artisan in the art would have appreciated a ring-shaped vertical transistor offering better electrostatic control and channel uniformity because the ring geometry helps distribute the electric filed more evenly around the channel. And the density of gate trenches is higher in a center than in a peripheral area because the central region has the shortest gate-to-channel distance and the most direct coupling between gate and channel. Thus, higher trench density ensures stronger electrostatic control over the central channel, reducing leakage current and improving subthreshold swing while peripheral trenches farther from the main channel have weaker coupling, so fewer trenches are needed to maintain performance.
As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate a ring-shaped vertical transistor with denser gate trenches from center out as taught by Georgescu into a vertical transistor of Takeuchi to improve the electrostatic control and channel uniformity. Doing so would reduce the current leakage and improve edge breakdown.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable by Takeuchi (US 20200161467 A1) in view of Quoirin (US 20050127434 A1) and Hu (US 20160336394 A1)
Regarding claim 18, Takeuchi in view of Quoirin discloses the transistor structure according to claim 17. Takeuchi is silent regarding wherein the polysilicon structure comprises: a first substructure; and a second substructure, wherein the first substructure and the second substructure overlap each other and form a split gate structure.
Hu discloses (Fig. 2, ¶ [0014]) a vertical transistor structure wherein a trench gate is deposited with polysilicon 135-1 and 135-2 portions separating from each other by an insulation layer (138). Artisans in the art would have appreciated splitting the polygate of a vertical transistor can lower gate-drain capacitance and thus improves switching speed. Thus, it would have been obvious to one of ordinary skill in the art before the filing date of the invention to substitute the split polygate of Hu for the polygate region of Takeuchi for a diversity of applications. Doing so would allow for the lower gate-drain capacitance improving switching speed.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Li (US 20230290815 A1) discloses a vertical trench gate transistor formed on the well.
Conclusion
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/DTH/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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