DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Khaderbad et al. (US 2020/0091011).
Regarding claim 1, Khaderbad teaches (FIG. 17):
A semiconductor structure comprising:
an n transistor (200A) and a p transistor (200B);
a ruthenium silicide (RuSi) layer (670) on the p transistor;
a titanium silicide (TiSi) layer (740/750) on one or more of the n transistor and the p transistor; and
a gap fill material (850/860).
Regarding claim 2, Khaderbad teaches:
The semiconductor structure of claim 1, further comprising a barrier layer (790/800) on one or more of the titanium silicide (TiSi) layer and the ruthenium silicide (RuSi) layer.
Regarding claim 3, Khaderbad teaches:
The semiconductor structure of claim 1, wherein the titanium silicide (TiSi) layer is on both of the n transistor and the p transistor (FIG. 17).
Regarding claim 4, Khaderbad teaches:
The semiconductor structure of claim 2, wherein the barrier layer comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), PVD tungsten (W), PVD molybdenum (Mo), and PVD ruthenium (Ru) ([0067]).
Regarding claim 5, Khaderbad teaches:
The semiconductor structure of claim 1, wherein the gap fill material comprises one or more of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru) ([0070]).
Regarding claim 6, Khaderbad teaches:
The semiconductor structure of claim 1, wherein the n transistor has an n-type source/drain region ([0028]).
Regarding claim 7, Khaderbad teaches:
The semiconductor structure of claim 1, wherein the p transistor has a p-type source/drain region ([0028]).
Regarding claim 8, Khaderbad teaches:
The semiconductor structure of claim 6, wherein the n-type source/drain region comprises silicon (Si) doped with phosphorus ([0028]).
Regarding claim 9, Khaderbad teaches:
The semiconductor structure of claim 7, wherein the p-type source/drain region comprises silicon germanium (SiGe) doped with boron (B) ([0028]).
Regarding claim 10, Khaderbad teaches:
The semiconductor structure of claim 1, wherein the gap fill material is substantially free of voids or seams (FIG. 17).
Regarding claim 11, Khaderbad teaches:
The semiconductor structure of claim 6, wherein the n-type source/drain region has a surface that is substantially free of oxide ([0051]).
Regarding claim 12, Khaderbad teaches:
The semiconductor structure of claim 7, wherein the p-type source/drain region has a surface that is substantially free of oxide ([0045]).
Regarding claim 13, Khaderbad teaches:
The semiconductor structure of claim 6, wherein the n transistor has an n-type source/drain region and the p transistor has a p-type source/drain region, and wherein the ruthenium silicide (RuSi) layer is directly on the p-type source/drain region and not on the n-type source/drain region (FIG. 17).
Regarding claim 14, Khaderbad teaches:
The semiconductor structure of claim 2, wherein the barrier layer is on both of the titanium silicide (TiSi) layer and on the ruthenium silicide (RuSi) layer (FIG. 17).
Regarding claim 15, Khaderbad teaches:
The semiconductor structure of claim 2, wherein the barrier layer is on the titanium silicide (TiSi) layer (FIG. 17).
Regarding claim 16, Khaderbad teaches:
The semiconductor structure of claim 2, wherein the barrier layer is on the ruthenium silicide (RuSi) layer (FIG. 17).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Madonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CORY W ESKRIDGE/Primary Examiner, Art Unit 2898
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