DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form
(http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1, 9 and 17.
b. Pending: 1-19, 21.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9-12, 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoon US Patent 8654587 (hereinafter Yoon), in view of Kanda PG PUB 20070036001 (hereinafter Kanda).
Regarding independent claim 1, Yoon teaches a method of operating a memory device (figure 7), the method comprising:
applying a program inhibition voltage to an unselected bit line in a first program loop of a plurality of program loops (VDD on unsel. BL in figure 7 of Yoon, [82] of Yoon, “…a bit line program inhibit voltage (e.g., a power supply voltage: VDD) may be applied to an unselected bit line BL1…”);
applying a program permission voltage to a selected bit line in the first program loop (GND on Sel. BL in figure 7 of Yoon, [82] of Yoon, “…a bit line program voltage (e.g., a ground voltage: GND) may be applied to a selected bit line BL0…”);
applying a pass voltage to an unselected word line in the first program loop (Vpass on unsel WL in figure 7 of Yoon, [97] of Yoon, “…memory cells may be programmed by applying a pass voltage to unselected word lines and a program voltage to a selected word line…”);
applying a program voltage to a selected word line in the first program loop (Vpgm on sel WL in figure 7 of Yoon, [97] of Yoon, “…memory cells may be programmed by applying a pass voltage to unselected word lines and a program voltage to a selected word line…”); and
applying a verification voltage to the selected word line after applying the pulse voltage to the selected word line, in the first program loop (S250 in figure 11 of Yoon, [98], “…In operation S250, the control logic 150 may perform a verification operation to judge whether a program operation is executed normally…”).
But Yoon does not teach applying a pulse voltage having a polarity opposite to a polarity of the program voltage to the selected word line after applying the program voltage to the selected word line, in the first program loop.
Kanda teaches in [0067] and figure 12 to apply a pulse voltage of opposite polarity after programming to detrap charges (figure 12 of Kanda, [0067] of Kanda, “…in step S3, a PGM detrapping pulse is applied to the memory cell, and the electrons trapped in oxide film OM or near the oxide film interface are forcedly detrapped…”, [0072] of Kanda, “…In the write sequence, as described above, application of the program pulse, application of the PGM detrapping pulse, and the program verification operation are repeated…”). The advantage of doing so is to “provide a nonvolatile semiconductor memory device that has an adequate read margin and is improved in operation reliability” ([0008] of Kanda).
Yoon and Kanda are analogous art because they address the same field of endeavor: memory storage apparatuses control circuit designs and control methods therefor. At the time of the effective filing, it would have been obvious to one of ordinary skill in the art, having the teachings of Yoon and Kanda before him, to apply Kanda’s opposite-polarity detrapping pulse to the selected word line in Yoon’s program loop after application of the program voltage and before verification, in order to stabilize the threshold voltage and improve operation reliability.
Regarding claim 2, the combination of Yoon and Kanda teaches the method of claim 1, wherein a threshold voltage of a selected memory cell connected to the selected word line after applying the program voltage to the selected word line is higher than the threshold voltage of the selected memory cell after applying the pulse voltage to the selected word line ([0063] of Kanda, “…when electrons in oxide film OM are detrapped after completion of the write sequence, the threshold voltage of the memory cell decreases…”)
Regarding claim 3, the combination of Yoon and Kanda teaches the method of claim 1, wherein the applying of the program inhibition voltage to the unselected bit line further comprises applying the program inhibition voltage to the unselected bit line during a first time period and a second time period following the first time period, wherein the applying of the program voltage to the selected word line further comprises applying the program voltage to the selected word line during the first time period, and wherein the applying of the pulse voltage to the selected word line further comprises applying the pulse voltage to the selected word line during the second time period (Yoon teaches applying program inhibit voltages to unselected bit lines during multiple program loops to prevent programming of unselected cells, Kanda teaches multi-period voltage application during program operations, including repeated application across multiple time intervals, this repetition inherently teaches applying the same inhibition during successive time periods).
Regarding claim 4, the combination of Yoon and Kanda teaches the method of claim 3, further comprising initializing voltage levels of the selected bit line, the unselected bit line, the selected word line, and the unselected word line after the second time period in the first program loop (Yoon teaches initializing and resetting voltage levels between program loops, e.g., see figure 7 of Yoon at time 0, Kanda teaches initializing voltages by setting multiple terminals to 0V following pulse operations, 90089] of Kanda, “…gate voltage VG, source voltage VS, drain voltage VD and substrate voltage VWELL all set at 0 V in this way…”, resetting all terminals to defined voltage levels constitutes initializing voltage levels).
Regarding independent claim 9, the combination of Yoon and Kanda teaches a method of operating a memory device, the method comprising:
applying a program inhibition voltage to an unselected bit line in each of a plurality of program loops (VDD on unsel. BL in figure 7 of Yoon, [82] of Yoon, “…a bit line program inhibit voltage (e.g., a power supply voltage: VDD) may be applied to an unselected bit line BL1…”);
applying a program permission voltage to a selected bit line in the first program loop (GND on Sel. BL in figure 7 of Yoon, [82] of Yoon, “…a bit line program voltage (e.g., a ground voltage: GND) may be applied to a selected bit line BL0…”);
applying a pass voltage to an unselected word line in the first program loop (Vpass on unsel WL in figure 7 of Yoon, [97] of Yoon, “…memory cells may be programmed by applying a pass voltage to unselected word lines and a program voltage to a selected word line…”);
applying a program voltage to a selected word line in each of the plurality of program loops (Vpgm on sel WL in figure 7 of Yoon, [97] of Yoon, “…memory cells may be programmed by applying a pass voltage to unselected word lines and a program voltage to a selected word line…”);
and
applying a pulse voltage having a polarity opposite to a polarity of the program voltage to the selected word line after applying the program voltage to the selected word line in a first program loop of the plurality of program loops (figure 12 of Kanda, [0067] of Kanda, “…in step S3, a PGM detrapping pulse is applied to the memory cell, and the electrons trapped in oxide film OM or near the oxide film interface are forcedly detrapped…”, [0072] of Kanda, “…In the write sequence, as described above, application of the program pulse, application of the PGM detrapping pulse, and the program verification operation are repeated…”).
Regarding claim 10, the combination of Yoon and Kanda teaches the method of claim 9, wherein a threshold voltage of a selected memory cell connected to the selected word line after applying the program voltage to the selected word line in the first program loop is higher than the threshold voltage of the selected memory cell after applying the pulse voltage to the selected word line in the first program loop ([0063] of Kanda, “…when electrons in oxide film OM are detrapped after completion of the write sequence, the threshold voltage of the memory cell decreases…”)
Regarding claim 11, the combination of Yoon and Kanda teaches the method of claim 9, wherein the applying of the pass voltage to the unselected word line further comprises applying a pass voltage to the unselected word line in first and second time periods of each of the plurality of program loops, wherein the applying of the program voltage to the selected word line further comprises applying the program voltage to the selected word line during the first time period, and wherein the applying of the pulse voltage to the selected word line further comprises applying the pulse voltage to the selected word line during the second time period (Yoon teaches applying program inhibit voltages to unselected bit lines during multiple program loops to prevent programming of unselected cells, Kanda teaches multi-period voltage application during program operations, including repeated application across multiple time intervals, this repetition inherently teaches applying the same inhibition during successive time periods).
Regarding claim 12, the combination of Yoon and Kanda teaches the method of claim 11, further comprising: initializing voltage levels of the selected bit line, the unselected bit line, the selected word line, and the unselected word line after the second time period; and applying a verification voltage to the selected word line after the initializing of the voltage levels of the selected bit line, the unselected bit line, the selected word line, and the unselected word line (Yoon teaches initializing and resetting voltage levels between program loops, e.g., see figure 7 of Yoon at time 0, Kanda teaches initializing voltages by setting multiple terminals to 0V following pulse operations, 90089] of Kanda, “…gate voltage VG, source voltage VS, drain voltage VD and substrate voltage VWELL all set at 0 V in this way…”, resetting all terminals to defined voltage levels constitutes initializing voltage levels).
Regarding independent claim 17, the combination of Yoon and Kanda teaches a memory device comprising:
a memory cell array connected to a plurality of word lines and a plurality of bit lines (figure 1 of Yoon);
a voltage generator (circuit responsible for generating voltages applied to WL in figure 1 of Yoon, 3 in figure 1 of Kanda) configured to generate voltages to be applied to the plurality of word lines; and
a control circuit (150 in figure 1 of Yoon) configured to control a program operation for a plurality of memory cells of the memory cell array, wherein, during the program operation, the control circuit controls the voltage generator to generate a pass voltage to be applied to an unselected word line (Vpass on unsel WL in figure 7 of Yoon, [97] of Yoon, “…memory cells may be programmed by applying a pass voltage to unselected word lines and a program voltage to a selected word line…”), and a program voltage (Vpgm on sel WL in figure 7 of Yoon, [97] of Yoon, “…memory cells may be programmed by applying a pass voltage to unselected word lines and a program voltage to a selected word line…”) and a pulse voltage having a polarity opposite to a polarity of the program voltage to be sequentially applied to a selected word line (figure 12 of Kanda, [0067] of Kanda, “…in step S3, a PGM detrapping pulse is applied to the memory cell, and the electrons trapped in oxide film OM or near the oxide film interface are forcedly detrapped…”, [0072] of Kanda, “…In the write sequence, as described above, application of the program pulse, application of the PGM detrapping pulse, and the program verification operation are repeated…”).
Regarding claim 18, the combination of Yoon and Kanda teaches the memory device of claim 17, further comprising a page buffer circuit (circuit responsible for applying various voltages on bitlines in figure 1 of Yoon, [82] of Yoon, “…a bit line program voltage (e.g., a ground voltage: GND) may be applied to a selected bit line BL0, and a bit line program inhibit voltage (e.g., a power supply voltage: VDD) may be applied to an unselected bit line BL1 …”) configured to apply voltages to the bit lines, wherein, during the program operation, the control circuit controls the page buffer circuit to apply a program inhibition voltage to an unselected bit line and a program permission voltage to a selected bit line.
Allowable Subject Matter
Claims 5-8, 13-16, 19, 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The closest prior art to the present invention is Kanda (US 20070036001 Al).
Kanda discloses after data writing is performed by injecting electrons into a floating gate from a semiconductor substrate of a memory cell, the gate voltage is set at -3 V, and the source voltage, the drain voltage and the substrate voltage are set at 0 V, thereby detrapping the electrons trapped in an oxide film during data writing. The gate voltage (-3 V) is set at a negative voltage value that is smaller in absolute value than the gate voltage (-10.5 V) applied during data erasing.
Regarding claim 5, the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: wherein the applying of the pulse voltage to the selected word line further comprises applying the pulse voltage to the selected word line in the plurality of program loops, and wherein a level of the pulse voltage increases in the plurality of program loops.
Regarding claim 6, the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: the applying of the pulse voltage to the selected word line further comprises: applying the pulse voltage to the selected word line in first to k-1th (k is a natural number greater than or equal to 2) program loops among the plurality of program loops, a level of the pulse voltage increasing in the first to k-1th program loops.
Regarding claim 7, the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: the applying of the pulse voltage to the selected word line further comprises applying the pulse voltage to the selected word line in the plurality of program loops, a pulse width of the pulse voltage increasing in the plurality of program loops.
Regarding claim 8, the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: the applying of the pulse voltage to the selected word line further comprises: applying the pulse voltage to the selected word line in first to k-1th (k is a natural number greater than or equal to 2) program loops among the plurality of program loops, a pulse width of the pulse voltage increasing in the first to k-1th program loops.
Regarding claim 13 (and the respective dependent claims), the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: applying a second pulse voltage to the selected word line in a second program loop among the plurality of program loops, and wherein a voltage level of the first pulse voltage is lower than a voltage level of the second pulse voltage.
Regarding claim 15 (and the respective dependent claims), the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: applying a second pulse voltage having a second pulse width to the selected word line in a second program loop among the plurality of program loops, and wherein the first pulse width is less than the second pulse width.
Regarding claim 19, the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: the control circuit controls the voltage generator to generate the pulse voltage having an increasing voltage level in two or more of a plurality of program loops.
Regarding claim 21, the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: the control circuit controls the voltage generator to generate the pulse voltage having an increasing pulse width in two or more of the plurality of program loops.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance”.
Conclusion
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824