Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment of Amendment
Acknowledgment is made of applicant's amendment, filed on 5/22/2026. The changes and remarks disclosed therein have been considered. Claims 11, 18 have been amended. Therefore, claims 1-20 remain pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maekawa US Patent 10446211 (hereinafter Maekawa), supported by CHEON PG PUB 20120246392, and Langlois PG PUB 20100037001.
Regarding independent claim 1, Maekawa teaches a storage device (title) comprising:
a first buffer memory (11a(11) in figure 9, Maekawa teaches in (133)-(139) that 11a can serve as part of data buffer 22 in figure 1, “…As Specific Example 1, the first region 11a is a L1 cache (which is also referred to as a primary cache and functions as a part of the data buffer 22) and the second region 11b is an L2 cache (which is also referred to as a secondary cache and functions as a part of the data buffer 22)…”, [33], “…data buffer 22 receives data transmitted to the memory system 4 from the host 3 through the host interface 21, and temporarily stores the data. In addition, the data buffer 22 temporarily stores the data to be transmitted to the host 3 from the memory system 4 through the host interface 21…”, figure 20 shows data buffer 22 including L1 cache 22a, and L2 cache 22b, applicant argues that regions 11a/11b are memory storage regions and not buffer memories. However, Maekawa teaches embodiments in which cache memories form portion of data buffer 22, including L1 cache 22a, and L2 cache 22b. Accordingly, Maekawa demonstrates the use of multiple cache/buffer regions having different performance characteristics and therefore teaches or at least suggest first and second buffer memories corresponding to claimed first and second buffer memories) and a second buffer memory (11b(11) in figure 9, Maekawa teaches in (133)-(139) that 11b can serve as part of data buffer 22 in figure 1, figure 20 shows region 11a=L1 Cache 22a, region 11b=L2 cache 22b, both 22a/22b are part of data buffer 22) that are different from each other in at least one operation parameter ([149], “…the memory region 11 is divided into a first region 11a, a second region 11b, and a third region 11c…” [151], “…bank BK2 is a bank having a higher write speed than that of the bank BK3. The bank BK1 is a bank having a higher write speed than that of the bank BK2…” [141], “…the volume of the MTJ element varies in accordance with storage region…”, the first region and second region have different operation parameters (write speed, retention, MTJ volume));
a non-volatile memory (1 in figure 1 and 1 in figure 18, regions 11a/11b are used as temporary cache/buffer storage, while semiconductor storage device 1 provides longer-term storage of data migrated from the cache regions, see para(133)-para(139), figure 20); and
a storage controller (24/26/23/25/21 in figure 1 of Maekawa) connected to the first buffer memory (11a(11) in figure 9 that serves as part of data buffer 22 in figure 1 of Maekawa, L1 Cache in figure 20), the second buffer memory (11b(11) in figure 9 that functions as part of data buffer 22 in figure 1 of Maekawa, L2 cache in figure 20), and the non-volatile memory (1 in figure 1) and configured to perform communication with the first buffer memory, the second buffer memory and the non-volatile memory, wherein each of the first buffer memory and the second buffer memory includes Magnetic Random Access Memory (MRAM) cells (figure 3) and a peripheral circuit (20b/20c in figure 3) configured to operate the MRAM cells according to the at least one operation parameter.
Maekawa teaches the first and second regions 11a, 11b function as a data buffer (buffer 22, [133]-[139]. Accordingly, the semiconductor storage device 1 shown in figure 1, provides longer-term relative to cache regions 11a, 11b, which function as temporary storage region, and therefore reasonably corresponds to claimed non-volatile memory under BRI.
For argument sake, let us assume Maekawa does not explicitly teach 1 in figure 1 is a non-volatile memory, however, the use of buffer memory in front of non-volatile memory is well known in the art, as evidenced by CHEON PG PUB 20120246392, and Langlois PG PUB 20100037001, both of which disclose controller managed buffer memories configured to temporarily store data prior to writing to non-volatile memory. One of ordinary skill in the art would therefore have found it obvious to employ such buffer-based architecture in Maekawa’s storage system.
Regarding claim 2, the combination of Maekawa, CHEON and Langlois teaches the storage device of claim 1, wherein the first buffer memory and the second buffer memory are separate semiconductor chips that are disposed outside a first semiconductor chip (2 in figure 1 of Maekawa) in which the storage controller is disposed and a second semiconductor chip (1 in figure 1 of Maekawa) in which the non-volatile memory is disposed (Maekawa teaches that a semiconductor storage device in which memory regions and controller may be implemented on different chips or stacked chips, [238] of Maekawa, “…the first layer LY1 is a memory controller 2… the second layer LY2 is a semiconductor storage device 1. Further, the first layer LY1 and the second layer LY2 are stacked in the D3 direction and electrically connected using a TSV or the like…”, Cheon teaches that buffer memory maybe implemented separately from both the controller and flash memory, [0006] of Cheon, “…a storage device includes a flash memory, a buffer memory and a memory controller…”, [0004] of Langlois, “…MRAM buffer receives data via the host interface and stores the data until the data is written to the flash memory under control of the flash memory controller…”)
Regarding claim 3, the combination of Maekawa, CHEON and Langlois teaches the storage device of claim 1, wherein the first buffer memory is integrated into a first semiconductor chip in which the storage controller is disposed, and wherein the second buffer memory is disposed in a semiconductor chip separated from the first semiconductor chip in which the storage controller is disposed and a second semiconductor chip in which the non-volatile memory is disposed (Maekawa teaches first and second buffer that function as data buffers, Maekawa further teaches that storage system may be implemented using multiple semiconductor chips or layers having different functions, [238], “…a first layer LY1 and a second layer LY2 the functions and characteristics of which are different from each other…”, Maekawa explicitly teaches that functional blocks may be disposed on different chips or layers and are not limited to a single integration configuration, [139], “…disclosure is not limited to the specific examples…”, It would have been obvious to one of ordinary skill in the art to dispose one of the buffer regions (e.g., region 11a) on a semiconductor chip together with controller, while disposing another buffer region (e.g., region 11b) on a separate chip, in order to balance latency, bandwidth, and packaging constraints, especially in view of Maekawa’s explicit teaching of flexible multi-layer and multi-chip implementation).
Regarding claim 4, the combination of Maekawa, CHEON and Langlois teaches the storage device of claim 1, wherein the first buffer memory and the second buffer memory are integrated into a first semiconductor chip (2 in figures 19, 20 of Maekawa) in which the storage controller is disposed (figure 20 of Maekawa).
Regarding claim 5, the combination of Maekawa, CHEON and Langlois teaches the storage device of claim 1, wherein the first buffer memory and the second buffer memory are integrated into a second semiconductor chip in which the non-volatile memory is disposed ([252] of Maekawa, “…the memory system or the semiconductor storage device may be packaged as single components…”)
Regarding claim 6, the combination of Maekawa, CHEON and Langlois teaches the storage device of claim 1, wherein the first buffer memory is integrated into a first semiconductor chip in which the storage controller is disposed, and the second buffer memory is integrated into a second semiconductor chip in which the non-volatile memory is disposed (Maekawa teaches first and second buffer that function as data buffers, Maekawa further teaches that storage system may be implemented using multiple semiconductor chips or layers having different functions, [238], “…a first layer LY1 and a second layer LY2 the functions and characteristics of which are different from each other…”, Maekawa explicitly teaches that functional blocks may be disposed on different chips or layers and are not limited to a single integration configuration, [139], “…disclosure is not limited to the specific examples…”, It would have been obvious to one of ordinary skill in the art to dispose one of the buffer regions (e.g., region 11a) on a semiconductor chip together with controller, while disposing another buffer region (e.g., region 11b) on a separate chip, in order to balance latency, bandwidth, and packaging constraints, especially in view of Maekawa’s explicit teaching of flexible multi-layer and multi-chip implementation).
Regarding claim 7, the combination of Maekawa, CHEON and Langlois teaches the storage device of claim 1, wherein the at least one operation parameter includes a first retention period of the first buffer memory and a second retention period of the second buffer memory, and wherein the first retention period is different from the second retention period ([149]-[152] of Maekawa, “…the first region 11a includes multiple banks BK1… the second region 11b includes multiple banks BK2… the bank BK2 is a bank having a higher data retention property than that of the bank BK1…”)
Regarding claim 8, the combination of Maekawa, CHEON and Langlois teaches the storage device of claim 1, wherein the first buffer memory and the second buffer memory are disposed in separate semiconductor chips, respectively (Maekawa teaches first and second buffer that function as data buffers, Maekawa further teaches that storage system may be implemented using multiple semiconductor chips or layers having different functions, [238], “…a first layer LY1 and a second layer LY2 the functions and characteristics of which are different from each other…”, Maekawa explicitly teaches that functional blocks may be disposed on different chips or layers and are not limited to a single integration configuration, [139], “…disclosure is not limited to the specific examples…”, It would have been obvious to one of ordinary skill in the art to dispose one of the buffer regions (e.g., region 11a) on a semiconductor chip together with controller, while disposing another buffer region (e.g., region 11b) on a separate chip, in order to balance latency, bandwidth, and packaging constraints, especially in view of Maekawa’s explicit teaching of flexible multi-layer and multi-chip implementation).
Regarding claim 9, the combination of Maekawa, CHEON and Langlois teaches the storage device of claim 1, wherein the storage controller is configured to store data provided from a host into the non-volatile memory via one of the first buffer memory and the second buffer memory (Maekawa teaches in (133)-(139) that 11a, 11b can function as part of data buffer 22 in figure 1, [33] of Maekawa, data buffer 22 receives data transmitted to the memory system 4 from the host 3 through the host interface 21, and temporarily stores the data. In addition, the data buffer 22 temporarily stores the data to be transmitted to the host 3 from the memory system 4 through the host interface 21…”)
Regarding independent claim 10, the combination of Maekawa, CHEON and Langlois teaches a storage device (title of Maekawa) comprising:
a first buffer memory including first MRAM memory cells operating at a first operation parameter (11a(11) in figure 9 of Maekawa, Maekawa teaches in (133)-(139) that 11a can function as part of data buffer 22 in figure 1, [149]-[152] of Maekawa, “…the first region 11a includes multiple banks BK1… the second region 11b includes multiple banks BK2… the bank BK2 is a bank having a higher data retention property than that of the bank BK1…”, “…As Specific Example 1, the first region 11a is a L1 cache (which is also referred to as a primary cache and functions as a part of the data buffer 22) and the second region 11b is an L2 cache (which is also referred to as a secondary cache and functions as a part of the data buffer 22)…”, [33], “…data buffer 22 receives data transmitted to the memory system 4 from the host 3 through the host interface 21, and temporarily stores the data. In addition, the data buffer 22 temporarily stores the data to be transmitted to the host 3 from the memory system 4 through the host interface 21…”, figure 20 shows data buffer 22 including L1 cache 22a, and L2 cache 22b, applicant argues that regions 11a/11b are memory storage regions and not buffer memories. However, Maekawa teaches embodiments in which cache memories form portion of data buffer 22, including L1 cache 22a, and L2 cache 22b. Accordingly, Maekawa demonstrates the use of multiple cache/buffer regions having different performance characteristics and therefore teaches or at least suggest first and second buffer memories corresponding to claimed first and second buffer memories);
a second buffer memory including second MRAM memory cells operating at a second operation parameter (11b(11) in figure 9 of Maekawa, Maekawa teaches in (133)-(139) that 11a can function as part of data buffer 22 in figure 1, [149]-[152] of Maekawa, “…the first region 11a includes multiple banks BK1… the second region 11b includes multiple banks BK2… the bank BK2 is a bank having a higher data retention property than that of the bank BK1…”);
a non-volatile memory (1 in figure 1 and 1 in figure 18 of Maekawa, regions 11a/11b are used as temporary cache/buffer storage, while semiconductor storage device 1 provides longer-term storage of data migrated from the cache regions, see para(133)-para(139) of Maekawa, figure 20 of Maekawa); and
a storage controller (24/26/23/25/21 in figure 1 of Maekawa) configured to store data, which is provided from a host, in one of the first buffer memory and the second buffer memory in accordance with an amount of the data provided from the host (Maekawa teaches a storage controller configured to selectively store data in different MRAM regions having different write speeds and retention properties based on workload characteristics such as elapsed time and access frequency. The claimed selection of a buffer memory based on an amount of data represents an obvious variation, because the amount of data is well known indicator of write burden and retention demand. One of ordinary skill in the art would have found it obvious to use the amount of data as selection criterion when choosing between buffer memories having different write speeds, as a predictable substitution for the access-based criteria taught by Maekawa, as Cheon clearly teaches in figure 6 a size threshold comparison with threshold and decide whether data is stored in NV-RAM or DRAM. Applicant argues that Maekawa does not teach selecting between first and second buffer based on data characteristics. However, Maekawa teaches controller directed placement of data among regions having different write speeds and retention characteristics. Such placement constitutes selection between first and second buffer memories having different operating parameters).
Regarding claim 11, the combination of Maekawa, CHEON and Langlois teaches the storage device of claim 10, wherein the storage controller is configured to:
determine whether an amount of the data exceeds a set value (Maekawa teaches controller comparison against threshold values to control data placement, Cheon in figure 6);
store, in response to determining that the amount of the data does not exceed the set value, in the first buffer memory (Maekawa teaches selective storage into different regions under controller control, [165] of Maekawa, “…the memory controller 2 writes the data, … in the bank BK2 … in the bank BK3 of the…”); and
store, in response to determining of the amount of the data exceeding the set value, the data in the second buffer memory (Maekawa teaches selective storage into different regions under controller control, [165] of Maekawa, “…the memory controller 2 writes the data, … in the bank BK2 … in the bank BK3 of the…”), wherein the first operation parameter includes a first write speed of the first buffer memory ([151] of Maekawa, “…bank BK1 is a bank having a higher write speed than that of the bank BK2…”), wherein the second operation parameter includes a second write speed of the second buffer memory, and wherein the first write speed is faster than the second write speed ([153] of Maekawa, “…the first region 11a including the bank BK1 having the higher write speed … second region 11b including the bank BK2 having an intermediate write speed...”)
Regarding claim 12, the combination of Maekawa, CHEON and Langlois teaches the storage device of claim 11, wherein the first buffer memory is integrated into a first semiconductor chip of the storage controller (figure 20 of Maekawa).
Regarding claim 13, the combination of Maekawa, CHEON and Langlois teaches the storage device of claim 10, wherein the storage controller is configured to: determine whether the non-volatile memory is in an idle state, and store, in response to determining of the non-volatile memory being in the idle state, the data stored in one of the first buffer memory and the second buffer memory in the non-volatile memory (Maekawa teaches migration from buffer like regions to long-term storage, performing such migration during idle periods is a routine buffer-management optimization, obvious once buffered staging is taught).
Regarding claim 14, the combination of Maekawa, CHEON and Langlois teaches the storage device of claim 10, wherein the first buffer memory and the second buffer memory are disposed in separate chips (Maekawa teaches first and second buffer that function as data buffers, Maekawa further teaches that storage system may be implemented using multiple semiconductor chips or layers having different functions, [238], “…a first layer LY1 and a second layer LY2 the functions and characteristics of which are different from each other…”, Maekawa explicitly teaches that functional blocks may be disposed on different chips or layers and are not limited to a single integration configuration, [139], “…disclosure is not limited to the specific examples…”, It would have been obvious to one of ordinary skill in the art to dispose one of the buffer regions (e.g., region 11a) on a semiconductor chip together with controller, while disposing another buffer region (e.g., region 11b) on a separate chip), respectively, wherein the first operation parameter includes a first writing speed and a first retention period ([151]-[151] of Maekawa, “…bank BK1 is a bank having a higher write speed than that of the bank BK2… the bank BK2 is a bank having a higher data retention property than that of the bank BK1…”), wherein the second operation parameter include a second writing speed and a second retention period, wherein the first writing speed is faster than the second writing speed, and wherein the first retention period is shorter than the second retention period.
Regarding claim 15, the combination of Maekawa, CHEON and Langlois teaches the storage device of claim 10, wherein the first buffer memory and the second buffer memory are disposed in separate semiconductor chips, respectively, which are disposed outside a first semiconductor chip of the storage controller and a second semiconductor chip of the non-volatile memory (Maekawa teaches embodiments are not limited to specific arrangement, given Maekawa’s teaching of multi-layer and multi-chip structure, placing buffers on separate chips outside controller and NVM chips is an obvious layout variation).
Regarding claim 16, the combination of Maekawa, CHEON and Langlois teaches the storage device of claim 10, wherein at least one of the first buffer memory and the second buffer memory is integrated into a first semiconductor chip of the storage controller (figure 20 of Maekawa, Maekawa expressly teaches that multi-layer/multi-chip implementations with varying functional allocations (para(139), (238), (252), placement of cache/buffer regions on the controller die would have been an obvious design alternative).
Regarding claim 17, the combination of Maekawa, CHEON and Langlois teaches the storage device of claim 10, wherein at least one of the first buffer memory and the second buffer memory is integrated into a second semiconductor chip of the non-volatile memory ([252] of Maekawa, “…the memory system or the semiconductor storage device may be packaged as single components…”)
Regarding independent claim 18, the combination of Maekawa, CHEON and Langlois teaches a storage device (title of Maekawa) comprising:
a first buffer memory including first MRAM memory cells operating at a first writing speed (11a(11) in figure 9 of Maekawa, Maekawa teaches in (133)-(139) that 11a can function as part of data buffer 22 in figure 1, [149]-[152] of Maekawa, “…the first region 11a includes multiple banks BK1… the second region 11b includes multiple banks BK2… bank BK1 is a bank having a higher write speed than that of the bank BK2…the bank BK2 is a bank having a higher data retention property than that of the bank BK1…”, figure 20 shows data buffer 22 including L1 cache 22a, and L2 cache 22b, applicant argues that regions 11a/11b are memory storage regions and not buffer memories. However, Maekawa teaches embodiments in which cache memories form portion of data buffer 22, including L1 cache 22a, and L2 cache 22b. Accordingly, Maekawa demonstrates the use of multiple cache/buffer regions having different performance characteristics and therefore teaches or at least suggest first and second buffer memories corresponding to claimed first and second buffer memories);
a second buffer memory including second MRAM memory cells operating at a second writing speed (11b(11) in figure 9 of Maekawa, Maekawa teaches in (133)-(139) that 11a can function as part of data buffer 22 in figure 1, “…As Specific Example 1, the first region 11a is a L1 cache (which is also referred to as a primary cache and functions as a part of the data buffer 22) and the second region 11b is an L2 cache (which is also referred to as a secondary cache and functions as a part of the data buffer 22)…”, [149]-[152] of Maekawa, “…the first region 11a includes multiple banks BK1… the second region 11b includes multiple banks BK2 …bank BK1 is a bank having a higher write speed than that of the bank BK2…the bank BK2 is a bank having a higher data retention property than that of the bank BK1…”, figure 20 shows data buffer 22 including L1 cache 22a, and L2 cache 22b, applicant argues that regions 11a/11b are memory storage regions and not buffer memories. However, Maekawa teaches embodiments in which cache memories form portion of data buffer 22, including L1 cache 22a, and L2 cache 22b. Accordingly, Maekawa demonstrates the use of multiple cache/buffer regions having different performance characteristics and therefore teaches or at least suggest first and second buffer memories corresponding to claimed first and second buffer memories);
a non-volatile memory (1 in figure 1 and 1 in figure 18 of Maekawa, regions 11a/11b are used as temporary cache/buffer storage, while other memory elements of semiconductor storage device 1 provides storage of data having greater retention characteristics, see para(133)-para(139) of Maekawa, figure 20 of Maekawa); and
a storage controller (24/26/23/25/21 in figure 1 of Maekawa) storage controller configured to store data, which is provided from a host, in one of the first buffer memory and the second buffer memory in accordance with an amount of the data provided from the host (Cheon teaches in figure 6 determining whether request size is smaller or larger than a threshold (S611), if request size is less than threshold, stored data in NV-RAM, if request size is larger than threshold, store in DRAM (S612), therefore, Cheon teaches to select between different buffer memories according to the amount/size of host data).
Maekawa teaches first and second MRAM buffer memories having different write speeds and retention characteristics Maekawa, however, does not explicitly teaches selecting between the first and second buffer memories according to an amount of data receiving from host.
Cheon teaches determining a size of host write data and selectively storing the data in one of two different buffer memories based on the amount of the received host data (figure 6, S611-S622).
It would have been obvious to modify Maekawa’s controller to select between first region 11a and second region 11b based on amount of host data, as taught by Cheon, in order to allocate data to a memory region having characteristics appropriate for the size of the incoming write request and thereby improve storage efficiency and performance.
Regarding claim 19, the combination of Maekawa, CHEON and Langlois teaches the storage device of claim 18, wherein each of first buffer memory and the second buffer memory includes a peripheral circuit (20b/20c in figure 3 of Maekawa, figure 9 and para(133)-(139) explain regions are part of memories region sharing peripheral circuit, under BRI, a memory region that is operated through an associated peripheral circuit may be considered to include that peripheral circuit as part of the corresponding memory structure).
Regarding claim 20, the combination of Maekawa, CHEON and Langlois teaches the storage device of claim 18, wherein at least one of the first buffer memory and the second buffer memory is incorporated into a first semiconductor chip of the storage controller (figure 20 of Maekawa) or a second semiconductor chip of the non-volatile memory.
Response To Arguments
Applicant's arguments filed on 5/22/2026 have been fully considered but they are not persuasive.
Applicant argues that Maekawa does not disclose at least one of "a first buffer memory and a
second buffer memory that are different from each other in at least one
operation parameter," and "a non-volatile memory," as recited in claim 1.
Examiner respectfully disagrees.
Maekawa teaches in (133)-(139) that 11a can function as part of data buffer 22 in figure 1, “…As Specific Example 1, the first region 11a is a L1 cache (which is also referred to as a primary cache and functions as a part of the data buffer 22) and the second region 11b is an L2 cache (which is also referred to as a secondary cache and functions as a part of the data buffer 22)…”, [33] of Maekawa, “…data buffer 22 receives data transmitted to the memory system 4 from the host 3 through the host interface 21, and temporarily stores the data. In addition, the data buffer 22 temporarily stores the data to be transmitted to the host 3 from the memory system 4 through the host interface 21…”, figure 20 of Maekawa shows data buffer 22 including L1 cache 22a, and L2 cache 22b. Accordingly, Maekawa demonstrates the use of multiple cache/buffer regions having different performance characteristics and therefore teaches or at least suggest first and second buffer memories corresponding to claimed first and second buffer memories. Maekawa also teaches in figure 1 or 18 that regions 11a/11b are used as temporary cache/buffer storage, while semiconductor storage device 1 provides longer-term storage of data migrated from the cache regions, see para(133)-para(139) of Maekawa, figure 20 of Maekawa.
Regarding claim 10, applicant argues that Maekawa does not disclose selecting between first and second buffer memories according to an amount of data provided from a host and further argues that Cheon merely classifies write data as random or sequential based on a threshold rather than selecting a buffer memory based on an amount of data.
The argument is not persuasive.
The rejection does not rely on Maekawa for teaching selection based on an amount of data provided from host. Rather Maekawa is relied on for teaching first and second MRAM memory regions (11a, 11b) having different operating parameters, including different write speeds and retention characteristics (figures 9, 12, 15, 20). Cheon is relied upon for teaching selection between different memory buffers according to an amount of data received from host. Specifically, Cheon teaches determining whether a size of write-requested data satisfies a reference value (figure 6, S611) and selecting between different memories based on that determination. Applicant’s assertion that Cheon selects memory based solely on write pattern rather than amount of data is not persuasive because Cheon determines the write pattern from the amount of incoming data. See Cheon [0035], which teaches determining a random pattern when the number of continuously received sectors is less than a reference value and determining a sequential pattern when the number exceeds the reference value. Thus the memory selection ultimately depends on the amount of data received from the host.
Accordingly, the Examiner maintains the position previously set forth.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOCHUN L CHEN whose telephone number is (571)272-0941. The examiner can normally be reached M-F: 9AM-5:00PM.
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/XIAOCHUN L CHEN/Primary Examiner, Art Unit 2824
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