DETAILED ACTION
This Office action is in response to the filing of this application on 07 August 2024. Claims 1-20 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-17 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Su et al., US 2021/0336019.
With respect to claim 1, Su et al. disclose an integrated circuit device, shown in Fig. 2, comprising:
a substrate 127;
a power delivery network layer 122/124 including a lower interconnection line 124, on a bottom surface of the substrate 127;
source/drain patterns 106/108 including horizontally spaced-apart first and second patterns 106/108, on the substrate 127;
a backside conductive structure 120/118 that penetrates the substrate and electrically connects the first pattern 106 to the power delivery network layer 122/124; and
a lower insulating pattern 126/212 extending below the second pattern 108, and in contact with a portion of the lower interconnection line 124.
With respect to claim 2, in the device of Su et al., the backside conductive structure 120 comprises a backside conductive pattern 120/118 and a backside barrier pattern 118 enclosing the backside conductive pattern 120.
With respect to claim 3, the device of Su et al. further comprises: an active contact 114, which is electrically connected to the second pattern 108, see Fig. 2 and paragraph [0053].
With respect to claim 4, in the device of Su et al., the lower insulating pattern126/212 has a first height in a direction perpendicular to the substrate 127; and wherein the backside conductive structure 120/118 has a second height in the direction perpendicular to the substrate 127, which is larger than or equal to the first height. The height of the backside conductive structure 120/118 is higher than the height of 126, as shown in Fig. 2.
With respect to claim 5, in the device of Su et al., the height of the backside conductive structure 120/118 is equal to the height of 126, as shown in Fig. 2 Therefore,
the first and second heights are equivalent.
With respect to claim 6, in the device of Su et al., a level of a bottom surface of the lower insulating pattern 126/212 is equal to a level of a bottom surface of the backside conductive structure 120/118. The level of the bottom surface of 126 is equal to a level of a bottom surface of the backside conductive structure 120/118, as shown in Fig. 2
With respect to claim 7, in the device of Su et al., opposite side surfaces of the lower insulating pattern 126/212 have a curved shape, as shown in Fig. 2. .As shown in Fig. 2, opposite side surfaces of 126 on opposite sides of the backside conductive structure 120/118 have a curved shape.
With respect to claim 8, the opposite side surfaces has a shape that is convex toward the substrate 127, as shown in Fig. 2.
With respect to claim 9, in the device of Su et al., the substrate 127 (see paragraph [0059]) and the lower insulating pattern 126/212 (see paragraphs [0024]) comprise different insulating materials relative to each other, for example, substrate 127 can comprise oxide and the lower insulating pattern 126/212 can comprise nitride.
With respect to claim 10, the substrate 127 and the lower insulating pattern 126/212 can comprise the same material, for example, both can comprise oxide, see paragraphs [0059] and [0024].
With respect to claim 11, in the device of Su et al., the substrate 127 comprises at least one of silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON), see paragraph [0059], and the lower insulating pattern 126/212 comprises at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), or aluminum nitride (AlN), see paragraph [0024].
With respect to claim 12, Su et al. disclose an integrated circuit device, shown in Fig. 2, comprising:
a substrate 127;
a power delivery network layer 122 on a bottom surface of the substrate 127;
source/drain patterns 106/108 including horizontally spaced-apart first and second patterns 106 and 108 on the substrate, as shown in Fig. 2;
a channel pattern 102, which extends on a side surface of at least one of the first pattern 106 and the second patterns 108 and includes a stack of a plurality of spaced-apart semiconductor patterns 102, as shown in Fig. 2;
a gate electrode 104 extending between the spaced-apart semiconductor patterns 102, as shown in Fig. 2;
a backside active contact 120 that penetrates the substrate and electrically connects the first pattern 106 to the power delivery network layer 122, as shown in Fig. 2; and
a lower insulating pattern 126/212 extending below the second pattern 108, said lower insulating pattern 126/212 having an uppermost surface that is located at a level lower than or equal to an uppermost surface of the backside active contact 120/118, as shown in Fig. 2.
With respect to claim 13, in the device of Su et al., the uppermost surface of the lower insulating pattern 126/212 is located at a first level in a direction perpendicular to the substrate 127; wherein the uppermost surface of the backside active contact 120/118 is located at a second level in the direction perpendicular to the substrate 127; and wherein the second level is higher than or equal to the first level. As shown in Fig. 2 of Su et al., the second level is equal to the first level, since the uppermost surface of 120/118 is higher than the level of the uppermost surface of 126.
With respect to claim 14, in the device of Su et al., the gate electrode 104 comprises a first inner electrode, a second inner electrode, and a third inner electrode, which extend between adjacent ones of the spaced-apart semiconductor patterns 102, and an outer electrode 104, which is provided on the uppermost one of the spaced-apart semiconductor patterns 102; and wherein the second level is higher than a bottom surface of the first inner electrode and is lower than a top surface of the first inner electrode, as shown in annotated Fig. 2 below.
PNG
media_image1.png
765
785
media_image1.png
Greyscale
With respect to claim 15, in the device of Su et al., the gate electrode 104 comprises a first inner electrode, a second inner electrode, and a third inner electrode, which extend between adjacent ones of the spaced-apart semiconductor patterns 102, and an outer electrode 104, which is provided on the uppermost one of the spaced-apart semiconductor patterns 102; and a gate insulating pattern enclosing the first inner electrode (see Fig. 2 and paragraph [0019]); and wherein the uppermost surface of the lower insulating pattern is located at the same level as a bottom surface of the gate insulating pattern, as shown in annotated Fig. 2 below.
PNG
media_image2.png
755
858
media_image2.png
Greyscale
With respect to claim 16, in the device of Su et al., the uppermost surface of the backside active contact 120/118 is located at a level that is higher than a bottom surface of the gate insulating pattern and is lower than a top surface of the gate insulating pattern, as shown in annotated Fig. 2 below.
PNG
media_image3.png
739
866
media_image3.png
Greyscale
With respect to claim 17, in the device of Su et al., the backside active contact 120/118 comprises at least one of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, or Co, see paragraph [0021].
Allowable Subject Matter
Claims 18-20 are allowable over the prior art of record.
The following is a statement of reasons for the indication of allowable subject matter: The closest prior art of record is Su et l., as applied in the above rejection of claims 1-17. However, Su et al. fail to teach or suggest an integrated circuit device comprising: a gate capping pattern on a top surface of the outer electrode; a first interlayer insulating layer on the source/drain patterns; a second interlayer insulating layer on the first interlayer insulating layer and the gate capping pattern; a third interlayer insulating layer on the second interlayer insulating layer, said third interlayer insulating layer including metal patterns and vias; an active contact that penetrates the first and second interlayer insulating layers and electrically connects the second pattern of the source/drain pattern to the metal pattern, as required in independent claim 18.
Claims 19 and 20 are allowable by virtue of their dependence on independent claim 18.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additionally cited references disclose integrated circuit devices having backside conductive structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARY A WILCZEWSKI whose telephone number is (571)272-1849. The examiner can normally be reached M-TH 7:30 AM-5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
