DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and examined.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by PGPub. 2020/0144293 to Majhi et al. (hereafter Majhi).
Regarding independent claim 1, Majhi teaches a neuromorphic device comprising:
a plurality of bit lines (memory device 908 of FIG. 9, plurality of bit lines are represented with bit line 832 of FIG. 8, see par. [0095]);
a plurality of word lines (memory device 908 of FIG. 9, plurality of word lines are represented with word line 836 of FIG. 8, see par. [0095]); and
a non-volatile memory array including an ambipolar transistor disposed in a region where the bit lines and the word lines intersect (FIG. 8: FeFET 834, also see FIGS. 1A-1B and par. [0028]-[0033]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-20 are rejected under 35 U.S.C. 103 as being unpatentable over Majhi in view of PGPub. 2024/0303484 to Grollier et al. (hereafter Grollier).
Majhi teaches, as applied in prior rejection of claim 1, all claimed subject matter except further limitations set forth in the following claim(s).
Regarding dependent claim 2, Grollier teaches a neuromorphic device comprising synaptic devices (FIG. 1: synapse 24), wherein each synapse is produced by a set of two memristors (FIG. 4: synapse 24 comprising two memristors 24) using ferroelectric tunnel junctions for non-volatile function (see par. [0083]-[0084]), wherein the synapse is responsive to both positive and negative voltage pulse to produce positive and negative weights (see FIG. 5 and par. [0082]-[0095]).
Since Majhi and Grollier are both from the same field of endeavor, the purpose disclosed by Majhi would have been recognized in the pertinent art of Grollier.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the ambipolar transistor of Majhi as a synapse for the a neuromorphic device of Grollier for simplicity because the ambipolar transistor of Majhi is responsive to both positive and negative voltage pulse.
Regarding dependent claim 3, Grollier teaches wherein the non-volatile memory array performs two-layer operation by implanting different weights in two current regions present in the ambipolar transistor (FIG. 4: synapse 24 comprising two memristors 24, each memristor is corresponding to one current region).
Regarding dependent claim 4, Grollier teaches wherein the non-volatile memory array alternately applies specific voltages of first and second polarities to word lines and bit lines connected to specific synaptic devices among the plurality of bit lines and the plurality of word lines to perform weight implantation for multi-layer learning (see FIG. 5 and par. [0084]-[0095]).
Regarding dependent claim 5, Grollier teaches applying a specific voltage of a first polarity to a memristor of a synapse, and applying a specific voltage of a second polarity different from the first polarity to the other memristor of the synapse to implant different weights in the respective regions (see FIGS. 4-5 and par. [0084]-[0095]).
Majhi teaches the ambipolar transistor having forward region responsive to a positive voltage pulse, and a ambipolar region responsive to a negative voltage pulse (see FIG. 3C).
Regarding dependent claim 6, Grollier teaches wherein the non-volatile memory array performs weight implantation by applying a specific voltage to a word line (FIG. 1: e.g. applying u1 to first horizonal line, wherein u1 may be waveform in FIG. 5) and a bit line (FIG. 1: e.g. generating current I on vertical line) connected to a target device among the plurality of bit lines and the plurality of word lines, and implicitly allowing the remaining word lines and bit lines to be grounded or floating (i.e. when other horizonal lines and vertical lines are not selected).
Regarding independent claim 7, Grollier teaches multi-layer artificial neural network processing neuromorphic device, comprising:
a plurality of bit lines arranged to extend along a first direction (FIG. 1: vertical lines);
a plurality of word lines extending along a second direction perpendicular to the first direction (FIG. 1: horizontal lines); and
a plurality of synaptic devices located in regions where the bit lines and the word lines intersect (FIG. 1: synaptic devices 24),
wherein the synaptic device FIG. 4: synapse 24 comprising two memristors 24, each memristor is corresponding to one current region).
Grollier does not teach the synaptic device includes an ambipolar transistor.
Majhi teaches a non-volatile memory cell including an ambipolar transistor (FIG. 8: FeFET 834, also see FIGS. 1A-1B and par. [0028]-[0033]).
Since Grollier and Majhi are both from the same field of endeavor, the purpose disclosed by Majhi would have been recognized in the pertinent art of Grollier.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the ambipolar transistor of Majhi as a synapse for the a neuromorphic device of Grollier for simplicity because the ambipolar transistor of Majhi is responsive to both positive and negative voltage pulse.
Regarding dependent claim 8, Majhi teaches wherein the ambipolar transistor includes a tunneling transistor or a ferroelectric tunneling transistor (FIGS. 1A-1B: the transistor is ferroelectric transistor).
Regarding dependent claim 9, Majhi teaches wherein the ambipolar transistor has two or more different current mechanisms depending on a gate voltage, and includes a forward region and an ambipolar region with symmetrical current characteristics as a function of voltage (see FIGS. 1A-1B and FIG. 3C).
Regarding dependent claim 10, Majhi teaches wherein in a non-volatile memory device based on the ambipolar transistor, the forward region and the ambipolar region.
Grollier teaches the two memristors are each controlled to store two weights in one synaptic device (see FIGS. 4-5 and par. [0084]-[0095]).
Regarding dependent claim 11, Grollier teaches wherein when different weights are stored in two memristors, two analog vector matrix multiplications (VMM) are performed in one synapse array (because of positive and negative voltage pulses).
Majhi teaches different weights are stored in the forward region and the ambipolar region of ambipolar transistors.
Regarding independent claim 12, Grollier teaches an operation method of a neuromorphic device using a synaptic device disposed in an array of non-volatile memory formed along a plurality of bit lines and a plurality of word lines (see FIG. 1), the method comprising:
implanting a first weight in a first region of the synaptic device (FIG. 4: in first memristor 30 of synaptic device 24);
implanting a second weight in a second region of the synaptic device (FIG. 4: in second memristor 30 of synaptic device 24);
performing a first layer operation using a current in the first region and the implanted first weight (FIG. 4: e.g. writing one of positive and negative weight to the synaptic device 24); and
performing a second layer operation using a current in the second region and the implanted second weight (FIG. 4: e.g. writing the other of positive and negative weight to the synaptic device 24).
Grollier does not teach the synaptic device includes an ambipolar transistor.
Majhi teaches a non-volatile memory cell including an ambipolar transistor (FIG. 8: FeFET 834, also see FIGS. 1A-1B and par. [0028]-[0033]).
Since Grollier and Majhi are both from the same field of endeavor, the purpose disclosed by Majhi would have been recognized in the pertinent art of Grollier.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the ambipolar transistor of Majhi as a synapse for the a neuromorphic device of Grollier for simplicity because the ambipolar transistor of Majhi is responsive to both positive and negative voltage pulse.
Regarding dependent claim 13, Majhi teaches wherein the ambipolar transistor has two or more different current mechanisms depending on a gate voltage, and includes a forward region and an ambipolar region with symmetrical current characteristics as a function of voltage (see FIGS. 1A-1B).
Regarding dependent claim 14, Majhi teaches wherein the implanting of the first weight includes applying a specific voltage of a first polarity to a gate of the ambipolar transistor to perform weight implantation in one of a forward region and an ambipolar region of the ambipolar transistor (see FIGS 1A and 3B for hole accumulation).
Regarding dependent claim 15, Majhi teaches wherein the implanting of the second weight includes applying a specific voltage of a second polarity to the gate of the ambipolar transistor to perform weight implantation in the remaining region of the ambipolar transistor (see FIGS. 1B and 3B for electron accumulation).
Regarding dependent claim 16, Grollier teaches wherein in the implanting of the first weight and the implanting of the second weight, two weights are stored in one synaptic device (see FIG. 4)
Majhi teaches implanting weight by controlling a forward region and an ambipolar region of the ambipolar transistor (see FIGS. 1A-1B).
Regarding dependent claims 17-18, Grollier teaches wherein the performing of the first/second layer operation includes calculating with a weight of a memristor and adjusting a magnitude of an input signal through a voltage time applied to the memristor (see FIGS. 4-5 and par. [0152])
Majhi teaches implanting weight by controlling a forward region and an ambipolar region of the ambipolar transistor (see FIGS. 1A-1B).
Regarding dependent claims 19-20, Grollier teaches wherein the performing of the first/second layer operation includes performing a product operation of weight and voltage by reading a current in one of the memristors, and obtaining an operation result by sensing a current through an analog-to-digital converter (FIG. 4: through conveyor of current 60).
Majhi teaches the ambipolar transistor having forward region responsive to a positive voltage pulse, and a ambipolar region responsive to a negative voltage pulse (see FIG. 3C).
Conclusion
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March 4, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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