DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 05/12/2026 Amendment.
Claims 1-2, 4-8, 10-12, 14-20 are pending and examined. Claims 3, 9, 13 have been cancelled.
Claim Rejections - 35 USC § 112
Claims 1-2, 4-8, 10-12, 14-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites limitation “wherein the non-volatile memory array performs two-layer operation by implanting different weights in the forward region and the ambipolar region of the ambipolar transistor” on lines 10-13. Examiner is unable to support for this limitation in the disclosure.
Paragraph [58] of disclosure describes:
PNG
media_image1.png
475
756
media_image1.png
Greyscale
There appear paragraph [58] of the pending application describes an ambipolar transistor-based non-volatile memory can store two independent weights in one device. There is no description that each ambipolar transistor-based non-volatile memory device comprises one single ambipolar transistor. In addition, FIGS. 5A and 5B explain when forward region is controlled, the ambipolar region is inhibited, and vice versa. This implies an ambipolar transistor is either placed in forward region or ambipolar region, not both forward region and ambipolar region at the same instant moment.
For purpose of examination, Examiner interprets the limitations as -- wherein the non-volatile memory array performs two-layer operation by implanting different weights in the forward region and the ambipolar region of an ambipolar transistor-based device--.
Claim 7 recites limitation “wherein in a non-volatile memory device based on the ambipolar transistor, two layer operation is performed by implanting different weights in the forward region and the ambipolar region of the ambipolar transistor” on lines 13-15. Same rejection and interpretation as in claim 1 are applied herein.
Claim 12 recites limitations “implanting a first weight in one region of a forward region and an ambipolar region of the ambipolar transistor; implanting a second weight in another region of the forward region and ambipolar region of the ambipolar transistor” on lines 4-7. Same rejection as in claim 1 are applied herein. Examiner temporary does not consider claim 12 for prior art rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-8, 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over PGPub. 2020/0144293 to Majhi et al. (hereafter Majhi) in view of PGPub. 2024/0303484 to Grollier et al. (hereafter Grollier).
Regarding independent claim 1, Majhi teaches a neuromorphic device comprising:
a plurality of bit lines (memory device 908 of FIG. 9, plurality of bit lines are represented with bit line 832 of FIG. 8, see par. [0095]);
a plurality of word lines (memory device 908 of FIG. 9, plurality of word lines are represented with word line 836 of FIG. 8, see par. [0095]); and
a non-volatile memory array including an ambipolar transistor disposed in a region where the bit lines and the word lines intersect (FIG. 8: FeFET 834, also see FIGS. 1A-1B and par. [0028]-[0033]),
wherein the ambipolar transistor has two or more different current mechanisms depending on a gate voltage (each of the current mechanisms corresponding to one of FIGS. 1A-1B), and includes a forward region and an ambipolar region with symmetrical current characteristics as a function of voltage (see FIGS. 3A-3C and paragraphs [0040], and [0043]-[0044]), and
Majhi does not teach the strikethrough limitations.
Grollier teaches a neuromorphic device comprising synaptic devices (FIG. 1: synapse 24), wherein each synapse is produced by a set of two memristors (FIG. 4: synapse 24 comprising two memristors 24) using ferroelectric tunnel junctions for non-volatile function (see par. [0083]-[0084]), wherein the synapse is responsive to both positive and negative voltage pulse to produce positive and negative weights (see FIG. 5 and par. [0082]-[0095]).
Since Majhi and Grollier are both from the same field of endeavor, the purpose disclosed by Majhi would have been recognized in the pertinent art of Grollier.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the ambipolar transistor of Majhi as a synapse for the a neuromorphic device of Grollier for simplicity because the ambipolar transistor of Majhi is responsive to both positive and negative voltage pulse.
Regarding dependent claim 2, Majhi teaches wherein the non-volatile memory array uses ferroelectric tunnel junctions as a synaptic device. Grollier teaches ambipolar transistor has ferroelectric tunnel junction.
Regarding dependent claim 4, Grollier teaches wherein the non-volatile memory array alternately applies specific voltages of first and second polarities to word lines and bit lines connected to specific synaptic devices among the plurality of bit lines and the plurality of word lines to perform weight implantation for multi-layer learning (see FIG. 5 and par. [0084]-[0095]).
Regarding dependent claim 5, Grollier teaches applying a specific voltage of a first polarity to a memristor of a synapse, and applying a specific voltage of a second polarity different from the first polarity to the other memristor of the synapse to implant different weights in the respective regions (see FIGS. 4-5 and par. [0084]-[0095]).
Majhi teaches the ambipolar transistor having forward region responsive to a positive voltage pulse, and a ambipolar region responsive to a negative voltage pulse (see FIG. 3C).
Regarding dependent claim 6, Grollier teaches wherein the non-volatile memory array performs weight implantation by applying a specific voltage to a word line (FIG. 1: e.g. applying u1 to first horizonal line, wherein u1 may be waveform in FIG. 5) and a bit line (FIG. 1: e.g. generating current I on vertical line) connected to a target device among the plurality of bit lines and the plurality of word lines, and implicitly allowing remaining word lines and bit lines to be grounded or floating (i.e. when other horizonal lines and vertical lines are not selected).
Regarding independent claim 7, Grollier teaches multi-layer artificial neural network processing neuromorphic device, comprising:
a plurality of bit lines arranged to extend along a first direction (FIG. 1: vertical lines);
a plurality of word lines extending along a second direction perpendicular to the first direction (FIG. 1: horizontal lines); and
a plurality of synaptic devices located in regions where the bit lines and the word lines intersect (FIG. 1: synaptic devices 24),
wherein each of the plurality of the synaptic devices FIG. 4: synapse 24 comprising two memristors 24, each memristor is corresponding to one current region, FIG. 1 shows a plurality of synaptic devices),
wherein in a non-volatile memory device (FIG. 4: synapse 24 comprising two memristors 24) see FIG. 5 and par. [0082]-[0095])
Grollier does not teach the synaptic device includes an ambipolar transistor, but ferroelectric tunnel junctions for non-volatile function.
Majhi teaches a non-volatile memory cell including an ambipolar transistor (FIG. 8: FeFET 834, also see FIGS. 1A-1B and par. [0028]-[0033]), wherein the ambipolar transistor has two or more different current mechanisms depending on a gate voltage (each of the current mechanisms corresponding to one of FIGS. 1A-1B), and includes a forward region and an ambipolar region with symmetrical current characteristics as a function of voltage (see FIGS. 3A-3C and paragraphs [0040], and [0043]-[0044]).
Since Grollier and Majhi are both from the same field of endeavor, the purpose disclosed by Majhi would have been recognized in the pertinent art of Grollier.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the ambipolar transistor of Majhi as a synapse for the a neuromorphic device of Grollier for simplicity because the ambipolar transistor of Majhi is responsive to both positive and negative voltage pulse.
Regarding dependent claim 8, Majhi teaches wherein the ambipolar transistor includes a tunneling transistor or a ferroelectric tunneling transistor (FIGS. 1A-1B: the transistor is ferroelectric transistor).
Regarding dependent claim 10, Majhi teaches wherein in a non-volatile memory device based on the ambipolar transistor, the forward region and the ambipolar region.
Grollier teaches the two memristors are each controlled to store two weights in one synaptic device (see FIGS. 4-5 and par. [0084]-[0095]).
Regarding dependent claim 11, Grollier teaches wherein when different weights are stored in two memristors, two analog vector matrix multiplications (VMM) are performed in one synapse array (because of positive and negative voltage pulses).
Majhi teaches different weights are stored in the forward region and the ambipolar region of ambipolar transistors.
Response to Arguments
Applicant's arguments filed 05/12/2026 have been fully considered but they are not persuasive.
Applicant argues:
PNG
media_image2.png
469
701
media_image2.png
Greyscale
Examiner kindly refers Applicant to claim rejections under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, above. Examiner is unable to find support for the highlighted text in the arguments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
June 22, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
Prosecution Insights