Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1 and 5
b. Pending: 1-7
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 17/577,289, filed on 01/17/2022.
Information Disclosure Statement
The information disclosure statement (IDS) is submitted on 8/7/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Independent claims 1 and 5 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for refresh operation (see paragraph [0049]), does not reasonably provide enablement for “operation period” recited in independent claims.
All the dependent claims 2-4 and 6-7 carry the same deficit and henceforth are rejected.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Independent claims 1 and 5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are: refresh operation which is not recited in the independent claims but instead they recite “operation period” without further clarification.
All the dependent claims 2-4 and 6-7 carry the same deficit and henceforth are rejected.
Independent claims 1 and 5 recite the limitation " the input count" in line 5 and 2 respectively. There is insufficient antecedent basis for this limitation in the claim.
All the dependent claims 2-4 and 6-7 carry the same deficit and henceforth are rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe et al (US 20020080677) in view of Saifuddin et al. (US 20170316818).
Regarding independent claim 1, Watanabe discloses a semiconductor system (Fig. 3) comprising:
an active counting circuit (90; Fig. 27) configured to store a counting signal generated by counting the number of times that an active command is input during a test mode period (Fig. 27 and [0321] describes an ACT counter 90 which counts active command ACT), and generate an operation control signal for adjusting an operation period (Fig. 27 and [0321] describes generating control signal ACN<2:0>. Fig. 67 and [0565] describes test mode) when the input count of the active command is equal to or more than a preset count;
an operation information generation circuit (circuits GEN2-GEN0; Fig. 27) configured to receive the operation control signal, and generate operation information for adjusting the operation period (Fig. 27 and [0321]-[0322] shows GEN2-GEN0 receives signals ACN<2:0> and outputs main row-related control signals RCNTAA<2>-RCNTAC<2> and RCNTAA<1>-RCNTAC<1> and RCNTAA<0>-RCNTAC<0>. [0345] describes that main row-related control signals control the row-related control signals that are generated for a period from start of the row selection to the sense amplifier activation); and
a test control circuit (Fig. 67 shows test interface circuit 400 and logic 20. Together they form test control circuit) configured to generate a reset signal for resetting the counting signal when the test mode period is ended ([0051]-[0052] describes refresh counter with a reset circuit for resetting the count value to an initial value of "000 000 000" when the count value reaches "101.sub.--111111111". [0582] and Figs. 18, 68-70 describes reset mechanism).
Watanabe is silent about when the input count of the active command is equal to or more than a preset count;
However, Saifuddin teaches when the input count of the active command is equal to or more than a preset count ([0062] describes that a threshold number can be programmed into the registers such that if DRAM controller 280 receives a number of requests (e.g., from processor 270 for access to DRAM system 260) within a window of time which is less than the threshold, then the traffic may be determined to be light, causing DRAM controller 280 to direct DRAM system 260 to remain in the self-refresh state to service selected bank active commands);
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Saifuddin to Watanabe in order to provide method for accessing a DRAM array and performing low power self-correction by integrating a self-correction operation within a self-refresh cycle as taught by Saifuddin ([0075]).
Regarding claim 2, Watanabe and Saifuddin together disclose all the elements of claim 1 as above and through Watanabe further the test mode period is set to a constant time period ([0377] describes that sequence of edges of rising and falling of main row activating signals RCNTAA-RCNTAC is fixed and activation and deactivation of internal row control signals ACTA-ACTC are accordingly performed at fixed timings. That means the period is constant).
Regarding claim 3, Watanabe and Saifuddin together disclose all the elements of claim 1 as above and through Watanabe further the active counting circuit (90; Fig. 27) comprises:
a counter configured to generate the counting signal by counting the number of times that the active command is input (Figs. 27-28A and [0321]-[0327] describes an ACT counter 90 which counts active command ACT), from a point of time that a first pulse of a period signal is input to a point of time that a second pulse of the period signal is input, store the generated counting signal (Fig. 30 and [0345]), and reset the counting signal when the reset signal is input ([0324], [0329]-[0335] describes reset mechanism); and
Saifuddin teaches a comparison circuit configured to generate the operation control signal by comparing the counting signal and a comparison signal (Fig. 6 at step 610 does the comparison. So, a comparison circuit is inherently present).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Saifuddin to modified Watanabe in order to provide method for accessing a DRAM array and performing low power self-correction by integrating a self-correction operation within a self-refresh cycle as taught by Saifuddin ([0075]).
Regarding claim 4, Watanabe and Saifuddin together disclose all the elements of claim 1 as above and through Watanabe further the test control circuit generates a pulse of the period signal for setting the test mode period (Fig. 67, 69 and claim 14 recites a test control signal activated in a test mode).
Independent claim 5 recites the same claim limitations of independent device claim 1 in method format and henceforth rejected the same way.
Regarding claim 6, Watanabe and Saifuddin together disclose all the elements of claim 5 as above and through Watanabe further the operation period is set to a time period from a point of time that the active command is generated to a point of time that a precharge command is generated (Fig. 30 and [0344]).
Regarding claim 7, Watanabe and Saifuddin together disclose all the elements of claim 5 as above and through Watanabe further detecting that the active command is generated, when the pulse of the period signal for setting the test mode period is not generated; and counting the number of times that the active command is input (Fig. 27 and [0321] describes an ACT counter 90 which counts active command ACT before test mode).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SULTANA BEGUM whose telephone number is (571)431-0691. The examiner can normally be reached M-F 8 am - 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at 571272 1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SULTANA BEGUM/Primary Examiner, Art Unit 2824 1/16/2026