DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to an application filed on 07/20/2026.
Claim 2 is cancelled per the amendment.
Claims 1 and 3-20 are pending for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-6 and 17-19 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by An et al. (US 9,989,582 B2 and An hereinafter).
As to Claim 1, An in its teachings as shown in Fig.1-10 as best disclosed by Fig.3 disclose a measurement circuit (10, 20), comprising:
a current source (20) configured to provide a current to a drain terminal of a transistor (see Col.4, Line 1-6);
a voltage-measure circuit configured to measure a drain-to-source voltage of the transistor (Fig.3 shows the current source 20 output the measured voltage output VD); and
a regulator circuit (10) configured to:
receive from the voltage-measure circuit (Fig.3 shows the output of the current source VD being applied as an input to the regulator circuit 10) a voltage-measure signal indicative of the drain-to-source voltage of the transistor; and
regulate a gate-to-source voltage of the transistor (Fig.3 shows the voltage VD applied to an input of the operational amplifier 11) to be equal to the drain-to-source voltage of the transistor based on the voltage-measure signal (see Col.3, Line 57-67).
As to Claim 3, An disclose the measurement circuit of claim 1, wherein the regulator circuit comprises an enable input and is configured to regulate the gate-to-source voltage of the transistor based on the drain-to-source voltage of the transistor in response to an enable signal received at the enable input (see Fig.3 and Col.3, Line 58-67 and also Col.5, Line 10-22).
As to Claim 4, An disclose the measurement circuit of claim 3, wherein the voltage-measure signal corresponds to a gate threshold voltage (VG) of the transistor when the regulator circuit is enabled (see Fig.3 and Col.3, Line 58-67 and also Col.5, Line 10-22).
As to Claim 5, An disclose the measurement circuit of claim 4, wherein the voltage-measure signal corresponds to an on-state drain-to-source voltage of the transistor when the transistor is driven in an on-state and the regulator circuit is disabled (see Fig.3 and Col.3, Line 58-67 and also Col.5, Line 10-22).
As to Claim 6, An disclose the measurement circuit of claim 1, wherein the regulator circuit comprises: a reference input coupled to receive the voltage-measure signal; an gate-drive output coupled to a gate terminal of the transistor; and a feedback input coupled to the gate terminal of the transistor; and wherein the regulator circuit is configured to drive the gate terminal of the transistor based on a comparison of the reference input to the feedback input (An: see Fig.3 and 4 and also Col.3, Line 58-67 and also Col.5, Line 10-22).
As to Claim 17, An in its teachings as shown in Fig.1-10 as best disclosed by Fig.3 disclose a method, comprising:
providing a current (20) to a drain terminal of a transistor (NMOS);
measuring a drain-to-source voltage (VD) of the transistor;
regulating a gate-to-source voltage of the transistor to be equal to the drain-to-source voltage of the transistor (Fig.3 shows the voltage VD applied to an input of the operational amplifier 11 of the regulator circuit 10- see also (see Col.3, Line 61-67); and
determining a gate threshold voltage (VG) of the transistor based on the measured drain-to-source voltage of the transistor (The first operational amplifier 11 generates a gate voltage VG by amplifying a difference between a set voltage VSET and a drain voltage VD- see Col.3, Line 58-60).
As to Claim 18, An disclose the method of claim 17, further comprising generating a voltage-measure signal based on the drain-to-source voltage of the transistor (see Fig.3 and Col.3, Line 58-67).
As to Claim 19, An disclose the method of claim 18, wherein regulating the gate-to-source voltage comprises driving a gate terminal of the transistor based on a comparison of a gate voltage to the voltage-measure signal (An: see Fig.3 and 4 and also Col.3, Line 58-67 and also Col.5, Line 10-22).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 8-15 are rejected under 35 U.S.C. 103 as being unpatentable over Takamori et al. (US 2013/0207583 A1 and Takamori hereinafter) in view of An.
As to Claim 8, Takamori in its teachings as shown in Fig.1-5 disclose an inverter circuit (400), comprising:
a plurality of transistors (TRs) configured to drive an electric (700) motor (see also [0035] – [0036]); and
a gate drive circuit (300) including a plurality of gate drivers (310, 320) configured to respectively drive the plurality of transistors during an operating phase of the inverter circuit (see [0014])
Although an inverter circuit (400) and a plurality of transistors (TRs) as shown above, it doesn’t explicitly disclose:
a measurement circuit configured to measure a gate threshold voltage, wherein the measurement circuit comprises:
a current source configured to provide a current to a drain terminal of the transistor;
a voltage-measure circuit configured to measure a drain-to-source voltage of the transistor; and
a regulator circuit configured to:
receive from the voltage-measure circuit a voltage-measure signal indicative of the drain-to-source voltage of the transistor; and
regulate a gate-to-source voltage of the transistor to be equal to the drain-to-source voltage of the transistor based on the voltage-measure signal
Nonethless, An in its teachings as shown in Fig.1-10 as best disclosed by Fig.3 disclose a measurement circuit (10, 20) configured to measure a gate threshold voltage (VG) of a transistor (NMOS) comprising a current source (20) configured to provide a current to a drain terminal of a transistor (see Col.4, Line 1-6); a voltage-measure circuit configured to measure a drain-to-source voltage of the transistor (Fig.3 shows the current source 20 output the measured voltage output VD); and a regulator circuit (10) configured to: receive from the voltage-measure circuit (Fig.3 shows the output of the current source VD being applied as an input to the regulator circuit 10) a voltage-measure signal indicative of the drain-to-source voltage of the transistor; and regulate a gate-to-source voltage of the transistor (Fig.3 shows the voltage VD applied to an input of the operational amplifier 11) to be equal to the drain-to-source voltage of the transistor based on the voltage-measure signal (see Col.3, Line 57-67)
Therefore, it would have been obvious before the effective filing date of the instant application for an inverter circuit to include a measurement circuit configured to measure a gate threshold voltage as thought by An within the teachings of Takamori in order to monitor, calibrate, or compensate for device performance variations caused by manufacturing process fluctuations, temperature changes, or aging.
As to Claim 9, Takamori in view of An disclose the inverter circuit of claim 8, wherein: the inverter circuit includes a plurality of measurement circuits; and each of the plurality of measurement circuits is configured to measure the gate threshold voltage of a respective one of the plurality of transistors during the initialization phase of the inverter circuit (An: see the measurement circuits (10,20) of a transistor Fig.3 and 4 that can be used for plurality of Transistors and see also Col.3, Line 58-67 and also Col.5, Line 10-22 and Takamori [0035]-[0039]).
As to Claim 10, Takamori in view of An disclose the inverter circuit of claim 8, wherein each transistor of the plurality of transistors comprises a silicon-carbide metal-oxide semiconductor field-effect transistor (see [0038]).
As to Claim 11, Takamori in view of An disclose the inverter circuit of claim 8, wherein each transistor of the plurality of transistors comprises a silicon insulated-gate bipolar transistor (see [0038]).
As to Claim 12, Takamori in view of An disclose the inverter circuit of claim 8, wherein the regulator circuit comprises an enable input and is configured to regulate the gate-to-source voltage of the transistor based on the drain-to-source voltage of the transistor in response to an enable signal received at the enable input (An: see Col.3, Line 58-67 and also Col.5, Line 10-22).
As to Claim 13, Takamori in view of An disclose the inverter circuit of claim 12, wherein the voltage-measure signal corresponds to a gate threshold voltage of the transistor when the regulator circuit is enabled (An: see Fig.3 and 4 and also Col.3, Line 58-67 and also Col.5, Line 10-22).
As to Claim 14, Takamori in view of An disclose the inverter circuit of claim 13, wherein the voltage-measure signal corresponds to an on-state drain-to-source voltage of the transistor when the transistor is driven in an on-state and the regulator circuit is disabled (An: see Fig.3 and 4 and also Col.3, Line 58-67 and also Col.5, Line 10-22).
As to Claim 15, Takamori in view of An disclose the inverter circuit of claim 8, wherein the regulator circuit comprises: a reference input coupled to receive the voltage-measure signal; an gate-drive output coupled to a gate terminal of the transistor; and a feedback input coupled to the gate terminal of the transistor; and wherein the regulator circuit is configured to drive the gate terminal of the transistor based on a comparison of the reference input to the feedback input (An: see Fig.3 and 4 and also Col.3, Line 58-67 and also Col.5, Line 10-22).
Claims 7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over An in view of Li et al. (US 2018/0102773).
As to Claims 7 and 20, An disclose the measurement circuit of claim 1 and the method of claim 18, however, it doesn’t explicitly disclose:
an analog-to-digital converter coupled to the voltage-measure circuit and configured to output a digital signal corresponding to an analog value of the voltage-measure signal
Nonethless, Li in its teachings as shown in Fig.1-5 disclose that the Vgth measurement of the threshold voltage can be determined by using Analog to digital (ADC) converter that samples voltage across the collector-emitter terminals or gate emitter terminals of IGBT 201 in connection with selection by multiplexer MUX (see also [0015] – [0016])
Therefore, it would have obvious before the effective filing date of the instant application to include an analog-to-digital converter coupled to the voltage-measure circuit as thought by Li within the teachings of An to translate continuous physical signals (like voltage, temperature, or pressure) into discrete, digital binary numbers that computers, microcontrollers, and digital systems can process, display, or store.
Claim 16 are rejected under 35 U.S.C. 103 as being unpatentable over Takamori in view of An and in further view of Li.
As to Claim 16, Takamori in view of An disclose the inverter circuit of claim 8, however, it doesn’t explicitly disclose:
an analog-to-digital converter coupled to the voltage-measure circuit and configured to output a digital signal corresponding to an analog value of the voltage-measure signal
Nonethless, Li in its teachings as shown in Fig.1-5 disclose that the Vgth measurement of the threshold voltage can be determined by using Analog to digital (ADC) converter that samples voltage across the collector-emitter terminals or gate emitter terminals of IGBT 201 in connection with selection by multiplexer MUX (see also [0015] – [0016])
Therefore, it would have obvious before the effective filing date of the instant application to include an analog-to-digital converter coupled to the voltage-measure circuit as thought by Li within the teachings of Takamori and An to translate continuous physical signals (like voltage, temperature, or pressure) into discrete, digital binary numbers that computers, microcontrollers, and digital systems can process, display, or store.
Response to Arguments/Remarks
As to applicant’s argument “…Applicant respectfully submits that the cited art does not disclose the subject matter of independent Claims 1, 8, and 17, which are thus patentable. For example, the cited art fails to disclose "a regulator circuit configured to ... regulate a gate-to-source voltage of the transistor to be equal to the drain-to-source voltage of the transistor based on the voltage-measure signal," as recited by independent Claims 1 and 8 as amended. Further the cited art fails to disclose "regulating a gate-to-source voltage of the transistor to be equal to the drain-to-source voltage of the transistor," as recited by independent Claim 17 as amended… (Remarks 6-8)”
In response to applicant’s argument, the examiner respectfully disagrees with the applicant’s assertion. The examiner would also like to emphasize that the claims are examined enlight of the specification using the broadest reasonable interpretation (BRI) as cited in the previous office action of record. In addition, in contrary to applicant’s argument, An as cited in the previous office action of record 05/13/2026 and further cited in this office action, it clearly teaches what is broadly claimed by the applicant in which drain voltage VD of the NMOS transistor N becomes substantially equal to the set voltage VSET that has a constant level (see Col.3, Line 62-64) and this alone reads on what is amended and argued by the applicant. Hence, the claimed and argued limitations of independent claims 1, 8 and 17 along its respective dependent claims 3-7, 9-16 and 18-20 remain rejected. In conclusion, applicant’s arguments/remarks filed on 07/20/2026 have been fully considered but they are not persuasive as shown above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GABRIEL AGARED/Primary Examiner, Art Unit 2837
