DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: SEMICONDUCTOR DEVICE WITH DC-DC CONVERTER
Claim Interpretation
Applicant has recited “and/or” in several claims (e.g. see claim 6), which is the equivalent either “and” or “or”, and as such, it reads on “or”. As such, it denotes a limitation with options wherein only one option is required to satisfy the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-24 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 20210118759), hereinafter Yu, in view of Herbert (US 20080024102), hereinafter Herbert.
Regarding claim 1, Yu (US 20210118759) teaches a semiconductor device comprising:
a first circuit layer (10, described in para 21 as “a processor device 10” – see Figure 5) comprising at least an integrated circuit (para 21); and
a second circuit layer (comprising 20, 104, 106 – see Figure 5) comprising at least a current supply (20, para 28 describes "power gating device 20” – see Figure 5) configured to supply the integrated circuit with electrical energy (para 28 describes "power gating device 20 is part of the power delivery network for the processor device 10");
the second circuit layer comprising a first region (region of 20) comprising a semiconductor material (22, described as "the power gating device 20 includes a semiconductor substrate 22" in para 29 – see Figure 3 and 5) and at least a second region comprising a mold material (104, described as "a dielectric layer 104" which may be "a molding compound" in para 37), wherein the first and second regions extend over (best seen in Figures 3 and 5) the width of the first circuit layer;
wherein a second main surface (i.e. upper horizontal surface of 10 in orientation of Figure 5) of the first circuit layer (10) is connected to a first or second main surface (i.e. lower or upper horizontal surface of 20/104/106 in orientation of Figure 5) of the second circuit layer (comprising 20, 104, 106);
wherein the second circuit layer (comprising 20, 104, 106) comprises one or more vias (106, described as "conductive vias 106" in para 38) which extend over (best seen in Figure 5) the thickness of the second circuit layer (comprising 20, 104, 106) and are configured to provide signal contact of the integrated circuit (i.e. integrated circuit of 10 – see Figure 5; also see para 36 and 40); and
wherein the one or more vias extend through a mold material (104) of the second circuit layer (comprising 20, 104, 106),
Yu does not disclose that the current supply comprises specifically “a DC-DC converter”. However, para 32 of Yu teaches “power gating device 20” can include switching elements such as “switch transistors”, power gating controllers and MOSFET devices. Further, Herbert (US 20080024102) teaches that DC-DC converters are switching power supplies that typically comprises components such as MOSFETs and power regulating controller (para 8). It would have been obvious to one of ordinary skills in the art before the effective filing of the claimed invention to modify Yu so that the current supply comprises specifically “a DC-DC converter”. The ordinary artisan would have been motivated to modify Yu for at least the purpose of using known components to configure a known power supply device such as a DC-DC converter that can accept unregulated voltage from an unregulated voltage source and convert it to regulated voltage as per requirement of the integrated circuit that is powered by the DC-DC converter (para 8 of Herbert).
Regarding claim 2, Yu teaches the semiconductor device in accordance with claim 1, wherein the connection of the second main surface (i.e. upper horizontal surface of 10 in orientation of Figure 5) of the first circuit layer (10) to the first or second main surface of the second circuit layer (comprising 20, 104, 106 – see Figure 5) comprises a direct connection, a direct bond connection, a bond connection, a connection with a contacting or a connection with a copper contacting (para 35 describes 10 and 20 are "directly bonded in a face-to-face manner", which reads on “a direct bond connection”).
Regarding claim 3, Yu teaches the semiconductor device in accordance with claim 1, wherein the integrated circuit (i.e. integrated circuit of 10) comprises logic/or a memory (para 27).
Regarding claim 4, Yu teaches the semiconductor device in accordance with claim 1, wherein the second circuit layer (comprising 20, 104, 106) covers the surface (i.e. upper surface in orientation of Figure 5) of the first circuit layer (10).
Regarding claim 5, Yu teaches the semiconductor device in accordance with claim 1, wherein the first main surface of the second circuit layer (comprising 20, 104, 106) comprises contacts (26; see para 35 describes "the die connectors 16A” of 10 are bonded to “the die connectors 26” of 20) when the second main surface serves for connecting to the first circuit layer (10), or (i.e. optional, and not required limitation) wherein the second main surface of the second circuit layer comprises contacts when the first main surface serves for contacting with the first circuit layer.
Regarding claim 6, Yu teaches the semiconductor device in accordance with claim 1, wherein the semiconductor device comprises contacts on a main surface (i.e. upper horizontal surface of 20 that is closest to 114 in orientation of Figure 5) of the second circuit layer (comprising 20, 104, 106) facing away (best seen in Figure 5) from the first circuit layer (10), wherein the contacts are arranged in the first region (i.e. region of 22) and are configured to conduct a current/voltage signal for voltage supply (para 36 describes “may receive power/ground signals” from 20; also see para 35), and/or (i.e. an optional scenario – see claim interpretation note above) wherein the contacts are arranged in the second region and are configured to conduct a control signal (para 35-36).
Regarding claim 7, Yu teaches the semiconductor device in accordance with claim 1, wherein the current supply (20) comprises contacts (114) for contact to external circuits and the current supply (20) comprises a DC-DC converter (as explained for claim 1), but does not specifically state that the DC-DC converter current supply is configured “to provide, starting from an unregulated voltage applied of an unregulated voltage source, a regulated voltage on the side of the second main surface of the first circuit layer for current supply for the integrated circuit”; and/or wherein the contacts are “configured to be connected to an unregulated voltage source”. Herbert (US 20080024102) teaches DC-DC converter application is to accept unregulated voltage from an unregulated voltage source that is connected to the DC-DC converter via contacts, wherein the DC-DC converter is used to convert the unregulated voltage to a regulated voltage as per requirement of the integrated circuit that is powered by the DC-DC converter (para 8). It would have been obvious to one of ordinary skills in the art before the effective filing of the claimed invention to modify Yu so that the DC-DC converter current supply is configured “to provide, starting from an unregulated voltage applied of an unregulated voltage source, a regulated voltage on the side of the second main surface of the first circuit layer for current supply for the integrated circuit”; and/or wherein the contacts are “configured to be connected to an unregulated voltage source”. The ordinary artisan would have been motivated to modify Yu for at least the purpose of using DC-DC converter for a known functionality; i.e. the DC-DC converter functions to accept unregulated voltage from an unregulated voltage source and convert it to regulated voltage as per requirement of the integrated circuit that is powered by the DC-DC converter (para 8 of Herbert).
Regarding claim 8, Yu teaches the semiconductor device in accordance with claim 1, wherein the second circuit layer comprises one or more further vias (30, described as "conductive vias 30," in para 29 – best seen in Figure 5) which extend through the first region (i.e. region of 20 that includes 22) and are configured to transport a current/voltage signal to the current supply (para 44).
Regarding claim 9, Yu teaches the semiconductor device in accordance with claim 1, wherein the second main surface of the first circuit layer (i.e. optional) and/or the second main surface (i.e. upper horizontal surface of 20/104/106 in orientation of Figure 5) of the second circuit layer comprise a rewiring sheet (108, described as "redistribution structure 108 " in para 40) and/or (i.e. optional) a device sheet.
Regarding claim 10, Yu teaches the semiconductor device in accordance with claim 1, but the embodiment of Figure 5 does not teach “a further circuit layer comprising an integrated circuit, logic and/or memory” is arranged on a first main surface (i.e. lower horizontal surface of 10 in orientation of Figure 5) of the first circuit layer (10). However, Yu teaches in the embodiment of Figure 16 that further integrated circuit packages (400, which may be “a memory package” – see para 67) may be attached to an existing integrated package (300 or 100 of Figure 16 – see para 67). It would have been obvious to one of ordinary skills in the art before the effective filing of the claimed invention to modify Yu to include a further circuit layer comprising an integrated circuit, logic and/or memory is arranged on a first main surface of the first circuit layer. The ordinary artisan would have been motivated to modify Yu for at least the purpose of creating semiconductor devices with increase memory capacity or that may serve as specific types of memory modules, such as LPDDR1 (para 71 of Yu).
Regarding claim 11, Yu teaches the semiconductor device in accordance with claim 1, wherein the integrated circuit of the first circuit layer is manufactured using a first semiconductor manufacturing technology, and wherein the at least one current supply of the second circuit layer is manufactured using a second semiconductor manufacturing technology; and wherein the first manufacturing technology differs from the second manufacturing technology (see para 126, which describes "first technology node" that is different from "second technology node"), and/or (i.e. optional, and not required) wherein the first semiconductor manufacturing technology comprises 3-nm or better technology.
Regarding claim 12, Yu teaches a manufacturing method for manufacturing a semiconductor device in accordance with claim 1, wherein the manufacturing method comprises connecting (by 30/26/16 – see Figure 5 and para 29; also see para 35) the first circuit layer (10) to the second circuit layer (comprising 20).
Regarding claim 13, Yu teaches the manufacturing method in accordance with claim 12, wherein connecting is performed by bonding, direct bonding or manufacturing a contacting connection or copper contacting connection (para 35 describes 10 and 20 may be "directly bonded" and that material of 16 and 26 may be "copper").
Regarding claim 14, Yu teaches the manufacturing method in accordance with claim 12, wherein connecting is performed by means of face-to-back technology or face-to-face technology (para 35 describes 10 and 20 are "directly bonded in a face-to-face manner"; also see Figure 5).
Regarding claim 15, Yu teaches a manufacturing method for manufacturing a semiconductor device in accordance with claim 2, wherein the manufacturing method comprises connecting (by 30/26/16 – see Figure 5 and para 29; also see para 35) the first circuit layer (10) to the second circuit layer (comprising 20).
Regarding claim 16, Yu teaches a manufacturing method for manufacturing a semiconductor device in accordance with claim 3, wherein the manufacturing method comprises connecting (by 30/26/16 – see Figure 5 and para 29; also see para 35) the first circuit layer (10) to the second circuit layer (comprising 20).
Regarding claim 17, Yu teaches a manufacturing method for manufacturing a semiconductor device in accordance with claim 4, wherein the manufacturing method comprises connecting (by 30/26/16 – see Figure 5 and para 29; also see para 35) the first circuit layer (10) to the second circuit layer (comprising 20).
Regarding claim 18, Yu teaches a manufacturing method for manufacturing a semiconductor device in accordance with claim 5, wherein the manufacturing method comprises connecting (by 30/26/16 – see Figure 5 and para 29; also see para 35) the first circuit layer (10) to the second circuit layer (comprising 20).
Regarding claim 19, Yu teaches a manufacturing method for manufacturing a semiconductor device in accordance with claim 6, wherein the manufacturing method comprises connecting (by 30/26/16 – see Figure 5 and para 29; also see para 35) the first circuit layer (10) to the second circuit layer (comprising 20).
Regarding claim 20, Yu teaches a manufacturing method for manufacturing a semiconductor device in accordance with claim 7, wherein the manufacturing method comprises connecting (by 30/26/16 – see Figure 5 and para 29; also see para 35) the first circuit layer (10) to the second circuit layer (comprising 20).
Regarding claim 21, Yu teaches a manufacturing method for manufacturing a semiconductor device in accordance with claim 8, wherein the manufacturing method comprises connecting (by 30/26/16 – see Figure 5 and para 29; also see para 35) the first circuit layer (10) to the second circuit layer (comprising 20).
Regarding claim 22, Yu teaches a manufacturing method for manufacturing a semiconductor device in accordance with claim 9, wherein the manufacturing method comprises connecting (by 30/26/16 – see Figure 5 and para 29; also see para 35) the first circuit layer (10) to the second circuit layer (comprising 20).
Regarding claim 23, Yu teaches a manufacturing method for manufacturing a semiconductor device in accordance with claim 10, wherein the manufacturing method comprises connecting (by 30/26/16 – see Figure 5 and para 29; also see para 35) the first circuit layer (10) to the second circuit layer (comprising 20).
Regarding claim 24, Yu teaches a manufacturing method for manufacturing a semiconductor device in accordance with claim 11, wherein the manufacturing method comprises connecting (by 30/26/16 – see Figure 5 and para 29; also see para 35) the first circuit layer (10) to the second circuit layer (comprising 20).
Conclusion
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/AJAY ARORA/Primary Examiner, Art Unit 2892
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