DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 1, 1, 1, 3, 3, 4, 5, 9, 9, 9, 10, 16, 16, 16, 16, 16, 16, 16, and 20 respectively of U.S. Patent No. 12,087,016. Although the claims at issue are not identical, they are not patentably distinct from each other because, the claims of the instant application are obvious variant of the corresponding ones of the US Patent No. 12,087,016. Furthermore, the scopes of the claims on the instant application are also met and encompassed by the corresponding ones of the Patent No. 12,087,016.
The apparent difference between the conflicting claims mainly arises from the style of limitation recitation and relative placement of conflicting elements within the claims’ body.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5, 7, 8, 13-18, and 20 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by SHIMIZU (US 20190007634 A1).
Regarding claim 1, SHIMIZU discloses an image sensor (title, abstract, fig. 3) comprising:
a pixel array (13, fig. 3);
a plurality of readout circuits configured to receive signals from the pixel array (NC and SC, figs. 3-4, ¶0060-0061); and
one or more calibration readout circuits ( …calibration pixel circuit group (VCAL readout rows in FIG. 7) – ¶0072.
…electrically cuts off the pixel circuits belonging to the calibration pixel circuit group from vertical readout lines and supplies a calibration voltage to the vertical readout lines at the time when the pixel circuits belonging to the calibration pixel circuit group are read … - Abstract) configured to receive a calibration voltage (As shown in FIG. 13, the calibration operation involves a calibration readout process CAL. In the process CAL, a calibration voltage VCAL is read out from pixel circuits … - ¶0090, fig. 13. Also see Abstract as cited above), each calibration readout circuit corresponding to a subset of readout circuits in the plurality of readout circuits (ibid, …electrically cuts off the pixel circuits belonging to the calibration pixel circuit group from vertical readout lines and supplies a calibration voltage to the vertical readout lines at the time when the pixel circuits belonging to the calibration pixel circuit group are read … - Abstract.
As shown in FIG. 13, the calibration operation involves a calibration readout process CAL. In the process CAL, a calibration voltage VCAL is read out from pixel circuits … - ¶0090, fig. 13.).
Regarding claim 2, SHIMIZU discloses the image sensor of claim 1, wherein the plurality of readout circuits comprises first readout circuits disposed at a first location relative to the pixel array (NC is located north of pixel array 13, figs. 3-4) and second readout circuits disposed at a second location different than the first location, relative to the pixel array (SC is located south of pixel array 13, figs. 3-4. Also see ¶0058-063, Since the south column processing circuit SC and the north column processing circuit NC have the same circuit configuration…).
Regarding claim 3, SHIMIZU discloses the image sensor of claim 2, wherein the one or more calibration readout circuits comprise:
a first calibration readout circuit disposed by the first readout circuits; and
a second calibration readout circuit disposed by the second readout circuits (ibid, NC and SC are located north and south of pixel array 13, figs. 3-4. Also see ¶0058-063, Since the south column processing circuit SC and the north column processing circuit NC have the same circuit configuration…
When the image sensor 1 according to the first embodiment reads out an imaging signal Sig from a pixel circuit, the imaging signal Sig is input to an analog-digital converter circuit ADC via a vertical readout line VRL. On the other hand, when the image sensor 1 according to the first embodiment performs calibration operation, a calibration voltage VCAL is input into an analog-digital converter circuit ADC via a vertical readout line VRL. In other words, the analog-digital converter circuit ADC of the image sensor 1 according to the first embodiment generates imaging data Dsig having a digital value corresponding to the voltage level of the imaging signal Sig input via the associated vertical readout line VRL and also generates calibration data DCAL having a digital value corresponding to the voltage level of the calibration voltage VCAL. – ¶0063).
Regarding claim 5, SHIMIZU discloses the image sensor of claim 3, further comprising:
a calibration voltage generator configured to output the calibration voltage onto a column line that is coupled to the first and second calibration readout circuits (The pixel clamping circuits PCL apply a calibration voltage VCAL to the vertical readout lines VRL. – ¶0058, fig. 4).
Regarding claim 7, SHIMIZU discloses the image sensor of claim 3, further comprising:
one or more black pixels configured to output the calibration voltage onto a column line that is coupled to the first and second calibration readout circuits (…the image sensor 1 according to the first embodiment obtains calibration data DCAL using the pixel circuits arranged in the optical black pixel area – ¶0083, fig. 11.
The pixel clamping circuits PCL apply a calibration voltage VCAL to the vertical readout lines VRL. – ¶0058, fig. 4).
Regarding claim 8, SHIMIZU discloses the image sensor of claim 3, wherein the first calibration readout circuit comprises a first analog-to-digital converter and wherein the second calibration readout circuit comprises a second analog-to-digital converter (On the other hand, when the image sensor 1 according to the first embodiment performs calibration operation, a calibration voltage VCAL is input into an analog-digital converter circuit ADC via a vertical readout line VRL – ¶0063.
NC and SC are located north and south of pixel array 13, figs. 3-4. Also see ¶0058-063, Since the south column processing circuit SC and the north column processing circuit NC have the same circuit configuration…).
Regarding claim 13, SHIMIZU discloses Imaging circuitry (title, abstract, fig. 3) comprising:
a pixel array (13, fig. 3);
first readout circuits disposed along a first side of the pixel array (NC disposed along a north side of the pixel array 13, figs. 3-4);
second readout circuits disposed along a second side, different than the first side, of the pixel array (SC disposed along a south side of the pixel array 13, figs. 3-4);
a calibration voltage generator configured to generate a calibration voltage (…electrically cuts off the pixel circuits belonging to the calibration pixel circuit group from vertical readout lines and supplies a calibration voltage to the vertical readout lines at the time when the pixel circuits belonging to the calibration pixel circuit group are read … - Abstract
As shown in FIG. 13, the calibration operation involves a calibration readout process CAL. In the process CAL, a calibration voltage VCAL is read out from pixel circuits … - ¶0090, fig. 13.); and
one or more first calibration readout circuits configured to receive the calibration voltage (ibid, Abstract, ¶0090. NC and SC are located north and south of pixel array 13, figs. 3-4. Also see ¶0058-063, …Since the south column processing circuit SC and the north column processing circuit NC have the same circuit configuration… ).
Regarding claim 14, SHIMIZU discloses the imaging circuitry of claim 13, further comprising:
one or more second calibration readout circuits configured to receive the calibration voltage via a first column line (ibid, Abstract, ¶0090. NC and SC are located north and south of pixel array 13, figs. 3-4. Also see ¶0058-063, …Since the south column processing circuit SC and the north column processing circuit NC have the same circuit configuration…).
Regarding claim 15, SHIMIZU discloses the imaging circuitry of claim 14, further comprising:
one or more third calibration readout circuits configured to receive the calibration voltage via the first column line and a second column line separate from the first column line (this limitation is understood met, when different VRL lines are considered for receiving calibration voltage, see fig. 4).
Regarding claim 16, SHIMIZU discloses the imaging circuitry of claim 15, further comprising:
an error detection circuit configured to output an error signal based on signals output from one or more of: the one or more first calibration readout circuits, the one or more second calibration readout circuits, and the one or more third calibration readout circuits (…generates pixel data by applying a correction value to the imaging data while accumulating calibration data; and updates the correction value to an updated correction value generated based on a predetermined number of the calibration data pieces – Abstact. Also see ¶0066.
Limitation is understood me for one of the first, second and third calibration readout circuit).
Regarding claim 17, SHIMIZU discloses the imaging circuitry of claim 16, further comprising:
an averaging circuit coupled between the one or more second calibration readout circuits and the error detection circuit (fig. 16, division or averaging process).
Regarding claim 18, SHIMIZU discloses the imaging circuitry of claim 16, further comprising:
a first averaging circuit coupled between the one or more first calibration readout circuits and the error detection circuit; and
a second averaging circuit coupled between the one or more third calibration readout circuits and the error detection circuit (fig. 16, division or averaging process is applied for both NC and SC calibration circuits).
Regarding claim 20, SHIMIZU discloses a method of operating imaging circuitry comprising:
with a pixel array (13, fig. 13), capturing an image (title, abstract);
with first column readout circuits formed along a first peripheral edge of the pixel array (NC disposed along a north side of the pixel array 13, figs. 3-4), reading signals out from the pixel array via a first readout path (¶0063);
with second column readout circuits formed along a second peripheral edge of the pixel array (SC disposed along a south side of the pixel array 13, figs. 3-4), reading signals out from the pixel array via a second readout path (¶0063, Since the south column processing circuit SC and the north column processing circuit NC have the same circuit configuration…¶0058-0063); and
generating two or more calibration voltages to characterize the first readout path based on a first equation and to characterize the second readout path based on a second equation different than the first equation (¶0058-0063, long and short exposure signal collected in SC and NC is understood meeting the limitation, since long and short exposure have different inherent exposure time duration indicating following different equations).
Allowable Subject Matter
Claims 4, 6, 9-12, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Prior arts of record taken alone or in combination fails to reasonably disclose or suggest,
Regarding claim 4, an error detection circuit configured to output an error signal based on signals output from the first and second calibration readout circuits.
Regarding claim 6, wherein the calibration voltage generator is disposed at a midpoint of the column line between the first and second calibration readout circuits.
Regarding claim 9, a first reference voltage generator configured to output a first reference voltage to the first calibration readout circuit and to the first readout circuits; and a second reference voltage generator configured to output a second reference voltage to the second calibration readout circuit and to the second readout circuit.
Claims 10-11 are allowable for being dependent on allowable claim 9.
Claims 12 is allowable for being dependent on allowable claim 4.
Regarding claim 9, a weighting circuit configured to receive a first average value from the first averaging circuit, to receive a second average value from the second averaging circuit, and to output a weighted value based on the first and second average values to the error detection circuit.
Conclusion
The prior and/or pertinent art(s) made of record and not relied upon is considered pertinent to applicant's disclosure, are – Chen et al. (US 20150049231 A1), and Shaw (US 7368696 B2), who disclose different calibration circuits within image sensor.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHBAZ NAZRUL whose telephone number is (571)270-1467. The examiner can normally be reached M-Th: 9.30 am-3 pm, 6.30 pm-9 pm, F: 9.30 am-1.30 pm, 4 pm-8 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached on 571-272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAHBAZ NAZRUL/Primary Examiner, Art Unit 2638