Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1 and 5
b. Pending: 1-6
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) is submitted on 8/7/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-6 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 of copending Application No. 18/797,056 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because when we compare both sets, we find they recite the same claim limitations.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claims 1-6 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 of copending Application No. 18/796,791 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because when we compare both sets, we find they recite the same claim limitations.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Seo (US 20200152256) in view of Takahashi (US 20040136250) and Bains (US 10210925).
Regarding independent claim 1, Seo discloses a semiconductor system (Figs. 1, 10-11) comprising:
a controller (11; Fig. 1) configured to generate an active command applied to a semiconductor device on the basis of a command (Fig. 1 shows command ACT being generated and applied to memory device 100); and
Seo in Fig. 11 shows at steps S310 and S320 receiving and counting number of ACT command;
Further, Takahashi teaches the semiconductor device configured to adjust a period of a smart refresh operation in which word lines adjacent to an internal address are additionally activated when the input count of the active command during a test mode period is equal to or more than a preset count (Figs. 6-7 and [0045] describes that an active command signal ACT outputted from the command buffer circuit 12 is supplied to, for example, a counter 15a, together with a clock signal CLK. The counter 15a counts a selected time of a word line, and counts the clock signal CLK in response to the active command signal ACT. Specifically, the counter 15a is a so-called preset counter. A value corresponding to the maximum selected time of a word line is preset in the counter 15a, and the counter 15a generates an output signal when a counted value reaches the preset value).
Takahashi doesn’t teach word lines adjacent to an internal address are additionally activated,
However, Bains teaches word lines adjacent to an internal address are additionally activated (Fig. 1 and (21) describes that memory device 110 includes target row 112, which is the row of memory subject to hammering, or being accessed repeatedly within a given time period. The target row is the target of the row hammer event. In many modern memory devices, the architecture of the semiconductor layout causes one or more physically adjacent rows to be at risk of becoming corrupted. The rows at risk of becoming corrupted due to row hammer of target row 112 are illustrated as victim row 114 and victim row 116. Either or both of victim rows 114, 116 can be at risk, depending on the physical layout of memory device 110).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Takahashi and Bains to Seo in order to provide with control circuit which generates an internal precharge signal to precharge the bit lines in response to the active signal outputted from the command buffer circuit, the control circuit controls a time in which one of the word lines is kept selected as taught by Takahashi ([0013]) and manage memory, and more particularly sending a refresh command in response to a row hammer event as taught by Bains (Field) respectively.
Regarding claim 3, Seo, Takahashi and Bains together disclose all the elements of claim 1 as above and through Seo and Takahashi further the semiconductor device comprises:
a smart refresh control circuit configured to generate a smart refresh signal having a generation period that is adjusted by the input count of the active command during the test mode period (Seo in Fig. 11 shows at steps S310 and S320 receiving and counting number of ACT command. Takahashi in Figs. 6-7 and [0045] describes that an active command signal ACT outputted from the command buffer circuit 12 is supplied to, for example, a counter 15a, together with a clock signal CLK. The counter 15a counts a selected time of a word line, and counts the clock signal CLK in response to the active command signal ACT. Specifically, the counter 15a is a so-called preset counter. A value corresponding to the maximum selected time of a word line is preset in the counter 15a, and the counter 15a generates an output signal when a counted value reaches the preset value); and
Bains teaches a bank configured to perform the smart refresh operation of additionally activating word lines adjacent to the internal address when the smart refresh signal is input (Fig. 1 and (21) describes that memory device 110 includes target row 112, which is the row of memory subject to hammering, or being accessed repeatedly within a given time period. The target row is the target of the row hammer event. In many modern memory devices, the architecture of the semiconductor layout causes one or more physically adjacent rows to be at risk of becoming corrupted. The rows at risk of becoming corrupted due to row hammer of target row 112 are illustrated as victim row 114 and victim row 116. Either or both of victim rows 114, 116 can be at risk, depending on the physical layout of memory device 110. (32) describes a row of memory in a different memory bank can become the victim of the row hammer event. Address map 220 enables DRAM 210 to identify what row to refresh in response to the targeted refresh command).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Takahashi and Bains to modified Seo in order to provide with control circuit which generates an internal precharge signal to precharge the bit lines in response to the active signal outputted from the command buffer circuit, the control circuit controls a time in which one of the word lines is kept selected as taught by Takahashi ([0013]) and manage memory, and more particularly sending a refresh command in response to a row hammer event as taught by Bains (Field) respectively.
Regarding claim 4, Seo, Takahashi and Bains together disclose all the elements of claim 3 as above and through Seo further the smart refresh control circuit comprises:
an active counter (350; Fig. 10) configured to generate the counting signal by counting the number of times that the active command is input (Figs. 1, 10 and [0089] describes active command counter 350 of the memory device 300 may count the active command ACT from the memory controller 11),
Takahashi teaches during the test mode period, store the generated counting signal, and reset the counting signal after the test mode period (Figs. 7-8 and [0045]-[0046] describes that an active command signal ACT outputted from the command buffer circuit 12 resets the flip-flop circuit 15b, and the counter 15a starts a counting operation. If the next active command signal ACT is supplied during the counting operation, the counter 15a is reset, and a counting operation is repeated from the start);
Takahashi further teaches a smart refresh control signal generation circuit configured to generate a smart refresh control signal by comparing the counting signal and a comparison signal; and a smart refresh signal generation circuit configured to generate the smart refresh signal having a generation period that is adjusted on the basis of the smart refresh control signal (Figs. 6-7 and [0045] describes that an active command signal ACT outputted from the command buffer circuit 12 is supplied to, for example, a counter 15a, together with a clock signal CLK. The counter 15a counts a selected time of a word line, and counts the clock signal CLK in response to the active command signal ACT. Specifically, the counter 15a is a so-called preset counter. A value corresponding to the maximum selected time of a word line is preset in the counter 15a, and the counter 15a generates an output signal when a counted value reaches the preset value. That means there is a comparison done).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Takahashi to modified Seo in order to provide with control circuit which generates an internal precharge signal to precharge the bit lines in response to the active signal outputted from the command buffer circuit, the control circuit controls a time in which one of the word lines is kept selected as taught by Takahashi ([0013]).
Regarding independent claim 5, it recites combinations of independent device claim 1 and 4 in method format and henceforth rejected the same way.
Regarding claim 6, Seo, Takahashi and Bains together disclose all the elements of claim 5 as above and through Seo further detecting that the active command is generated, when the pulse of the period signal for setting the test mode period is not generated (Fig. 11 shows at step S310 where ACT command is received before any other steps); and
counting the number of times the active command is input (Fig. 11 shows at steps S310 and S320 receiving and counting number of ACT command).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Seo (US 20200152256) in view of Takahashi (US 20040136250) and Bains (US 10210925) and Lee (US 20060221745).
Regarding claim 2, Seo, Takahashi and Bains together disclose all the elements of claim 1 as above and through Lee further the test mode period is set to a constant time period (Claim 1 recites a first period selector for generating one of a period-fixed pulse signal having a constant period and a period-variable pulse signal having a variable period based on a temperature of the semiconductor memory device in a test mode).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Lee to modified Seo in order to provide with a technique for automatically changing a refresh period in a semiconductor memory device or pseudo SRAM as taught by Lee ([0001]).
Conclusion
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 1/14/2026