Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1 and 5
b. Pending: 1 and 3-6
Claims 1 and 5 have been amended and claim 2 has been canceled.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Information Disclosure Statement
The information disclosure statement (IDS) is submitted on 1/28/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Terminal Disclaimer
The terminal disclaimer filed on 4/14/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of copending Application No. 18/796,791 and copending Application No. 18/797,056 have been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention. Evidence that claims 5-6 fail to correspond in scope with that which the inventor or a joint inventor, or for pre-AIA applications the applicant regards as the invention can be found in the Remarks filed on 4/14/2026. In that paper, the inventor or a joint inventor, or for pre-AIA applications the applicant has stated in pg.: 7, “claimed invention is directed to a coordinated control
architecture in which a constant-duration test mode period defines a bounded time window, within which command activity is counted, reset at the boundary, and used to dynamically adjust operation timing”; and this statement indicates that the invention is different from what is defined in the claim(s) because claim 5 recites following two operations based on two conditions:
line: 4-5
“adjusting the input period of a refresh command when the input count of the active command is equal to or more than a preset count;”
and line: 6-7
“resetting the input count of the active command, when the input count of the active command is less than the preset count,”
Here Examiner asserts that second scenario where input count will be less than preset count will keep happening that will reset input count every time and it will prevent reaching the first scenario of adjusting refresh period. This is in direct contradiction with the invention.
Claim 6 depends on claim 5 and henceforth rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Seo (US 20200152256) in view of Takahashi (US 20040136250) and Lee (US 20200342934).
Regarding independent claim 1, Seo discloses a semiconductor system (Figs. 1, 10-11) comprising:
a controller (11; Fig. 1) configured to generate an active command applied to a semiconductor device on the basis of a command (Fig. 1 shows command ACT being generated and applied to memory device 100); and
Seo in Fig. 11 shows at steps S310 and S320 receiving and counting number of ACT command;
Further, Takahashi teaches the semiconductor device configured to adjust a period of a smart refresh operation in which word lines adjacent to an internal address are additionally activated when the input count of the active command during a test mode period is equal to or more than a preset count (Figs. 6-7 and [0045] describes that an active command signal ACT outputted from the command buffer circuit 12 is supplied to, for example, a counter 15a, together with a clock signal CLK. The counter 15a counts a selected time of a word line, and counts the clock signal CLK in response to the active command signal ACT. Specifically, the counter 15a is a so-called preset counter. A value corresponding to the maximum selected time of a word line is preset in the counter 15a, and the counter 15a generates an output signal when a counted value reaches the preset value), and wherein the test mode period is set to a constant time period.
Takahashi doesn’t teach word lines adjacent to an internal address are additionally activated, and wherein the test mode period is set to a constant time period.
However, Lee teaches word lines adjacent to an internal address are additionally activated, and wherein the test mode period is set to a constant time period (Fig. 10A and [0068] describes that victim rows may include rows that are physically adjacent to the aggressor row (e.g., HitXADD+1 and HitXADD−1). Further, in some embodiments, the victim rows may also include rows that are physically adjacent to the physically adjacent rows of the aggressor row (e.g., HitXADD+2 and HitXADD−2). Fig. 12 and [0077]-[0079] describes a fixed first time duration and counting number of active command during that first time. Examiner equates that first time as fixed test mode duration).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Takahashi and Lee to Seo in order to provide with control circuit which generates an internal precharge signal to precharge the bit lines in response to the active signal outputted from the command buffer circuit, the control circuit controls a time in which one of the word lines is kept selected as taught by Takahashi ([0013]) and decrease power consumption and processing overhead of a memory device without substantially decreasing performance and/or reliability of the memory device. Also, eliminate unnecessary row hammer refresh operations, thus reducing power consumption while still mitigating undesirable row hammer effects as taught by Lee ([0024]) respectively.
Regarding claim 3, Seo, Takahashi and Lee together disclose all the elements of claim 1 as above and through Seo and Takahashi further the semiconductor device comprises:
a smart refresh control circuit configured to generate a smart refresh signal having a generation period that is adjusted by the input count of the active command during the test mode period (Seo in Fig. 11 shows at steps S310 and S320 receiving and counting number of ACT command. Takahashi in Figs. 6-7 and [0045] describes that an active command signal ACT outputted from the command buffer circuit 12 is supplied to, for example, a counter 15a, together with a clock signal CLK. The counter 15a counts a selected time of a word line, and counts the clock signal CLK in response to the active command signal ACT. Specifically, the counter 15a is a so-called preset counter. A value corresponding to the maximum selected time of a word line is preset in the counter 15a, and the counter 15a generates an output signal when a counted value reaches the preset value); and
Lee teaches a bank configured to perform the smart refresh operation of additionally activating word lines adjacent to the internal address when the smart refresh signal is input (Fig. 12 and corresponding sections of the Specification).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Takahashi and Lee to modified Seo in order to provide with control circuit which generates an internal precharge signal to precharge the bit lines in response to the active signal outputted from the command buffer circuit, the control circuit controls a time in which one of the word lines is kept selected as taught by Takahashi ([0013]) and decrease power consumption and processing overhead of a memory device without substantially decreasing performance and/or reliability of the memory device. Also, eliminate unnecessary row hammer refresh operations, thus reducing power consumption while still mitigating undesirable row hammer effects as taught by Lee ([0024]) respectively.
Regarding claim 4, Seo, Takahashi and Lee together disclose all the elements of claim 3 as above and through Seo further the smart refresh control circuit comprises:
an active counter (350; Fig. 10) configured to generate the counting signal by counting the number of times that the active command is input (Figs. 1, 10 and [0089] describes active command counter 350 of the memory device 300 may count the active command ACT from the memory controller 11),
Takahashi teaches during the test mode period, store the generated counting signal, and reset the counting signal after the test mode period (Figs. 7-8 and [0045]-[0046] describes that an active command signal ACT outputted from the command buffer circuit 12 resets the flip-flop circuit 15b, and the counter 15a starts a counting operation. If the next active command signal ACT is supplied during the counting operation, the counter 15a is reset, and a counting operation is repeated from the start);
Takahashi further teaches a smart refresh control signal generation circuit configured to generate a smart refresh control signal by comparing the counting signal and a comparison signal; and a smart refresh signal generation circuit configured to generate the smart refresh signal having a generation period that is adjusted on the basis of the smart refresh control signal (Figs. 6-7 and [0045] describes that an active command signal ACT outputted from the command buffer circuit 12 is supplied to, for example, a counter 15a, together with a clock signal CLK. The counter 15a counts a selected time of a word line, and counts the clock signal CLK in response to the active command signal ACT. Specifically, the counter 15a is a so-called preset counter. A value corresponding to the maximum selected time of a word line is preset in the counter 15a, and the counter 15a generates an output signal when a counted value reaches the preset value. That means there is a comparison done).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Takahashi to modified Seo in order to provide with control circuit which generates an internal precharge signal to precharge the bit lines in response to the active signal outputted from the command buffer circuit, the control circuit controls a time in which one of the word lines is kept selected as taught by Takahashi ([0013]).
Regarding independent claim 5, it recites combinations of independent device claim 1 and 4 in method format and henceforth rejected the same way.
Regarding claim 6, Seo, Takahashi and Lee together disclose all the elements of claim 5 as above and through Seo further detecting that the active command is generated, when the pulse of the period signal for setting the test mode period is not generated (Fig. 11 shows at step S310 where ACT command is received before any other steps); and
counting the number of times the active command is input (Fig. 11 shows at steps S310 and S320 receiving and counting number of ACT command).
Response to Arguments
Applicant’s arguments with respect to independent claim 5 have been considered but are moot because of new ground of rejection.
Conclusion
Applicant's amendments/arguments necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 5/12/2026
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