DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 7, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
It is rather confusing to use the term “wordline voltage” when the voltage is being applied, not to a wordline, but rather to an SOT line. Also, WL is used in FIG. 7 to mean wordline so is Applicant sure that the “wordline voltage” is being applied to the SOT line and NOT to the line WL? Also, referring to “a state” twice in a sentence is rather confusing especially if they are two states that not even the same thing, such as one meaning a data state and the other meaning a physical state. One suggestion is to amend the paragraphs as follows:
[0006] Also provided herein is a physical unclonable function circuit including: a plurality of variable resistance cells, wherein each of the plurality of variable resistance cells includes: a Spin-Orbit Torque (SOT) line (SOT line) connected to a corresponding source line, wherein the SOT line is configured to be provided with a wordline voltage; a free layer formed on top of the SOT line; a tunnel barrier formed on top of the free layer; and a pinned layer formed on top of the tunnel barrier, and wherein a data state of each of target cells may be determined while in a state that an internal magnetic field is generated to reduce a stray field of the target cells among the plurality of variable resistance cells.
[0007] Also provided herein is a security circuit including: a physical unclonable function circuit configured to generate a random number; and a processor configured to generate a key using the random number, wherein the physical unclonable function circuit includes a PUF block, the PUF block includes a plurality of variable resistance cells connected to bitlines, source lines, read wordlines, and write wordlines, each of the plurality of variable resistance cells includes, a Spin-Orbit Torque (SOT) line (SOT line) connected to a corresponding source line among the source lines, wherein the SOT line is configured to be provided with a wordline voltage; a free layer formed above the SOT line; a tunnel barrier formed on top of the free layer; and a pinned layer formed on top of the tunnel barrier, and wherein a data state of each of target cells may be determined while in a state that an internal magnetic field is generated to reduce a stray field of the target cells among the plurality of variable resistance cells.
[0008] Also provided herein is an electronic device including: a host device configured to generate a challenge for an authentication operation; and an integrated circuit configured to generate a response corresponding to the challenge, wherein the integrated circuit is configured to receive the challenge, to generate a random number corresponding to an internal challenge, and to generate the response corresponding to the random number, wherein the random number is generated from a plurality of variable resistance cells, and wherein a data state of each of target cells may be determined while in a state that the integrated circuit is configured to generate an internal magnetic field to reduce a stray field of target cells among the plurality of variable resistance cells.
[0025] In example embodiments, MRAM ( Magnetoresistive Random Access Memory) may be used in PUF so that the PUF may generate security keys in a non-deterministic method.
[0027] A memory cell of MRAM may have an MTJ (magnetic tunnel junction) including two ferromagnetic layers separated by an insulating layer. The memory cell has two or more energy states representing data. For example, to represent data of one bit, a P (Parallel) state in which magnetization directions between the two ferromagnetic layers are parallel, and an AP (Anti-Parallel) state in which the magnetization directions between the two ferromagnetic layers are opposite to each other may be used.
[0032] SOT-MRAM adjusts the magnetization direction of the free layer from perpendicular to in-plane through in-plane spin current generated in the heavy metal layer, and switches the magnetic direction of the free layer to the P state or the AP state. To achieve random switching characteristics in which the P state and the AP state are each switched at a 50% probability, the energies of P state and the AP state of the free layer may be equal.
[0038] The PUF block 110 may generate a plurality of random signals RS based on signals generated by a plurality of PUF cells. Accordingly, the plurality of random signals RS may be different from random signals generated by a PUF block included in another security device of the same structure. In example embodiments, the PUF block 110 may generate an n-bit random signal RS (where n is an integer greater than 1). For example, the PUF block 110 may include n PUF cells, and each PUF cell may generate a random signal RS corresponding to 1-bit.
[0056] FIG. 4 is a diagram explaining the existence of a stray field in a general PUF circuit. Generally, the pinned layer PL is part of the MRAM cell, and the spin direction thereof is fixed. This pinned layer PL may form a magnetic field, referred to as a stray field. These stray fields may affect free energy level of the free layer FL at the P state and the AP state. In an example of FIG. 4, an energy level at the P state may be lower than an energy level at the AP state. The difference between [[of]] energy levels at the P state and the AP state makes it difficult to generate a pure random number using the MRAM cells.
[0068] The resistance cell RVC may be connected between the bitline BL and the SOT line 311. The resistance cell RVC may include a free layer FL, a tunnel barrier TB, and a pinned layer PL. The free layer FL may be formed on the SOT line 311. A tunnel barrier TB may be formed on top of the free layer FL. The pinned layer PL may be formed on the tunnel barrier TB. The bitline BL may be formed on the pinned layer PL. The first transistor T1 may connect the wordline voltage VWL to the SOT line 311 in response to the first switch signal SW1. In this case, the SOT line 311 may be connected to the source line SL. The second transistor T2 may provide the digit voltage VDL to the digit line 312 in response to the second switch signal SW2.
Appropriate correction is required.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description:
Regarding FIG. 7: the signal at the gate of T1 is currently “WL”, which causes confusion with the term “wordline voltage” since WL is the standard abbreviation for wordline then one may think that the wordline voltage VWL is meant to be applied to this line and not to the SOT line. Perhaps, “WL” should be changed to “SW1” to match the term used in [0068] of the specification, and “DL” should be changed to “SW2” to match the term used in [0068] of the specification.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 5, 11, 16, and 17 objected to because of the following informalities:
Regarding claim 5: To correct grammar:
The method of claim 4, wherein the generating a random number in the target cells and generating of the internal magnetic field further comprises applying a write voltage to a target SOT line, wherein the target SOT line corresponds to the target cells, and wherein the predetermined voltage is lower than the write voltage.
Regarding claim 11: To correct grammar:
A physical unclonable function circuit comprising:
a plurality of variable resistance cells,
wherein each of the plurality of variable resistance cells comprises:
a Spin-Orbit Torque (SOT) line (SOT line) connected to a corresponding source line, wherein the SOT line is configured to be provided with a wordline voltage;
a free layer formed on top of the SOT line;
a tunnel barrier formed on top of the free layer; and
a pinned layer formed on top of the tunnel barrier, and
wherein a data state of each of target cells may be determined while in a state that an internal magnetic field is generated to reduce a stray field of the target cells among the plurality of variable resistance cells.
Regarding claim 16: To correct grammar:
A security circuit comprising:
a physical unclonable function (PUF) circuit configured to generate a random number; and
a processor configured to generate a key using the random number,
wherein the PUF circuit comprises a PUF block,
wherein the PUF block comprises a plurality of variable resistance cells connected to bitlines, source lines, read wordlines, and write wordlines,
wherein each of the plurality of variable resistance cells comprises:
a Spin-Orbit Torque (SOT) line (SOT line) connected to a corresponding source line among the source lines, wherein the SOT line is configured to be provided with a wordline voltage;
a free layer formed above the SOT line;
a tunnel barrier formed on top of the free layer; and
a pinned layer formed on top of the tunnel barrier, and
wherein a data state of each of target cells may be determined while in a state that an internal magnetic field is generated to reduce a stray field of the target cells among the plurality of variable resistance cells.
Regarding claim 17. To correct grammar:
The security circuit of claim 16, wherein the PUF block further comprises:
a first switch configured to connect the pinned layer to a corresponding bitline among the bitlines based on to a first switch signal during a read operation; and
a second switch configured to connect the SOT line to the corresponding bitline based on a second switch signal during a write operation.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by De et al. (US 2019/0190725 A1).
Regarding claim 1: De teaches a method of operating a physical unclonable function circuit (a device of FIG. 5A, [0068-0071] operated using method of FIG. 6A-C, [0073-0076]) using Magnetoresistive Random Access Memory (MRAM) ([0069] discloses that cell 501 of FIG. 5A comprises the MTJ of FIG. 2A, [0041-0059]), comprising:
generating an internal magnetic field to reduce a stray field of target cells ([0044]; each memory cell has this cancelling field and target cells may be at least a portion of the memory cells 501 of a row of memory cells selected during a read operation); and
generating a random number (PUF array value or PUF_code) in the target cells by controlling a voltage applied to the target cells (see “bias voltages” in [0071] for reading).
Regarding claim 2: De teaches the method of claim 1, wherein the MRAM is a Spin-Orbit Torque Magnetoresistive Random-Access Memory (SOT-MRAM) (FIG. 2A illustrates a memory cell operating based on Spin Orbit Coupling or Spin Hall Effect; [0041, 0042, 0059]).
Regarding claim 3. De teaches the method of claim 1, wherein the MRAM includes a plurality of variable resistance cells,
wherein each of the plurality of variable resistance cells (FIG. 2A) comprises:
_____a SOT line (222) connected to a corresponding source line (204 or 205), wherein the SOT line is configured to be provided with a wordline voltage (a voltage is applied to the line via transistor 201 and/or 206 during reading and/or writing; [0055]);
_____a free layer (221a) formed on top of the SOT line;
_____a tunnel barrier (221b) formed on top of the free layer; and
_____a pinned layer (SAF layer comprising 221c-e) formed on top of the tunnel barrier and having a fixed spin direction, and
wherein the target cells are some of the plurality of variable resistance cells (a portion of a row of memory cells of the array selected for reading).
Regarding claim 11: De teaches a physical unclonable function circuit (a device of FIG. 5A, [0068-0071] operated using method of FIG. 6A-C, [0073-0076]) comprising:
a plurality of variable resistance cells ([0069] discloses that cell 501 of FIG. 5A comprises the MTJ of FIG. 2A, [0041-0059]), wherein each of the plurality of variable resistance cells (FIG. 2A) comprises:
_____a Spin-Orbit Torque (SOT) line (SOT line) (222) connected to a corresponding source line (204 or 205), wherein the SOT line is configured to be provided with a wordline voltage (a voltage is applied to the line via transistor 201 and/or 206 during reading and/or writing; [0055]);
_____a free layer (221a) formed on top of the SOT line;
_____a tunnel barrier (221b) formed on top of the free layer; and
_____a pinned layer (SAF layer comprising 221c-e) formed on top of the tunnel barrier, and wherein a state of each of target cells may be determined in a state that an internal magnetic field is generated to reduce a stray field of the target cells among the plurality of variable resistance cells ([0044]; each memory cell has this cancelling field and target cells may be at least a portion of the memory cells 501 of a row of memory cells selected during a read operation).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 16 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over De (2019/0190725 A1) in view of Goettfert (20170237573 A1).
Regarding claim 16: De teaches a circuit (a device of FIG. 5A or 5B, [0068-0072] operated using method of FIG. 6A-C, [0073-0076]) comprising:
a physical unclonable function (PUF) circuit configured to generate a random number (PUF array value or PUF_code); and
a server (521) configured to store a system identification (ID), and to receive the random number,
wherein the PUF circuit comprises a PUF block (PUF array 501),
wherein the PUF block comprises a plurality of variable resistance cells ([0069] discloses that cell 501 of FIG. 5A comprises the MTJ of FIG. 2A, [0041-0059]) connected to bitlines (202 in FIG. 2A), source lines (204 or 205 in FIG. 2A), read wordlines (one of 203 or 207), and write wordlines (the other one of 203 and 207),
wherein each of the plurality of variable resistance cells comprises:
_____a Spin-Orbit Torque (SOT) line (SOT line) (222) connected to a corresponding source line among the source lines, wherein the SOT line is configured to be provided with a wordline voltage (a voltage is applied to the line via transistor 201 and/or 206 during reading and/or writing; [0055]);
_____a free layer (221a) formed above the SOT line;
_____a tunnel barrier (221b) formed on top of the free layer; and
_____a pinned layer (SAF layer comprising 221c-e) formed on top of the tunnel barrier, and
wherein a state of each of target cells may be determined in a state that an internal magnetic field is generated to reduce a stray field of the target cells among the plurality of variable resistance cells ([0044]; each memory cell has this cancelling field and target cells may be at least a portion of the memory cells 501 of a row of memory cells selected during a read operation).
De does not specifically teach a processor configured to generate a key using the random number.
Goettfert ([0023]) teaches a PUF value P can be considered to be an identification number, and a cryptoprocessor which derives a chip-card-specific cryptographic key from an identification number or a CPU 104 itself derives a cryptographic key therefrom.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Goettfert into the device and/or method of De in a manner such that a processor within the server would be configured to generate a key using the random number. The motivation to do so would have been for security ([0023-0024] of Goeffert).
Regarding claim 20: De teaches the security circuit of claim 16, wherein the PUF circuit is configured to sequentially apply the wordline voltage to the plurality of variable resistance cells in a scan manner and generate the internal magnetic field (FIG. 6B; [0073-0076]).
Allowable Subject Matter
Claims 4-10, 12-15, 17-19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827