Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1 and 6
b. Pending: 1-7
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) is submitted on 8/7/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 4 is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 2. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim 5 is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 3. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-7 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6 of copending Application No. 18/796,927 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because when we compare both sets of claim, we find that same claim limitations are divided among multiple claims of the reference application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 20200342934).
Regarding independent claim 1, Lee discloses a semiconductor system (Figs. 1, 12) comprising:
a refresh control circuit (Fig. 10A) configured to generate refresh information for adjusting a refresh period, when the input count of an active command during a test mode period is equal to or more than a preset count ([0062] describes controller 1050 may be configured to count a number of times active signal ACT is received at the associated memory bank during a time interval (e.g., a steal series). In these embodiments, counters 1051 may be reset (e.g., via control logic) (e.g., at the end of the time interval). Further, based on the number of times active signal ACT is received at the associated memory bank (e.g., during the time interval), controller 1050 may generate a signal that is conveyed to RHR state control 1052. [0063] describes controller 1050 may be configured to count a number of active signals, and convey this information to RHR state control 1052. In these embodiments, RHR state control 1052 may be configured to determine whether or not a row hammer refresh operation should occur at the memory bank and/or at what rate a row hammer refresh should occur. Fig. 12 shows the flow diagram); and
a command generation circuit configured to generate the active command applied to a semiconductor device on the basis of a command (Fig. 1 and [0029] describes one or more command signals COM, received via command terminals 112, may be conveyed to a command decoder 150 via a command input circuit 152. Command decoder 150 may include a circuit configured to generate various internal commands via decoding one or more command signals COM. Examples of the internal commands include an active signal ACT, a read/write signal R/W, and a refresh signal AREF), and adjust the input period of a refresh command applied to the semiconductor device on the basis of the refresh information ([0052] describes in response to a memory bank not receiving at least a minimum threshold number (e.g., 1, 5, 10, 20, 50, etc.) of active commands (e.g., during a time interval), the row hammer refresh rate of the memory bank may be adjusted from a one row hammer refresh rate (e.g., a default row hammer refresh rate) to another, lower row hammer refresh rate (e.g., a minimum row hammer refresh rate). Further, for example, in response to a memory bank, which is operating with a reduced row hammer refresh rate (e.g., relative to a default row hammer refresh rate), receiving at least a minimum threshold number of active commands (e.g., during a time interval), the row hammer refresh rate of the memory bank may be adjusted from a lower row hammer refresh rate to a higher row hammer refresh rate (e.g., a default row hammer refresh rate)).
Regarding claim 2, Lee discloses all the elements of claim 1 as above and further the refresh control circuit (Fig. 10A) comprises:
a test control circuit configured to generate a period signal for setting the test mode period by counting pulses of a clock (Fig. 5 and [0044] describes sample period (e.g., during a time interval 502). Fig. 10A and [0060] describes ArmSample generator 1056 may be configured to generate a sampling signal ArmSample, which may alternate between a low logic level and a high logic level);
an active counting circuit configured to generate an operation control signal when the input count of the active command from a point of time that a first pulse of the period signal is input to a point of time that a second pulse of the period signal is input is equal to or more than the preset count (Fig. 10A and [0062]-[0063] describes Controller 1050 may be configured to receive active signal ACT. According to various embodiments of the present disclosure, controller 1050, which may include logic such as one or more flip-flops and/or one or more counters 1051, may be configured to count a number of times an active signal ACT is received at the associated memory bank. More specifically, controller 1050 may be configured to count a number of times active signal ACT is received at the associated memory bank during a time interval (e.g., a steal series). In these embodiments, counters 1051 may be reset (e.g., via control logic) (e.g., at the end of the time interval). Further, based on the number of times active signal ACT is received at the associated memory bank (e.g., during the time interval), controller 1050 may generate a signal that is conveyed to RHR state control 1052); and
a refresh information generation circuit configured to generate the refresh information for adjusting the input period of the refresh command, on the basis of the operation control signal ([0064] describes RHR state control 1052 may receive a signal from controller 1050 indicating whether or not a row hammer refresh operation should occur at the memory bank and/or at what rate a row hammer refresh should occur).
Regarding claim 3, Lee discloses all the elements of claim 2 as above and further the active counting circuit comprises:
a counter configured to generate a counting signal by counting the number of times that the active command is input, from the point of time that the first pulse of the period signal is input to the point of time that the second pulse of the period signal is input (Fig. 10A and [0062]-[0063]); and
a comparison circuit configured to generate the operation control signal by comparing the counting signal and a comparison signal ([0080] and claim 13 describes one controller is configured to adjust the row hammer refresh rate of at least one memory bank in response to a comparison of the amount of activity associated with the at least one memory bank to a threshold amount of activity).
Regarding claim 4, Lee discloses all the elements of claim 1 as above and further the refresh control circuit (Fig. 10A) comprises:
an active counting circuit configured to generate an operation control signal when the input count of the active command from a point of time that a first pulse of the refresh command is input to a point of time that a second pulse of the refresh command is input is equal to or more than the preset count (Fig. 10A and [0062]-[0063] describes Controller 1050 may be configured to receive active signal ACT. According to various embodiments of the present disclosure, controller 1050, which may include logic such as one or more flip-flops and/or one or more counters 1051, may be configured to count a number of times an active signal ACT is received at the associated memory bank. More specifically, controller 1050 may be configured to count a number of times active signal ACT is received at the associated memory bank during a time interval (e.g., a steal series). In these embodiments, counters 1051 may be reset (e.g., via control logic) (e.g., at the end of the time interval). Further, based on the number of times active signal ACT is received at the associated memory bank (e.g., during the time interval), controller 1050 may generate a signal that is conveyed to RHR state control 1052); and
a refresh information generation circuit configured to generate the refresh information for adjusting the input period of the refresh command, on the basis of the operation control signal ([0064] describes RHR state control 1052 may receive a signal from controller 1050 indicating whether or not a row hammer refresh operation should occur at the memory bank and/or at what rate a row hammer refresh should occur).
Regarding claim 5, Lee discloses all the elements of claim 4 as above and further the active counting circuit comprises:
a counter configured to generate a counting signal by counting the number of times that the active command is input, from the point of time that the first pulse of the refresh command is input to the point of time that the second pulse of the refresh command is input (Fig. 10A and [0062]-[0063]); and
a comparison circuit configured to generate the operation control signal by comparing the counting signal and a comparison signal ([0080] and claim 13 describes one controller is configured to adjust the row hammer refresh rate of at least one memory bank in response to a comparison of the amount of activity associated with the at least one memory bank to a threshold amount of activity).
Regarding independent claim 6, Lee discloses a refresh period control method (Figs. 10A, 12) comprising:
resetting the input count of an active command, when a pulse of a period signal for setting a test mode period is generated; detecting the input count of the active command, before the input count is reset (Fig. 12 and [0078] describes one or more counters within a memory bank and/or external to the memory bank may count the number of active signals received at the memory bank during the time interval. Further, in this example, the one or more counters may be reset upon completion of the time interval); and
adjusting the input period of a refresh command when the input count of the active command is equal to or more than a preset count ([0062] describes controller 1050 may be configured to count a number of times active signal ACT is received at the associated memory bank during a time interval (e.g., a steal series). In these embodiments, counters 1051 may be reset (e.g., via control logic) (e.g., at the end of the time interval). Further, based on the number of times active signal ACT is received at the associated memory bank (e.g., during the time interval), controller 1050 may generate a signal that is conveyed to RHR state control 1052. [0063] describes controller 1050 may be configured to count a number of active signals, and convey this information to RHR state control 1052. In these embodiments, RHR state control 1052 may be configured to determine whether or not a row hammer refresh operation should occur at the memory bank and/or at what rate a row hammer refresh should occur. Fig. 12 shows the flow diagram).
Claim 7 recites the same claim limitations of device claims in method format and henceforth rejected the same way.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Saifuddin et al. (US 20170316818)
Youn et al. (US 20140355332) --- Fig. 5 and corresponding sections of the Specification.
Watanabe et al. (US 20020080677)
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 1/22/2026