DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note: glass cloth is made from real glass, but it is a flexible textile rather than a rigid, solid object like a window or a drinking glass, and a prepreg material can be made from a glass fabric or woven glass.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 13-14, 20, and 25-26 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Koyanagi (U.S. Patent 9,161,453).
As to claim 1, Koyanagi discloses a printed circuit board (10, column 2, line 39) as shown in figures 1-10 comprising:
a glass layer (core layer 11, column 2, line 51+) having a cavity (11x);
a through-via (11y) having a through-portion penetrating the glass layer (11), and a protrusion portion (the conductor 26 filled into the through hole 11x and protrude out the top surface of the core layer 11, figure 6) protruding upwards from an upper surface (first surface) of the glass layer (11);
an electronic component (12) disposed in the cavity (11x); and
a first insulating layer (13a) filling at least a portion of the cavity (11x), the first
insulating layer (13a) covering at least a portion of the electronic component (12), see
figure 1.
As to claim 13, Koyanagi discloses a printed circuit board (10) as shown in figures 1-10 comprising:
a glass layer (11); and
a through-via (11y) having a through-portion penetrating the glass layer (11), and a protrusion portion (26, figure 6) protruding upwards from an upper surface (a first surface) of the glass layer (11),
wherein, in cross-section, a width of an uppermost side of the through-portion
(11y) is substantially equal to a width of a lowermost side of the protrusion portion (26).
As to claim 20, Koyanagi discloses a printed circuit board (10) as shown in figures 1-10, comprising:
a glass layer (11) having through-holes (11x, 11y) penetrating through the glass layer (11) from an upper surface (first surface) to a lower surface (second surface) thereof, at least one of the through-holes (11y) being filled with a metal (the conductor 26) to form a through-via (11y), the through-via having a protrusion portion (26) extending past the upper surface of the glass layer to form a protrusion (26); and
an electronic component (12) disposed in at least one of the through-holes (11x)
not filled with the metal.
As to claims 2, 14, Koyanagi discloses the through-portion (11y) and the protrusion portion (26) are integrally formed.
As to claim 3, Koyanagi discloses the first insulating layer (13a) is disposed to extend onto a lower surface of the glass layer (11).
As to claim 4, Koyanagi further comprising: a first wiring layer (21) disposed on the first insulating layer (13a); and a first via layer (20y) having at least a portion in contact with the through-via (11y), the first via layer (20y) penetrating at least a portion of the first insulating layer (13a) to connect the first wiring layer and the through-via to each other.
As to claim 5, Koyanagi further comprising in figure 9: a second insulating layer (35) disposed on the first insulating layer (13a or 20); a second wiring layer (36) disposed on the second insulating layer (35); and a second via layer (35x) penetrating at least a portion of the second insulating layer (35) to connect the second wiring layer (36) and the first wiring layer (21) to each other or to connect the second wiring layers to each other.
As to claim 6, Koyanagi discloses the electronic component (12) includes a metal pillar (no label, column 7, lines 1-2, hereafter called MP), and the metal pillar (MP) protrudes toward an upper side of the first insulating layer (62).
As to claim 25, Koyanagi further comprising a first insulating layer (13a) filling at least a portion of the through-hole (11y) in which the electronic component (12) is disposed so as to encapsulate at least a portion of the electronic component (12).
As to claim 26, Koyanagi discloses in figure 3d the first insulating layer (13a) has exposed surfaces substantially coplanar with one or both of the upper and lower surfaces of the glass layer (111b).
Claim(s) 1-7,10-14, 20, and 22-26 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Jeong et al. (U.S. 2022/0007511).
As to claim 1, Jeong discloses a printed circuit board (100B) as shown in figure 3 comprising:
a glass layer (core layer 111b, para-0044) having a cavity (111ah, para-0033);
a through-via (116) having a through-portion penetrating the glass layer (111b), and a protrusion portion (the conductor filled into the through hole 116 and protrude out the top surface of the core layer 111b, figure 3, hereafter called PP) protruding upwards from an upper surface (first surface) of the glass layer (111b);
an electronic component (112b) disposed in the cavity (111ah); and
a first insulating layer (113b) filling at least a portion of the cavity (111ah), the first insulating layer (113b) covering at least a portion of the electronic component (112b), see figure 3.
As to claim 13, Jeong discloses a printed circuit board (100B) as shown in figure 3 comprising:
a glass layer (111b); and
a through-via (116) having a through-portion penetrating the glass layer (111b), and a protrusion portion (the conductor PP) protruding upwards from an upper surface (a first surface) of the glass layer (111b),
wherein, in cross-section, a width of an uppermost side of the through-portion
(116) is substantially equal to a width of a lowermost side of the protrusion portion (PP).
As to claim 20, Jeong discloses a printed circuit board (100B) as shown in figure 3, comprising:
a glass layer (111b) having through-holes (111ah, 116) penetrating through the glass layer (111b) from an upper surface (first surface) to a lower surface (second surface) thereof, at least one of the through-holes (116) being filled with a metal (the conductor PP) to form a through-via (116), the through-via having a protrusion portion (PP) extending past the upper surface of the glass layer to form a protrusion (PP); and
an electronic component (112b) disposed in at least one of the through-holes (111ah) not filled with the metal.
As to claims 2, 14, Jeong discloses the through-portion (116) and the protrusion portion (PP) are integrally formed.
As to claim 3, Jeong discloses the first insulating layer (113b) is disposed to extend onto a lower surface of the glass layer (111b).
As to claim 4, Jeong further comprising:
a first wiring layer (114b) disposed on the first insulating layer (113b); and
a first via layer (133) having at least a portion in contact with the through-via (116), the first via layer (133) penetrating at least a portion of the first insulating layer (113b) to connect the first wiring layer and the through-via to each other.
As to claim 5, Jeong further comprising: a second insulating layer (131) disposed on the first insulating layer (113b);
a second wiring layer (132) disposed on the second insulating layer (131); and a second via layer (133) penetrating at least a portion of the second insulating layer (131) to connect the second wiring layer (132) and the first wiring layer (114b) to each other or to connect the second wiring layers to each other.
As to claim 6, Jeong discloses the electronic component (112b) includes a metal pillar (115b), and the metal pillar (115b) protrudes toward an upper side of the first insulating layer (113b).
As claim 7, Jeong discloses an upper surface of the metal pillar (115b) is substantially coplanar with an upper surface of the through-portion of the through-via (116).
As to claims 10-11, Jeong discloses an upper and lower surfaces of the first
insulating layer (17 or 20) is substantially coplanar with the upper and lower surfaces of the glass layer (11).
As to claim 12, Jeong further comprising: a first wiring layer (114b) having at least a portion disposed on the lower surface of the glass layer (111b), wherein at least a portion of the first wiring layer (114b) is in contact with the through-via (116).
As claim 22, Jeong discloses the electronic component (112b) comprises a metal pillar (115b) extending from of a surface of the electronic component (112b) at least up to a plane coplanar with one or both of the upper surface and the lower surface of the glass layer (116).
As to claim 23, Jeong discloses a semiconductor chip (300) (electrically) connected to the electronic component via the metal pillar.
As to claim 24, Jeong discloses at the protrusion portion (the conductor) of the through-via (116) is electrically connected to the semiconductor chip (IC chip).
As to claim 25, Jeong further comprising a first insulating layer (113b) filling at least a portion of the through-hole (111ah) in which the electronic component (112b) is disposed so as to encapsulate at least a portion of the electronic component (112b).
As to claim 26, Jeong discloses the first insulating layer (113b) has exposed
surfaces substantially coplanar with one or both of the upper and lower surfaces
of the glass layer (111b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9, 15, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong in view of Haba et al. (U.S. Patent 8,878,353).
As claims 9, 15, and 21, Jeong discloses all of the limitations of claimed invention except for a lower surface of the through-via or through-portion is substantially coplanar with the lower surface of the glass layer.
Haba teaches a structure for microelectronic package (10) as shown in figure 3 comprising a lower surface of the through-via or through-portion (24) is substantially coplanar with the lower surface of the encapsulation element/ layer (40A, 40B).
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Haba employed in the PCB of Jeong or Koyanagi in order to provide excellent support for the protrusion formed within the core or encapsulation layer.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong in view of Koyanagi (‘453).
As claim 8, Jeong discloses all of the limitations of claimed invention except for the metal pillar is disposed on each of an upper side and a lower side of the electronic component.
Koyanagi teaches a wiring board (10) as shown in figure 1 comprising the metal pillar (no label, column 7, lines 1-2, hereafter called MP) is disposed on each of an upper side and a lower side of the electronic component (12).
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Koyanagi employed in the PCB of Jeong in order to provide excellent internal electrical connections from the electronic component to external source or other component or device.
Claim(s) 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong in view of Mano et al. (‘033) cited in the record.
As claim 16, Jeong discloses all of the limitations of claimed invention except for the through-via has a substantially upwardly tapered shape.
Mano teaches a printed circuit board (10) as shown in figure 1 comprising the through-via (31) has a substantially upwardly tapered shape.
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Mano employed in the PCB of Jeong in order to provide large contact zone, less resistance, and improve thermal and electrical dissipation under high loads.
As to claim 17, Jeong discloses a cavity (11x, figure 2d) penetrating at least a portion of the glass layer (11), wherein the cavity (11x) has a tapered shape except for the through-via (11y) have a tapered shape in the substantially same direction.
Mano teaches a printed circuit board (10) as shown in figure 1 comprising the through-via (31) has a substantially upwardly tapered shape in the same direction with the cavity.
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Mano employed in the PCB of Jeong in order to provide large contact zone, less resistance, and improve thermal and electrical dissipation under high loads.
As to claim 18, Jeong as modified by Mano discloses an electronic component (12) disposed in the cavity (11x).
Regarding claim 19, Jeong as modified by Mano discloses the electronic component (112b) comprises a metal pillar (115b) extending from of a surface of the electronic component at least up to a plane coplanar with one or both of the upper surface and the lower surface of the glass layer.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
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/TUAN T DINH/Primary Examiner, Art Unit 2847
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