DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 25 is objected to because of the following informalities:
Regarding claim 25, line 4, please, change “at leas” to - - at least - - for correct typo error.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 10-14, 16-18, 20, and 25-26 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Mano et al. (U.S. 2013/0223033).
As to claim 1, Mano discloses a printed circuit board (10, para-0033+) as shown in figures 1-10 comprising:
a glass layer (core base 30 made from prepreg material) having a cavity (20);
a through-via (36, para-0035) having a through-portion (31) penetrating the glass layer (30), and a protrusion portion (31a) protruding upwards from an upper surface of the glass layer (30);
an electronic component (110, para-0034) disposed in the cavity (20); and
a first insulating layer (50) filling at least a portion of the cavity (20), the first insulating layer (50) covering at least a portion of the electronic component (110), see figure 1.
As to claim 2, Mano discloses the through-portion (31) and the protrusion portion (31a) are integrally formed.
As to claim 3, Mano discloses the first insulating layer (50) is disposed to extend onto a lower surface (by element 50B) of the glass layer (30).
As to claim 4, Mano further comprising: a first wiring layer (58B) disposed on the first insulating layer (50B); and a first via layer (60B) having at least a portion in contact with the through-via (36), the first via layer (60B) penetrating at least a portion of the first insulating layer (50B) to connect the first wiring layer and the through-via to each other.
As to claim 5, Mano further comprising: a second insulating layer (50D) disposed on the first insulating layer (50B); a second wiring layer (58D) disposed on the second insulating layer (50D); and a second via layer (60D) penetrating at least a portion of the second insulating layer (50D) to connect the second wiring layer (58D) and the first wiring layer (58B) to each other or to connect the second wiring layers to each other.
As to claims 10-11, Mano discloses an upper and lower surfaces of the first insulating layer (50) is substantially coplanar with the upper and lower surfaces (F, S) of the glass layer (30).
As to claim 12, Mano further comprising: a first wiring layer (58B) having at least a portion disposed on the lower surface of the glass layer, wherein at least a portion of the first wiring layer is in contact with the through-via (36).
As to claim 13, Mano discloses a printed circuit board (10, para-0033+) as shown in figures 1-10 comprising:
a glass layer (30); and
a through-via (36) having a through-portion (31) penetrating the glass layer (30), and a protrusion portion (31a) protruding upwards from an upper surface of the glass layer,
wherein, in cross-section, a width of an uppermost side of the through-portion (31) is substantially equal to a width of a lowermost side of the protrusion portion (31a).
As to claim 14, Mano discloses the through-portion (31) and the protrusion portion (31a) are integrally formed.
As to claim 16, Mano discloses the through-via (36) has a substantially upwardly tapered shape.
As to claim 17, Mano further comprising: a cavity (20) penetrating at least a portion of the glass layer (30), wherein the cavity (20) and the through-via (36) have a tapered shape in the substantially same direction.
As to claim 18, Mano further comprising an electronic component (110) disposed in the cavity (20).
As to claim 20, Mano discloses a printed circuit board, comprising:
a glass layer (30) having through-holes (36) penetrating through the glass layer from an upper surface (F) to a lower surface (S) thereof, at least one of the through-holes (36) being filled with a metal (conductor) to form a through-via (31), the through-via having a protrusion portion (31a) extending past the upper surface (F) of the glass layer to form a protrusion; and
an electronic component (110) disposed in at least one of the through-holes (20) not filled with the metal.
As to claim 25, Mano further comprising a first insulating layer (50) filling at least a portion of the through-hole (20) in which the electronic component (110) is disposed so as to encapsulate at least a portion of the electronic component.
As to claim 26, Mano discloses the first insulating layer (50) has exposed surfaces substantially coplanar with one or both of the upper and lower surfaces (F, S) of the glass layer (30).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-7, 9, 15, 19, and 21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mano (‘033)99 in view of Ito et al. (U.S. Patent 8,101,868).
Regarding claim 6, Mano discloses all of the limitations of claimed invention except for the electronic component includes a metal pillar, and the metal pillar protrudes toward an upper side of the first insulating layer.
Ito teaches a multilayer printed circuit board (PCB) as shown in figures 4-6 comprising the electronic component (55) includes a metal pillar (78), and the metal pillar protrudes toward an upper side of the first insulating layer (62).
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Ito employed in the PCB of Mano in order to provide an electrical connection between the component to an external device.
Regarding claim 7, Mano as modified by Ito teaches an upper surface of the metal pillar (78) is substantially coplanar with an upper surface of the through-portion of the through-via (39).
Regarding claims 9, 15, Mano discloses all of the limitations of claimed invention except for a lower surface of the through-via is substantially coplanar with a lower surface of the glass layer.
Ito teaches a multilayer printed circuit board (PCB) as shown in figures 4-6 comprising a lower surface of the through-via (39) is substantially coplanar with a lower surface of the glass layer (32).
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Ito employed in the PCB of Mano in order to provide excellent bonding surface for electrical connection structure.
Regarding claim 19, Mano discloses all of the limitations of claimed invention except for the electronic component comprises a metal pillar extending from of a surface of the electronic component at least up to a plane coplanar with one or both of the upper surface and the lower surface of the glass layer.
Ito teaches a multilayer printed circuit board (PCB) as shown in figures 4-6 comprising the electronic component (55) includes a metal pillar (78), and the metal pillar (78) extending from of a surface of the electronic component (55) at least up to a plane coplanar with one or both of the upper surface and the lower surface of the glass layer.
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Ito employed in the PCB of Mano in order to provide an electrical connection between the component to an external device.
Regarding claim 21, Mano discloses all of the limitations of claimed invention except for a lower surface of the through-via is substantially coplanar with a lower surface of the glass layer.
Ito teaches a multilayer printed circuit board (PCB) as shown in figures 4-6 comprising a lower surface of the through-via (39) is substantially coplanar with a lower surface of the glass layer (32).
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Ito employed in the PCB of Mano in order to provide excellent bonding surface for electrical connection structure.
Regarding claim 22, Mano discloses all of the limitations of claimed invention except for the electronic component comprises a metal pillar extending from of a surface of the electronic component at least up to a plane coplanar with one or both of the upper surface and the lower surface of the glass layer.
Ito teaches a multilayer printed circuit board (PCB) as shown in figures 4-6 comprising the electronic component (55) includes a metal pillar (78), and the metal pillar (78) extending from of a surface of the electronic component (55) at least up to a plane coplanar with one or both of the upper surface and the lower surface of the glass layer.
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Ito employed in the PCB of Mano in order to provide an electrical connection between the component to an external device.
As to claim 23, Mano as modified by Ito discloses a semiconductor chip (IC, not label, para-0038+) connected to the electronic component via the metal pillar.
As to claim 24, Mano as modified by Ito discloses at the protrusion portion (31a) of the through-via (36) is connected to the semiconductor chip (IC chip).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mano (‘033) in view of Ito et al. (U.S. Patent 8,101,868), and further in view of Verhaverbake et al. (U.S. Patent 11,521,937).
As to claim 8, Mano as modified by Ito discloses all of the limitations of claimed invention except for the metal pillar is disposed on each of an upper side and a lower side of the electronic component.
Verhaverbake teaches package structures as shown in figures 8I-8J comprising the metal pillar (844) is disposed on each of an upper side and a lower side of the electronic component (626).
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Verhaverbake employed in the PCB of Mano and Ito in order to provide internal electrical connections.
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/TUAN T DINH/Primary Examiner, Art Unit 2847
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