Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application CN 202410985300.3 filed on 07/22/2024 The foreign application is not in English. The certified copy of the foreign priority application has been received. Filing Dates for the Claims — All Claims Not Entitled to Priority DateTo be entitled to the filing date of the foreign priority application JP 2021108104 that is not in English, an English translation of the non-English language foreign application and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Claim Rejections 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 8, 10, 11, 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US Pub. 20240170048), hereinafter referred to as Kim
Regarding claim 1, Kim teaches a semiconductor device, comprising: a control semiconductor structure (Kim, 3100F, Fig. 30, PREG, Fig. 31 paras. 227, 249); and array semiconductor structures (Kim, CREG1, GREG2, Fig. 31, para. 237) stacked along a first direction and coupled to the control semiconductor structure, wherein the array semiconductor structures comprise at least: a first array semiconductor structure (Kim, CREG1, Fig. 31) comprising: a first array region (Kim, BLBA, Fig. 31m para. 238) and a first connection region (Kim, WLBA, Fig. 31, para. 238, this also includes the area of PA that includes 5360 and 5460, see diagram below) adjacent to the first array region along a second direction perpendicular to the first direction; a first stack of conductive layers (Kim, 5330, Fig. 31, para. 242) and isolating layers (Kim, 5215, Fig. 31, para. 239) alternating with each other along the first direction; a first interconnect layer (Kim, Fig. 31, see diagram below); first bit lines (Kim, 5360c, Fig. 31, para. 243) in the first array region; first bit line connection structures (Kim, THV1, Fig. 31, para. 243) in the first array region, wherein the first bit line connection structures are coupled to the first bit lines and extend through the first stack along the first direction (Kim, Fig. 31, para. 248); first word line contact structures (Kim, 5340, Fig. 31, para. 250) extending along the first direction in the first connection region; and first word line connection structures (Kim, 5348, Fig. 31, para. 252) extending through the first stack along the first direction in the first connection region; and a second array semiconductor structure (Kim, CREG2, Fig. 31, para. 237) comprising: a second interconnect layer (Kim, Fig. 31, see diagram below); second bit lines (Kim, 5460c, Fig. 31) coupled to the first bit line connection structures through the second interconnect layer and second word line contact structures (Kim, 5440, Fig. 31, para. 252) extending along the first direction and being coupled to the first word line connection structures through the second interconnect layer.
Regarding claim 2, Kim teaches the semiconductor device of claim 1, wherein: one of the first bit line connection structures (Kim, THV1, Fig. 31) is coupled to a corresponding first bit line (Kim, 5360c, Fig. 31,) of the first bit lines and a corresponding second bit line (Kim, 5460, Fig. 19) of the second bit lines, and the corresponding first bit line of the first bit lines and the corresponding second bit line of the second bit lines are aligned along the first direction (Kim, Fig. 31); and one of the first word line connection structures (Kim, 5348, Fig. 31) is coupled to a corresponding second word line contact structure (Kim, 5441, Fig. 31, para. 252) of the second word line contact structures.
Regarding claim 3, modified Kim teaches the semiconductor device of claim 1, wherein the control semiconductor (Kim, PREG, Fig. 31) structure is bonded to the first array semiconductor structure (Kim, CREG1, Fig. 31) through a first bonding structure (Kim, 5272a, 5372a, 5370b, 5270b, 5270c, 5370c, Fig. 31, paras. 249, 250, 254), and the first array semiconductor structure is bonded to the second array semiconductor structure (Kim, CREG2, Fig. 31) through a second bonding structure (Kim, 5371e, 5472a, 5472d, 5372d, Fig. 31, paras. 248, 254).
Regarding claim 4, Kim teaches the semiconductor device of claim 1, wherein the first array semiconductor structure further comprises a first conductive structure (Kim, 5304, Fig. 31, para. 257) outside the first array region and the first connection region, the first conductive structure is coupled to the control semiconductor structure through the first interconnect layer (Kim, Fig. 31, see diagram) the second array semiconductor structure further comprises a second conductive structure (Kim, 5404, Fig. 31, para. 257), the second conductive structure is coupled to the first conductive structure through the second interconnect layer (Kim, Fig. 31, see diagram), and the second conductive structure is aligned with the first conductive structure along the first direction (Kim, Fig. 31).
Regarding claim 8, Kim teaches the semiconductor device of claim 1, wherein the first word line connection structures and the first word line contact structures are arranged along a line extending in the second direction (Kim, Fig. 31), the first word line connection structures are next to each other, and the first word line contact structures are next to each other (Kim Fig. 31).
Regarding claim 10, Kim teaches the semiconductor device of claim 1, wherein the first word line connection structures are arranged along a first line extending in the second direction (Kim, Fig. 31), the first word line contact structures are arranged along a second line extending in the second direction (Kim, Fig. 31), and the first word line connection structures are adjacent to the first word line contact structures along a third direction perpendicular to the first direction and the second direction (Kim, Fig. 31).
Regarding claim 11, Kim teaches the semiconductor device of claim 1, wherein the control semiconductor structure comprises: page buffer circuits (Kim, 3120, Fig. 30, para. 227),
wherein one of the page buffer circuits is coupled to a corresponding first bit line of the first bit lines and a corresponding second bit line of the second bit lines (Kim, para. 231), the corresponding first bit line of the first bit lines is coupled to the corresponding second bit line of the second bit lines through a first bit line connection structure of the first bit line connection structures (Kim, paras. 247-248); first string drivers coupled to the first word lines contact structures (Kim, 3110, Fig. 30, paras 227, 139); and second string drivers coupled to the second word lines contact structures through the first word line connection structures (Kim, 3110, Fig. 30, para. 227, 139).
Regarding claim 17, Kim teaches a method for forming a semiconductor device, comprising: forming a first array semiconductor structure (Kim, CREG1, Fig. 31, para. 227) of the semiconductor device, wherein the first array semiconductor structure comprises: a first array region (BLBA, Fig. 31, para.238) and a first connection region (Kim, WLBA, Fig. 31, para. 238) adjacent to the first array region along a second direction perpendicular to a first direction; a first stack of conductive layers (Kim, 5330, Fig. 31, para. 242) and isolating layers (Kim, 5215, Fig. 31, para. 239) alternating with each other along the first direction; a first interconnect layer (Kim, Fig. 31, see diagram below); and first bit lines (Kim, 5360c, Fig. 31, para. 243) in the first array region; forming a second array semiconductor structure (Kim, CREG, Fig. 31, para. 237) of the semiconductor device, wherein the second array semiconductor structure comprises: a second interconnect layer (Kim, Fig. 31, see diagram below); and second bit lines (Kim, 5460c, Fig. 31);
forming a control semiconductor structure (Kim, 3100F, Fig. 30m PREG, Fig. 31, Figs 227, 249) of the semiconductor device, wherein the control semiconductor structure comprises peripheral circuits configured to control the first array semiconductor structure and the second array semiconductor structure (Kim, para. 227); and stacking the control semiconductor structure, the first array semiconductor structure, and the second array semiconductor structure along the first direction (Kim, Fig. 31).
Regarding claim 18, Kim teaches the method of claim 17, further comprising: bonding the control semiconductor structure (Kim, PREG, Fig. 31) to the first array semiconductor structure (Ki, CREG1, Fig. 31) using a first bonding structure (Kim, 5272a, 5372a, 5370b, 5270b, 5270c, 5370c, Fig. 31, paras. 249, 250, 254); and bonding the first array semiconductor structure to the second array semiconductor structure (Kim, CREG2, Fig. 31) using a second bonding structure (Kim, 5371e, 5472a, 5472d, 5372d, Fig. 31, paras. 248, 254).
Regarding claim 19, Kim teaches the method of claim 17, wherein forming the first array semiconductor structure comprises forming: first bit line connection structures (Kim, THV1, Fig. 31, paras. 247248) in the first array region, wherein the first bit line connection structures are coupled to the first bit lines and extend through the first stack along the first direction (Kim, Fig. 31), and the first bit line connection structures are coupled to the second bit lines (Kim, Fig. 31, THV! Couples to 5460c); first word line contact structures (Kim, 5340, Fig. 31, para. 250) extending along the first direction in the first connection region; and first word line connection structures (Kim, 5348, 5350a, 5360a, Fig. 31, para. 225) extending through the first stack along the first direction in the first connection region; and wherein forming the second array semiconductor structure comprises forming second word line contact structures (Kim, 5440, Fig. 31, para. 252) extending along the first direction, wherein the second word line contact structures are configured to be coupled to the first word line connection structures through the second interconnect layer (Ki, Fig. 31, para.252, (5348 is coupled to 5441).
Regarding claim 20, Kim teaches the method of claim 19, wherein the first word line connection structures and the first word line contact structures are arranged along a line extending in the second direction (Kim, Fig. 31), the first word line connection structures are next to each other (Kim, Fig. 31), and the first word line contact structures are next to each other (Kim, Fig. 31).
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Claim Rejections 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim.
Regarding claim 12, Kim teaches a semiconductor device, comprising: a control semiconductor structure (Kim, 3100F, Fig. 30, PREG, Fig. 31 paras. 227, 249); and array semiconductor structures stacked along a first direction and coupled to the control semiconductor structure (Kim, CREG1, GREG2, Fig. 31, para. 237); wherein the array semiconductor structures comprise at least a first array semiconductor structure (Kim, CREG1, Fig. 31, para. 237), a second array semiconductor structure (Kim, GREG2, Fig. 31, para. 237), and a third array semiconductor structure (Kim, para. 237, Fig. 31 shows only two upper chips (CREG1, CREG2. However, as para. 237 describes the number of upper chips as not thereto limited), and wherein: the first array semiconductor structure comprises: a first array region (Kim, BLBA, Fig. 31m para. 238) and a first connection region (Kim, WLBA, Fig. 31, para. 238, this also includes the area of PA that includes 5360 and 5460, see diagram below) adjacent to the first array region along a second direction perpendicular to the first direction; a first stack of conductive layers (Kim, 5330, Fig. 31, para. 242) and isolating layers (Kim, 5215, Fig. 31, para. 239) alternating with each other along the first direction; a first interconnect layer (Kim, Fig. 31, see diagram below); first bit lines (Kim, 5360c, Fig. 31, para. 243) in the first array region; first bit line connection structures (Kim, THV1, Fig. 31, para. 243)in the first array region, wherein the first bit line connection structures are coupled to the first bit lines and extend through the first stack along the first direction (Kim, Fig. 31, para. 248); first word line contact structures (Kim, 5340, Fig. 31, para. 250) extending along the first direction in the first connection region; and first word line connection structures (Kim, 5348, Fig. 31, para. 252) extending through the first stack along the first direction in the first connection region; the second array semiconductor structure comprises: a second array region (Kim, BLBA, Fig. 31m para. 238) and a second connection region (Kim, WLBA, Fig. 31, para. 238, this also includes the area of PA that includes 5360 and 5460, see diagram below) adjacent to the second array region along the second direction; a second stack of conductive layers (Kim, 5430, Fig. 31, para. 242) and isolating layers (Kim, 5415, Fig. 31, para. 258) alternating with each other along the first direction; a second interconnect layer (Kim, Fig. 31, see diagram); second bit lines (Kim, 6460c, Fig. 31) in the second array region, wherein the second bit lines are coupled to the first bit line connection structures (Ki, Fig. 31, coupled through 5372d and 5472d); second bit line connection structures (Kim, THV2, Fig. 31, paras 247-248) in the second array region, wherein the second bit line connection structures are coupled to the second bit lines and extend through the second stack along the first direction (Kim, Fig. 31); second word line contact structures (Kim, 5440, Fig. 31, para 252) extending along the first direction in the second connection region and being coupled to a first set of the first word line connection structures through the second interconnect layer.
Kim does not explicitly teach second word line connection structures extending through the second stack along the first direction in the second connection region and being coupled to a second set of the first word line connection structures through the second interconnect layer;
the third array semiconductor structure comprises: a third interconnect layer; third bit lines coupled to the second bit line connection structures; and third word line contact structures extending along the first direction and being coupled to the second word line connection structures through the third interconnect layer; and a quantity of the first word line connection structure is equal to or greater than a sum of a quantity of the second word line contact structures and a quantity of the third word line contact structures.
However, Kim, in para. 237 states “as illustrated in FIG. 31, the memory device 5000 may include two upper chips. However, the number of the upper chips is not limited thereto.” Therefore, it would have been obvious to one having ordinary skill in the art before the filing date of the invention to have added a third upper chip (i. e. CREG3) with similar structure to CREG1 and 2 and with similar interconnection and bonding regions as well as similar connections between CREG2 and CREG2 in order to increase integration degree and memory capacity (Kim, para. 4). Such a structure would require a word line connection structure running from CREG1 through CREG2 to CREG3 and a bit line connection structure running though CREG1, CREG2 and CREG3. This would have placed 3 word line connection structures in CREG1, 2 in CREG2 and 1 in CREG3.
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Regarding claim 13, Kim teaches the semiconductor device of claim 12, wherein the first array semiconductor structure further comprises a first conductive (Kim, 5304, Fig. 31, para. 257) structure outside the first array region and the first connection region, the first conductive structure is coupled to the control semiconductor structure though the first interconnect layer (Kim, Fig 31), the second array semiconductor structure further comprises a second conductive structure (Kim, 5404, Fig. 31, para. 257) outside the second array region and the second connection region, the second conductive structure is coupled to the first conductive structure through the second interconnect layer, the third array semiconductor structure further comprises a third conductive structure coupled to the second conductive structure through the third interconnect layer (Kim, para. 237, states the number of upper chips is not limited to 2. Because the chips would have similar structures and interconnections the third chip would have a third conductive structure), and the first conductive structure, the second conductive structure, and the third conductive structure are aligned along the first direction (Kim, Fig. 31, shows that the first and second conductive structure are aligned along the first direction, therefore it is reasonable to expect the third conductive structure implied by para. 237 to be similarly aligned).
Regarding claim 15, Kim teaches the semiconductor device of claim 12, wherein the control semiconductor structure comprises: page buffer circuits (Kim, 3120, Fig. 30, para. 227),
wherein one of the page buffer circuits is coupled to a corresponding first bit line of the first bit lines, a corresponding second bit line of the second bit lines, and a corresponding third bit line of the third bit lines (Kim, paras. 231, 232, 237), wherein the corresponding first bit line of the first bit lines is coupled to the corresponding second bit line of the second bit lines through a first bit line connection structure of the first bit line connection structures, and the corresponding second bit line of the second bit lines is coupled to the corresponding third bit line of the third bit lines through a second bit line connection structure of the second bit line connection structures (Kim, THV1, THV2, Fig. 31, paras. 237, 247-248); first string drivers (Kim, 3110, Fig. 30, paras 139, 227) coupled to the first word lines contact structures; second string drivers coupled to the second word lines contact structures through the first set of the first word line connection structures (Kim, 3110, Fig. 30, paras. 139, 227); and third string drivers coupled to the third word lines contact structures through the second set of the first word line connection structures and the second word line connection structures (Kim, 3110, Fig. 30, paras. 139, 227, 237).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 4 above, and further in view of Chen (US. Pub. 20220208705) hereinafter referred to as Chen.
Regarding claim 5, Kim teaches he semiconductor device of claim 4, but does not teach wherein the first array semiconductor structure further comprises a third interconnect layer, the first stack is between the first interconnect layer and the third interconnect layer along the first direction, and the first bit line connection structures, the first word line connection structures, and the first conductive structure are coupled between the first interconnect layer and the third interconnect layer.
However, Chen teaches a memory device (Chen, 199, Fig. 19, para. 64) with a semiconductor layer (Chen, 131, Fig. 19, para. 46) that provides interconnection between vias (Chen 174, 175, Fig. 19, paras.51-53).
Therefore, it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the dielectric layers of Chen with the structures of Kim in order to provide for hydrogen diffusion for defect repair (Chen, para. 75).
Allowable Subject Materia
Regarding claim 6, Kim teaches the semiconductor device of claim 4, wherein: the first array semiconductor structure comprises a first peripheral region (Kim, PA, Fig. 31, see diagram below) adjacent to the first array region and the first connection region along a third direction perpendicular to the first direction and the second direction, wherein the first conductive structure is in the first peripheral region (Kim, Fig. 31); and the first array region comprises a center region and an edge region arranged along the third direction (Kim, Fig. 31, see diagram below), wherein the edge region is in one side of the first array region along the third direction (Kim, Fig. 31), the first bit line connection structures are in the edge region (Kim, Fig. 31).
Kim does not teach, not does the prior art of record suggest and the center region is between the edge region and the first peripheral region along the third direction.
Regarding claim 7, Kim teaches the semiconductor device of claim 4, wherein: the first array semiconductor structure comprises a first peripheral region (Kim, PA, Fig. 31, see diagram below) adjacent to the first array region and the first connection region along a third direction perpendicular to the first direction and the second direction, wherein the first conductive structure is in the first peripheral region (Kim, Fig. 31).
Kim does not teach, nor does the prior art of record suggest wherein the first array region comprises a center region, a first edge region, and a second edge region arranged along the third direction, wherein the first edge region and the second edge region are in two opposite sides of the first array region along the third direction, a first set of the first bit line connection structures are in the first edge region, a second set of the first bit line connection structures are in the second edge region, the center region is between the first edge region and the second edge region along the third direction, and the second edge region is between the center region and the first peripheral region along the third direction.
Regarding claim 9, Kim teaches the semiconductor device of claim 1, wherein the first word line connection structures and the first word line contact structures are arranged along a line extending in the second direction.
Kim does not teach, nor does the prior art of record suggest wherein each of the first word line connection structures is next to a corresponding first word line contact structure of the first word line contact structures.
Regarding claim 14, Kim teaches the semiconductor device of claim 13, wherein: the first array semiconductor structure comprises a first peripheral region (Kim, PA, Fig. 31, see diagram below) adjacent to the first array region and the first connection region along a third direction perpendicular to the first direction and the second direction, and the first conductive structure is in the first peripheral region (Kim, Fig. 31);
Kim does not teach, nor does the prior art of record suggest and the first array region comprises a center region and an edge region arranged along the third direction, the edge region is in one side of the first array region along the third direction, the first bit line connection structures are in the edge region, and the center region is between the edge region and the first peripheral region along the third direction.
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Regarding claim 16, Kim teaches the semiconductor device of claim 12, wherein the first set of the first word line connection structures are arranged along a first line extending in the second direction (Kim, Fig. 31), the second set of the first word line connection structures are arranged along a second line extending in the second direction (Kim, para. 237 demonstrates additional word line connection which would have been used to connect to a theoretical CREG3, and which would have extended in the first direction), the first word line contact structures are arranged along a third line extending in the second direction (Kim, Fig. 31).
Kim does not teach, nor does the prior art of record suggest the first word line contact structures are between the first set of the first word line connection structures and the second set of the first word line connection structures along a third direction perpendicular to the first direction and the second direction.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Okina (US Pub. 20220189984) teaches a memory device with two tiers and a control circuit wherein the control circuit is bonded through a silicon nitride layer, and the two tires are bonded through an inter-tier dielectric layer.
Maejima (US Pub 20250014643) teaches a memory device with two memory layers and a CMOS control layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:30-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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